/* setup.scr v1 Frank Berndt
 * setup for compile;
 * read files and constraints to prepare pre-compile db;
 */

/*
 * read verilog, link and check rtl;
 * save into rtl db to avoid lengthy re-reads;
 */
include ./script/read_verilog.scr > ./report/rtl.read
current_design = bb
link > ./report/rtl.link
check_design > ./report/rtl.check
write -h -o db/rtl.db
write -f verilog -h -o ./gate/rtl.v

/*
 * include common scripts from NEC;
 */
include ../common/MUX_SCAN.scr
include ../common/set_wire_load.scr

/*
 * include our scripts;
 * these override any previous settings;
 */
include ./script/global.scr
include ./script/io.scr
include ./script/ddr.scr
include ./script/fixes.scr

/*
 * flatten rdp, rsp and vi;
 * do not uniquify, jlib was creating 1000s of modules;
 */
current_design = rdp
ungroup -all -flatten
current_design = rsp
ungroup -all -flatten
current_design = vi
ungroup -all -flatten
current_design = bb

/*
 * report constraints, clocks and port;
 */
report_constraint -verbose > ./report/constraints
report_clock > ./report/clocks
report_port > ./report/ports
report_timing_requirements -attributes -ignored > ./report/timing.req

/*
 * report status before compilation;
 */
report -area > ./report/pre.area
report -cell > ./report/pre.cell
report -hier -full > ./report/pre.hier
check_design > ./report/pre.check
write -h -o ./db/pre.db
write -f verilog -h -o ./gate/pre.v

/*
 * uniquify design;
 * save uniquified db and netlist;
 * quit tool, compile.scr starts fresh from db;
 */
uniquify_naming_style = "bb%s_%d"
uniquify > report/pre.uniquify
write -h -o ./db/uniq.db
write -f verilog -h -o ./gate/uniq.v

quit