pllx2.tcl
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# PLL Offset/Jitter ( ABPLSSCH Specification ) -------------------
####set offset_minus 0.060
####set offset_plus 0.120
####set jitter_minus 0.100
####set jitter_plus 0.100
# Disalble Timing Arc from lib -----------------------------------
set_disable_timing -from ATBI0 -to CLKOA analog/ABPLSSCH
set_disable_timing -from ATBI0 -to CLKOB analog/ABPLSSCH
set_disable_timing -from ATBI0 -to CLKOC analog/ABPLSSCH
# Get delay from PAD_SYSCLK to pllx2/RCLK ------------------------
set in_to_pll_path_max \
[ get_timing_paths \
-from [get_ports PAD_SYSCLK] \
-to [get_pins pllx2/RCLK] \
-delay max_rise \
]
set indelay_pll_max \
[ get_attribute $in_to_pll_path_max arrival ]
set in_to_pll_path_min \
[ get_timing_paths \
-from [get_ports PAD_SYSCLK] \
-to [get_pins pllx2/RCLK] \
-delay min_rise \
]
set indelay_pll_min \
[ get_attribute $in_to_pll_path_min arrival ]
# Get delay from pllx2/CLKOA to pllx2/CLKI -----------------------
# PLL adjusts phase of RCLK and CLKI -----------------------------
set feedback_pll_path_max \
[ get_timing_paths \
-from [get_pins pllx2/CLKOA] \
-to [get_pins pllx2/CLKI] \
-delay max_rise \
]
set pll_feedback_delay_max \
[ get_attribute $feedback_pll_path_max arrival ]
set_clock_latency -source -late \
[ expr $indelay_pll_max - $pll_feedback_delay_max ] \
[ get_clocks MEMCLK ]
set feedback_pll_path_min \
[ get_timing_paths \
-from [get_pins pllx2/CLKOA] \
-to [get_pins pllx2/CLKI] \
-delay min_rise \
]
set pll_feedback_delay_min \
[ get_attribute $feedback_pll_path_min arrival ]
set_clock_latency -source -early \
[ expr $indelay_pll_min - $pll_feedback_delay_min ] \
[ get_clocks MEMCLK ]