[DEVICE]
Family = lc4k;
PartType = LC4032V;
Package = 48TQFP;
PartNumber = LC4032V-75T48C;
Speed = -7.5;
Operating_condition = COM;
EN_Segment = Yes;
Pin_MC_1to1 = No;
Default_Device_Io_Types=LVCMOS18,-;
Voltage = 5.0;

[REVISION]
RCS = "$Revision: 1.1 $";
Parent = lc4k32.lci;
Design = ;
DATE = 10/27/2003;
TIME = 14:59:35;
Source_Format = Schematic_Verilog_HDL;
Type = ;
Pre_Fit_Time = ;

[IGNORE ASSIGNMENTS]
Pin_Assignments = No;
Pin_Keep_Block = No;
Pin_Keep_Segment = No;
Group_Assignments = No;
Macrocell_Assignments = No;
Macrocell_Keep_Block = No;
Macrocell_Keep_Segment = No;
Pin_Reservation = No;
Block_Reservation = No;
Segment_Reservation = No;
Timing_Constraints = No;
IO_Types = No;

[CLEAR ASSIGNMENTS]
Pin_Assignments = No;
Pin_Keep_Block = No;
Pin_Keep_Segment = No;
Group_Assignments = No;
Macrocell_Assignments = No;
Macrocell_Keep_Block = No;
Macrocell_Keep_Segment = No;
Pin_Reservation = No;
Block_Reservation = No;
Segment_Reservation = No;
Timing_Constraints = No;
IO_Types = No;

[BACKANNOTATE ASSIGNMENTS]
Pin_Assignment = No;
Pin_Block = No;
Pin_Macrocell_Block = No;
Routing = No;
Io_Types = No;

[GLOBAL CONSTRAINTS]
Max_Fanin = 24;
Max_PTerm_Split = 80;
Max_PTerm_Collapse = 16;
Max_Pin_Percent = 100;
Max_Macrocell_Percent = 100;
Max_GLB_Input_Percent = 100;
Logic_Reduction = Yes;
XOR_Synthesis = Yes;
Keep_XOR = No;
DT_Synthesis = Yes;
Node_Collapse = Yes;
Speed = FMAX;
Fmax_Logic_Level = 1;
Use_CE = Yes;
Use_Internal_COM_FB = Yes;
Set_Reset_Swap = No;
Clock_Optimize = No;
EN_Set_Reset_Dont_Care = No;
TOE_AS_IO = No;
Set_Reset_Dont_Care = No;
EN_In_Reg_Optimize = No;
In_Reg_Optimize = Yes;
Run_Time = 0;
Routing_Attempts = 2;
Balanced_Partitioning = Yes;
Spread_Placement = Yes;
Usercode = ;
Usercode_Format = HEX;
Vcc = ;
Dual_Function_Macrocell = 1;
Global_PTOE = Yes;
Hard_Fast_Bypass = No;
Fitter_Effort_Level = LOW;

[LOCATION ASSIGNMENTS]
// Block A
D0=pin,48,-,A,4;
reg_cnt_3_=node,-,-,A,3;
reg_cnt_2_=node,-,-,A,9;
// Block B
CEO=pin,24,-,B,4;
reg_cnt_9_=node,-,-,B,0;
reg_cnt_8_=node,-,-,B,1;
reg_cnt_7_=node,-,-,B,5;
reg_cnt_1_=node,-,-,B,3;
reg_cnt_0_=node,-,-,B,7;
reg_cnt_6_=node,-,-,B,9;
reg_cnt_5_=node,-,-,B,12;
reg_cnt_4_=node,-,-,B,2;
// Input/Clock Pins
RE=pin,43,-,-,-;
CLE=pin,18,-,-,-;
WE=pin,19,-,-,-;
CEI=pin,42,-,-,-;

[PTOE ASSIGNMENTS]

[FAST BYPASS]
Default=;

[OSM BYPASS]
Default=None;

[INPUT REGISTERS]
Default=NONE;
;

[IO TYPES]
D0=LVCMOS33,pin,-,-;
CLE=LVCMOS33,pin,-,-;
WE=LVCMOS33,pin,-,-;
RE=LVCMOS33,pin,-,-;
CEI=LVCMOS33,pin,-,-;
CEO=LVCMOS33,pin,1,-;

[PLL ASSIGNMENTS]

[RESOURCE RESERVATIONS]
layer=OFF;

[SLEWRATE]
FAST=CEO;
Default=Fast;

[PULLUP]
Default=Hold;

[FITTER RESULTS]
I/O_pin_util = 6;
I/O_pin = 2;
Logic_PT_util = 14;
Logic_PT = 23;
Occupied_MC_util = 34;
Occupied_MC = 11;
Occupied_PT_util = 22;
Occupied_PT = 38;
GLB_input_util = 27;
GLB_input = 20;

[FITTER REPORT FORMAT]
Fitter_Options = Yes;
Pinout_Diagram = No;
Pinout_Listing = Yes;
Detailed_Block_Segment_Summary = Yes;
Input_Signal_List = Yes;
Output_Signal_List = Yes;
Bidir_Signal_List = Yes;
Node_Signal_List = Yes;
Signal_Fanout_List = Yes;
Block_Segment_Fanin_List = Yes;
Postfit_Eqn = Yes;
Page_Break = Yes;

[POWER]
Default=HIGH;

[SOURCE_CONSTRAINT_OPTION]

[HARDWARE DEVICE OPTIONS]
Zero_Hold_Time = No;
Signature_Word = ;
Pullup = No;
Slew_Rate = FAST;

[TIMING ANALYZER]
Last_source=;
Last_source_type=Fmax;