tcfix.rpt
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|--------------------------------------------------------------|
|- ispLEVER 3.00.02.49.34_SP2003.02_Patch Fitter Report File -|
|- Copyright(C), 1992-2001, Lattice Semiconductor Corporation -|
|- All Rights Reserved. -|
|--------------------------------------------------------------|
Project_Summary
~~~~~~~~~~~~~~~
Project Name : tcfix
Project Path : \\Elk\berndt\tcfix
Project Fitted on : Mon Oct 27 15:02:58 2003
Device : M4032_32
Package : 48
GLB Input Mux Size : 6
Available Blocks : 2
Speed : -7.5
Part Number : LC4032V-75T48C
Source Format : Schematic_Verilog_HDL
// Project 'tcfix' Fit Successfully! //
Compilation_Times
~~~~~~~~~~~~~~~~~
Prefit Time 0 secs
Load Design Time 0.06 secs
Partition Time 0.05 secs
Place Time 0.00 secs
Route Time 0.00 secs
Total Fit Time 00:00:01
Design_Summary
~~~~~~~~~~~~~~
Total Input Pins 5
Total Logic Functions 11
Total Output Pins 1
Total Bidir I/O Pins 0
Total Buried Nodes 10
Total Flip-Flops 10
Total D Flip-Flops 5
Total T Flip-Flops 5
Total Latches 0
Total Product Terms 41
Total Reserved Pins 0
Total Locked Pins 6
Total Locked Nodes 0
Total Unique Output Enables 0
Total Unique Clocks 1
Total Unique Clock Enables 0
Total Unique Resets 3
Total Unique Presets 3
Device_Resource_Summary
~~~~~~~~~~~~~~~~~~~~~~~
Total
Available Used Available Utilization
----------------------------------------------------------------------
Dedicated Pins
Clock/Input Pins 4 4 0 --> 100
I/O / Enable Pins 2 0 2 --> 0
I/O Pins 30 2 28 --> 6
Logic Functions 32 11 21 --> 34
Input Registers 32 0 32 --> 0
Unusable Macrocells .. 0 .. --> ..
GLB Inputs 72 20 52 --> 27
Logical Product Terms 160 23 137 --> 14
Occupied GLBs 2 2 0 --> 100
Occupied Macrocells 32 11 21 --> 34
One Function Macrocells .. 11 .. --> ..
Zero Function Macrocells .. 0 .. --> ..
Occupied Product Terms 168 38 130 --> 22
Control Product Terms:
GLB Clock/Clock Enables 2 0 2 --> 0
GLB Reset/Presets 2 0 2 --> 0
Macrocell Clocks 32 0 32 --> 0
Macrocell Clock Enables 32 0 32 --> 0
Macrocell Enables 32 0 32 --> 0
Macrocell Resets 32 2 30 --> 6
Macrocell Presets 32 2 30 --> 6
Global Routing Pool 68 14 54 --> 20
GRP from IFB .. 4 .. --> ..
(from input signals) .. 4 .. --> ..
(from output signals) .. 0 .. --> ..
(from bidir signals) .. 0 .. --> ..
GRP from MFB .. 10 .. --> ..
----------------------------------------------------------------------
<Note> 1 : IFB is I/O feedback.
<Note> 2 : MFB is macrocell feedback.
GLB_Resource_Summary
~~~~~~~~~~~~~~~~~~~~
# of PT
I/O Input Macrocells Macrocells Logic clusters
Fanin Pins Regs Used Unusable available PTs used
------------------------------------------------------------------------------
Maximum
GLB 36 *(1) 8 -- -- 16 80 16
==============================================================================
GLB A 6 1/16 0 2 0 14 7 2
GLB B 14 1/16 0 9 0 7 16 9
------------------------------------------------------------------------------
<Note> 1 : For ispMACH 4000 devices, the number of IOs depends on the GLB.
<Note> 2 : Four rightmost columns above reflect last status of the placement process.
GLB_Control_Summary
~~~~~~~~~~~~~~~~~~~
Shared Shared | Mcell Mcell Mcell Mcell Mcell
Clk/CE Rst/Pr | Clock CE Enable Reset Preset
------------------------------------------------------------------------------
Maximum
GLB 1 1 16 16 16 16 16
==============================================================================
GLB A 0 0 0 0 0 0 0
GLB B 0 0 0 0 0 2 2
------------------------------------------------------------------------------
<Note> 1 : For ispMACH 4000 devices, the number of output enables depends on the GLB.
Optimizer_and_Fitter_Options
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Pin Assignment : Yes
Group Assignment : No
Pin Reservation : No
@Ignore_Project_Constraints :
Pin Assignments : No
Keep Block Assignment --
Keep Segment Assignment --
Group Assignments : No
Macrocell Assignment : No
Keep Block Assignment --
Keep Segment Assignment --
@Backannotate_Project_Constraints
Pin Assignments : No
Pin And Block Assignments : No
Pin, Macrocell and Block : No
@Timing_Constraints : No
@Global_Project_Optimization :
Balanced Partitioning : Yes
Spread Placement : Yes
Note :
Pack Design :
Balanced Partitioning = No
Spread Placement = No
Spread Design :
Balanced Partitioning = Yes
Spread Placement = Yes
@Logic_Synthesis :
Logic Reduction : Yes
Node Collapsing : FMAX
Fmax_Logic_Level : 1
D/T Synthesis : Yes
XOR Synthesis : Yes
Max. P-Term for Collapsing : 16
Max. P-Term for Splitting : 80
Max Symbols : 24
@Utilization_options
Max. % of Macrocells used : 100
@Usercode (HEX)
@IO_Types Default = LVCMOS18 (2)
@Output_Slew_Rate Default = FAST (2)
@Power Default = HIGH (2)
@Pull Default = PULLUP_HOLD (2)
@Fast_Bypass Default = None (2)
@OSM_Bypass Default = None
@Input_Registers Default = None (2)
Device Options:
<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
follow the drive level set for the Global Configure Unused I/O Option.
<Note> 2 : For user-specified constraints on individual signals, refer to the Output,
Bidir and Buried Signal Lists.
Pinout_Listing
~~~~~~~~~~~~~~
| Pin |GLB |Assigned| | Signal|
Pin No| Type |Pad |Pin | I/O Type | Type | Signal name
-------------------------------------------------------------------
1 | TDI | | | | |
2 | I_O | A5 | | | |
3 | I_O | A6 | | | |
4 | I_O | A7 | | | |
5 |GNDIO0 | | | | |
6 |VCCIO0 | | | | |
7 | I_O | A8 | | | |
8 | I_O | A9 | | | |
9 | I_O | A10| | | |
10 | I_O | A11| | | |
11 | TCK | | | | |
12 | VCC | | | | |
13 | GND | | | | |
14 | I_O | A12| | | |
15 | I_O | A13| | | |
16 | I_O | A14| | | |
17 | I_O | A15| | | |
18 |INCLK1 | | * |LVCMOS33 | Input |CLE
19 |INCLK2 | | * |LVCMOS33 | Input |WE
20 | I_O | B0 | | | |
21 | I_O | B1 | | | |
22 | I_O | B2 | | | |
23 | I_O | B3 | | | |
24 | I_O | B4 | * |LVCMOS33 | Output|CEO
25 | TMS | | | | |
26 | I_O | B5 | | | |
27 | I_O | B6 | | | |
28 | I_O | B7 | | | |
29 |GNDIO1 | | | | |
30 |VCCIO1 | | | | |
31 | I_O | B8 | | | |
32 | I_O | B9 | | | |
33 | I_O | B10| | | |
34 | I_O | B11| | | |
35 | TDO | | | | |
36 | VCC | | | | |
37 | GND | | | | |
38 | I_O | B12| | | |
39 | I_O | B13| | | |
40 | I_O | B14| | | |
41 | I_O/OE| B15| | | |
42 |INCLK3 | | * |LVCMOS33 | Input |CEI
43 |INCLK0 | | * |LVCMOS33 | Input |RE
44 | I_O/OE| A0 | | | |
45 | I_O | A1 | | | |
46 | I_O | A2 | | | |
47 | I_O | A3 | | | |
48 | I_O | A4 | * |LVCMOS33 | Input |D0
-------------------------------------------------------------------
<Note> GLB Pad : This notation refers to the GLB I/O pad number in the device.
<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
<Note> Pin Type :
ClkIn : Dedicated input or clock pin
CLK : Dedicated clock pin
I_O : Input/Output pin
INP : Dedicated input pin
JTAG : JTAG Control and test pin
NC : No connected
Input_Signal_List
~~~~~~~~~~~~~~~~~
Input
Pin Fanout
Pin GLB Type Pullup Signal
----------------------------------
42 -- INCLK 1 -B Hold CEI
18 -- INCLK 2 AB Hold CLE
48 A I/O 1 -B Hold D0
43 -- INCLK -- Hold RE
19 -- INCLK 2 AB Hold WE
----------------------------------
Output_Signal_List
~~~~~~~~~~~~~~~~~~
I C P R O Output
N L Mc R E C O I F B Fanout
Pin GLB P PTs S Type E S E E R P P Slew Pullup Signal
--------------------------------------------------------------
24 B 12 2 1 COM -- Fast Hold CEO
--------------------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
PRE = Has preset equation
RES = Has reset equation
CE = Has clock enable equation
OE = Has output enable equation
IR = Input register
FP = Fast path used
OBP = OSM bypass used
Bidir_Signal_List
~~~~~~~~~~~~~~~~~
I C P R O Bidir
N L Mc R E C O I F B Fanout
Pin GLB P PTs S Type E S E E R P P Slew Pullup Signal
--------------------------------------------------------------
--------------------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
PRE = Has preset equation
RES = Has reset equation
CE = Has clock enable equation
OE = Has output enable equation
IR = Input register
FP = Fast path used
OBP = OSM bypass used
Buried_Signal_List
~~~~~~~~~~~~~~~~~~
I C P R Node
N L Mc R E C I F Fanout
Mc GLB P PTs S Type E S E R P Signal
------------------------------------------------
7 B 3 1 1 DFF * 2 AB reg_cnt_0_
3 B 4 2 1 DFF * 2 AB reg_cnt_1_
9 A 5 3 1 DFF * 2 AB reg_cnt_2_
3 A 6 4 1 DFF * 2 AB reg_cnt_3_
2 B 7 2 1 DFF * 1 -B reg_cnt_4_
12 B 7 1 1 TFF * 1 -B reg_cnt_5_
9 B 8 1 1 TFF * 1 -B reg_cnt_6_
5 B 9 1 1 TFF * 1 -B reg_cnt_7_
1 B 11 3 1 TFF * * 1 -B reg_cnt_8_
0 B 12 3 1 TFF * * 1 -B reg_cnt_9_
------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
PRE = Has preset equation
RES = Has reset equation
CE = Has clock enable equation
OE = Has output enable equation
IR = Input register
FP = Fast path used
OBP = OSM bypass used
Signals_Fanout_List
~~~~~~~~~~~~~~~~~~~
Signal Source : Fanout List
------------------------------------------------------------
CEI{..} : CEO{B}
CLE{..} : CEO{B} reg_cnt_0_{B} reg_cnt_1_{B}
: reg_cnt_2_{A} reg_cnt_3_{A} reg_cnt_4_{B}
: reg_cnt_5_{B} reg_cnt_6_{B} reg_cnt_7_{B}
: reg_cnt_8_{B} reg_cnt_9_{B}
D0{A} : reg_cnt_8_{B} reg_cnt_9_{B}
WE{..} : reg_cnt_0_{B} reg_cnt_1_{B} reg_cnt_2_{A}
: reg_cnt_3_{A} reg_cnt_4_{B} reg_cnt_5_{B}
: reg_cnt_6_{B} reg_cnt_7_{B} reg_cnt_8_{B}
: reg_cnt_9_{B}
reg_cnt_0_.Q{B}: CEO{B} reg_cnt_0_{B} reg_cnt_1_{B}
: reg_cnt_2_{A} reg_cnt_3_{A} reg_cnt_4_{B}
: reg_cnt_5_{B} reg_cnt_6_{B} reg_cnt_7_{B}
: reg_cnt_8_{B} reg_cnt_9_{B}
reg_cnt_1_.Q{B}: CEO{B} reg_cnt_1_{B} reg_cnt_2_{A}
: reg_cnt_3_{A} reg_cnt_4_{B} reg_cnt_5_{B}
: reg_cnt_6_{B} reg_cnt_7_{B} reg_cnt_8_{B}
: reg_cnt_9_{B}
reg_cnt_2_.Q{A}: CEO{B} reg_cnt_2_{A} reg_cnt_3_{A}
: reg_cnt_4_{B} reg_cnt_5_{B} reg_cnt_6_{B}
: reg_cnt_7_{B} reg_cnt_8_{B} reg_cnt_9_{B}
reg_cnt_3_.Q{A}: CEO{B} reg_cnt_3_{A} reg_cnt_4_{B}
: reg_cnt_5_{B} reg_cnt_6_{B} reg_cnt_7_{B}
: reg_cnt_8_{B} reg_cnt_9_{B}
reg_cnt_4_.Q{B}: CEO{B} reg_cnt_4_{B} reg_cnt_5_{B}
: reg_cnt_6_{B} reg_cnt_7_{B} reg_cnt_8_{B}
: reg_cnt_9_{B}
reg_cnt_5_.Q{B}: CEO{B} reg_cnt_6_{B} reg_cnt_7_{B}
: reg_cnt_8_{B} reg_cnt_9_{B}
reg_cnt_6_.Q{B}: CEO{B} reg_cnt_7_{B} reg_cnt_8_{B}
: reg_cnt_9_{B}
reg_cnt_7_.Q{B}: CEO{B} reg_cnt_8_{B} reg_cnt_9_{B}
reg_cnt_8_.Q{B}: CEO{B} reg_cnt_9_{B}
reg_cnt_9_.Q{B}: CEO{B}
------------------------------------------------------------
<Note> {.} : Indicates GLB location of signal
GLB_A_CLUSTER_TABLE
~~~~~~~~~~~~~~~~~~~
CCCC CCCC CCCC CCCC GGBBBB I T L X C
0000 0000 0011 1111 CECCAA / P P P P
0123 4567 8901 2345 KBKERP Type O T T T T Signal
-----------------------------------------------------------
M00 *--- ---- ---- ---- ------
M01 -*-- ---- ---- ---- ------
M02 --*- ---- ---- ---- ------
M03 ---4 ---- ---- ---- 1---1- NODE - 0 4 0 0 reg_cnt_3_
M04 ---- *--- ---- ---- ------
M05 ---- -*-- ---- ---- ------
M06 ---- --*- ---- ---- ------
M07 ---- ---* ---- ---- ------
M08 ---- ---- *--- ---- ------
M09 ---- ---- -3-- ---- 1---1- NODE - 0 3 0 0 reg_cnt_2_
M10 ---- ---- --*- ---- ------
M11 ---- ---- ---* ---- ------
M12 ---- ---- ---- *--- ------
M13 ---- ---- ---- -*-- ------
M14 ---- ---- ---- --*- ------
M15 ---- ---- ---- ---* ------
-----------------------------------------------------------
Block Init PT: CLE & !WE
GLB_B_CLUSTER_TABLE
~~~~~~~~~~~~~~~~~~~
CCCC CCCC CCCC CCCC GGBBBB I T L X C
0000 0000 0011 1111 CECCAA / P P P P
0123 4567 8901 2345 KBKERP Type O T T T T Signal
-----------------------------------------------------------
M00 3--- ---- ---- ---- 1----- NODE - 0 1 0 2 reg_cnt_9_
M01 -3-- ---- ---- ---- 1----- NODE - 0 1 0 2 reg_cnt_8_
M02 --2- ---- ---- ---- 1----1 NODE - 0 1 1 0 reg_cnt_4_
M03 ---2 ---- ---- ---- 1---1- NODE - 0 2 0 0 reg_cnt_1_
M04 ---- 2--- ---- ---- ------ OUT 4 0 2 0 0 CEO
M05 ---- -1-- ---- ---- 1---1- NODE - 0 1 0 0 reg_cnt_7_
M06 ---- --*- ---- ---- ------
M07 ---- ---1 ---- ---- 1---1- NODE - 0 1 0 0 reg_cnt_0_
M08 ---- ---- *--- ---- ------
M09 ---- ---- -1-- ---- 1---1- NODE - 0 1 0 0 reg_cnt_6_
M10 ---- ---- --*- ---- ------
M11 ---- ---- ---* ---- ------
M12 ---- ---- ---- 1--- 1---1- NODE - 0 1 0 0 reg_cnt_5_
M13 ---- ---- ---- -*-- ------
M14 ---- ---- ---- --*- ------
M15 ---- ---- ---- ---* ------
-----------------------------------------------------------
Block Init PT: CLE
& !WE
<Note> Pin clocks, block clocks, block resets, block presets and
output enables are not included in the ctrl pterm counts
in the above tables.
<Note> LPT = Number of Logic Pterms
XPT = Number of XOR Pterms
CPT = Number of Control Pterms
<Note> TPT = Number of Pterm Adders
<Note> GCK = Global Pin Clock
GEB = Global Output Enable Bus
BCK = Block Asynchronous Clock
BCE = Block Clock Enable
BAR = Block Asynchronous Reset
BAP = Block Asynchronous Preset
GLB_A_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~
GI Source Signal GI Source Signal
----------------------------- -----------------------------
00 ... ... 18 ... ...
01 mc A-3 reg_cnt_3_.Q 19 ... ...
02 mc A-9 reg_cnt_2_.Q 20 ... ...
03 ... ... 21 ... ...
04 mc B-7 reg_cnt_0_.Q 22 ... ...
05 mc B-3 reg_cnt_1_.Q 23 ... ...
06 ... ... 24 ... ...
07 ... ... 25 ... ...
08 ... ... 26 ... ...
09 ... ... 27 ... ...
10 ... ... 28 ... ...
11 ... ... 29 ... ...
12 ... ... 30 ... ...
13 ... ... 31 ... ...
14 ... ... 32 ... ...
15 pin 19 WE 33 ... ...
16 pin 18 CLE 34 ... ...
17 ... ... 35 ... ...
--------------------------------------------------------------
GLB_B_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~
GI Source Signal GI Source Signal
----------------------------- -----------------------------
00 ... ... 18 mc B-5 reg_cnt_7_.Q
01 mc A-3 reg_cnt_3_.Q 19 ... ...
02 mc A-9 reg_cnt_2_.Q 20 ... ...
03 mc B-12 reg_cnt_5_.Q 21 pin 42 CEI
04 mc B-7 reg_cnt_0_.Q 22 ... ...
05 mc B-3 reg_cnt_1_.Q 23 pin 48 D0
06 ... ... 24 mc B-2 reg_cnt_4_.Q
07 mc B-1 reg_cnt_8_.Q 25 ... ...
08 mc B-0 reg_cnt_9_.Q 26 ... ...
09 ... ... 27 ... ...
10 ... ... 28 ... ...
11 ... ... 29 ... ...
12 ... ... 30 ... ...
13 ... ... 31 ... ...
14 mc B-9 reg_cnt_6_.Q 32 ... ...
15 pin 19 WE 33 ... ...
16 pin 18 CLE 34 ... ...
17 ... ... 35 ... ...
--------------------------------------------------------------
<Note> GI indicates the GLB inputs into the AND array.
<Note> Source indicates where the signal comes from (pin or macrocell).
PostFit_Equations
~~~~~~~~~~~~~~~~~
------------------------
Product Term Histogram
------------------------
1 pterms : 4 (4 )
2 pterms : 3 (7 )
3 pterms : 3 (10 )
4 pterms : 1 (11 )
------------------------
<Note> The number of pterms in the above histogram counts only
cluster pterms used. It does not include pterms from
control equations placed on global pins or block level
product terms.
<Note> The value in brackets is the cumulative number of
functions having less than or equal number of product
terms.
------------------------
GLB Input Histogram
------------------------
3 inputs : 1 (1 )
4 inputs : 1 (2 )
5 inputs : 1 (3 )
6 inputs : 1 (4 )
7 inputs : 2 (6 )
8 inputs : 1 (7 )
9 inputs : 1 (8 )
11 inputs : 1 (9 )
12 inputs : 2 (11 )
------------------------
<Note> The number of block inputs in the above histogram counts
only signal sources that are inputs to the AND array.
It does not include signal sources assigned to global pins.
<Note> The value in brackets is the cumulative number of
functions having less than or equal number of signal
sources.
CEO = !CLE & !reg_cnt_9_.Q & !reg_cnt_8_.Q & !reg_cnt_7_.Q & !reg_cnt_1_.Q
& !reg_cnt_0_.Q & !reg_cnt_6_.Q & !reg_cnt_5_.Q & !reg_cnt_4_.Q
& !reg_cnt_3_.Q & !reg_cnt_2_.Q
# !CLE & CEI ; (2 pterms, 12 signals)
reg_cnt_0_.D = !reg_cnt_0_.Q ; (1 pterm, 1 signal)
reg_cnt_0_.C = RE ; (1 pterm, 1 signal)
reg_cnt_0_.AR = CLE & !WE ; (1 pterm, 2 signals)
reg_cnt_1_.D = !reg_cnt_1_.Q & !reg_cnt_0_.Q
# reg_cnt_1_.Q & reg_cnt_0_.Q ; (2 pterms, 2 signals)
reg_cnt_1_.C = RE ; (1 pterm, 1 signal)
reg_cnt_1_.AR = CLE & !WE ; (1 pterm, 2 signals)
reg_cnt_2_.D = !reg_cnt_1_.Q & !reg_cnt_0_.Q & !reg_cnt_2_.Q
# reg_cnt_0_.Q & reg_cnt_2_.Q
# reg_cnt_1_.Q & reg_cnt_2_.Q ; (3 pterms, 3 signals)
reg_cnt_2_.C = RE ; (1 pterm, 1 signal)
reg_cnt_2_.AR = CLE & !WE ; (1 pterm, 2 signals)
reg_cnt_3_.D = !reg_cnt_1_.Q & !reg_cnt_0_.Q & !reg_cnt_3_.Q & !reg_cnt_2_.Q
# reg_cnt_0_.Q & reg_cnt_3_.Q
# reg_cnt_1_.Q & reg_cnt_3_.Q
# reg_cnt_3_.Q & reg_cnt_2_.Q ; (4 pterms, 4 signals)
reg_cnt_3_.C = RE ; (1 pterm, 1 signal)
reg_cnt_3_.AR = CLE & !WE ; (1 pterm, 2 signals)
reg_cnt_4_.D.X1 = reg_cnt_4_.Q ; (1 pterm, 1 signal)
reg_cnt_4_.D.X2 = !reg_cnt_1_.Q & !reg_cnt_0_.Q & !reg_cnt_3_.Q
& !reg_cnt_2_.Q ; (1 pterm, 4 signals)
reg_cnt_4_.C = RE ; (1 pterm, 1 signal)
reg_cnt_4_.AP = CLE & !WE ; (1 pterm, 2 signals)
reg_cnt_5_.T = !reg_cnt_1_.Q & !reg_cnt_0_.Q & !reg_cnt_4_.Q & !reg_cnt_3_.Q
& !reg_cnt_2_.Q ; (1 pterm, 5 signals)
reg_cnt_5_.C = RE ; (1 pterm, 1 signal)
reg_cnt_5_.AR = CLE & !WE ; (1 pterm, 2 signals)
reg_cnt_6_.T = !reg_cnt_1_.Q & !reg_cnt_0_.Q & !reg_cnt_5_.Q & !reg_cnt_4_.Q
& !reg_cnt_3_.Q & !reg_cnt_2_.Q ; (1 pterm, 6 signals)
reg_cnt_6_.C = RE ; (1 pterm, 1 signal)
reg_cnt_6_.AR = CLE & !WE ; (1 pterm, 2 signals)
reg_cnt_7_.T = !reg_cnt_1_.Q & !reg_cnt_0_.Q & !reg_cnt_6_.Q & !reg_cnt_5_.Q
& !reg_cnt_4_.Q & !reg_cnt_3_.Q & !reg_cnt_2_.Q ; (1 pterm, 7 signals)
reg_cnt_7_.C = RE ; (1 pterm, 1 signal)
reg_cnt_7_.AR = CLE & !WE ; (1 pterm, 2 signals)
reg_cnt_8_.T = !reg_cnt_7_.Q & !reg_cnt_1_.Q & !reg_cnt_0_.Q & !reg_cnt_6_.Q
& !reg_cnt_5_.Q & !reg_cnt_4_.Q & !reg_cnt_3_.Q & !reg_cnt_2_.Q ; (1 pterm, 8 signals)
reg_cnt_8_.C = RE ; (1 pterm, 1 signal)
reg_cnt_8_.AR = !D0 & CLE & !WE ; (1 pterm, 3 signals)
reg_cnt_8_.AP = D0 & CLE & !WE ; (1 pterm, 3 signals)
reg_cnt_9_.T = !reg_cnt_8_.Q & !reg_cnt_7_.Q & !reg_cnt_1_.Q & !reg_cnt_0_.Q
& !reg_cnt_6_.Q & !reg_cnt_5_.Q & !reg_cnt_4_.Q & !reg_cnt_3_.Q
& !reg_cnt_2_.Q ; (1 pterm, 9 signals)
reg_cnt_9_.C = RE ; (1 pterm, 1 signal)
reg_cnt_9_.AR = D0 & CLE & !WE ; (1 pterm, 3 signals)
reg_cnt_9_.AP = !D0 & CLE & !WE ; (1 pterm, 3 signals)