#include "entry.h"
#include <PR/bbsim.h>
#include <PR/bbskapi.h>

//#define NO_CACHE_SCRUB 1
#undef NO_CACHE_SCRUB

/* 
 *  NOTES:
 *
 *   assume we always enter from code that was running in kernel mode. 
 *   otherwise, have no way to know how to set the C0_SR[KSU] bit.
 *
 *   assume the C0_SR[BEV] bit was NOT set prior to entry nmi. (so
 *   external code has already initialized it's own exception
 *   handlers).
 *
 *   exit write to MI SM reg will go into write buffer. since we
 *   invalidate icache on entry, write buffer is gauranteed to be
 *   flushed before returned code is executed (since must load to
 *   obtain code).
 */

#define DCACHE_INVAL_ON_EXIT_USING_T0          \
	la	t0, __dcache_inval_sk_exit;    \
	jalr	t0
#define DCACHE_INVAL_ON_ENTRY_USING_T0         \
	la	t0, __dcache_inval_sk_enter;   \
	jalr	t0
		
/* reserve space for the stack pointer */
.bss
.align 4
/*
 * setting stack in internal RAM
 */

/*	
.comm __stack, SK_STACK_SIZE
*/

	
.globl __stack
	__stack = PHYS_TO_K0(INTERNAL_RAM_END) - SK_STACK_SIZE

	
/* declare "C" handler */
.extern __c_exception_handler

.global __sk_exit_app_launch

/* need mips3 for cache instructions */
.set mips3
	
.text
.align 2
.set reorder
.global __start
.ent __start
__start:
	.set push
	.set noat

	/*
	 * use full 64 bits of k1 to hold the 32-bit entry values
	 * of both k1 and k0 (in upper and lower 32-bit halves,
	 * respectively). this is safe because the exception handler
	 * in libultra (only place where k0 and k1 are used) never
	 * use k0 or k1 in a 64-bit manner. the only entry case
	 * where k0 and k1 must be restored are for the sk timer,
	 * so once we determine this is not a timer entry, k0 and
	 * k1 will not need to be restored.
	 */

	.set noreorder
	
        /* place both k0 and k1 into k1 (k1 into upper 32 bits) */
        dsll32  k0, 0
        dsrl32  k0, 0
        dsll32  k1, 0
        daddu   k1, k1, k0

	/* determine entry reason. entry from boot is default.
	 * check timer first so ensuing cases may use both
	 * k0 and k1 (since they don't need to be restored). 
	 */
	lw	k0, PHYS_TO_K1(MI_SEC_MODE_REG) /* assember uses only k0 */
	andi	k0, MI_SEC_MODE_TIMER  /* MI_SEC_MODE_TIMER must be in a
					* a bit position [0..15] to use
					* andi. this is the only way to
					* to this check using only a
					* single register.
					*/
	bgtz	k0, enter_timer
	nop
	.set reorder

	/* safe to use k[0..1], t[0..7] */
	lw	k0, PHYS_TO_K1(MI_SEC_MODE_REG)
	move	k1, k0
        and	k0, MI_SEC_MODE_APP
	bgtz	k0, enter_api
	move	k0, k1
	and	k0, MI_SEC_MODE_MD_TRAP | MI_SEC_MODE_BUT_TRAP | \
	            MI_SEC_MODE_TRAP    | MI_SEC_MODE_FATAL
	bgtz	k0, enter_trap
	
	.set pop


	/* TODO, XXX: need to consider handling multiple (all) entry
	 *            reasons in this single entry. if not, need to
	 *            consider priorities.
	 */

	/*****************************************************
	 *
	 *    B O O T   E N T R Y
	 *
	 *****************************************************/

	
	/* by default we assume entrance from boot code */
.globl skReboot
skReboot:
enter_boot:
	/* we're already running cached from boot code, and do not
	 * need to restore any context
	 */

	/* zero bss */
        .set noreorder
        la      t0, __bss_start
        la      t1, _end - 4
	REG_TO_K1(t0)
	REG_TO_K1(t1)
zero_bss:
        sw      zero, (t0)
        bge     t1, t0, zero_bss
        add     t0, 4
        .set reorder

	/* jump to C to handle loading sysapp. 
	 * The return value is the target load address (in v0).
	 * This will be used later to jump to the sysapp.
	 */
	SK_STACK_SET
	la	t0, skEntryBoot
	jalr	t0

	/****************************************
	 *     EXCEPTION HANDLING OVERHEAD START
	 ****************************************/
	
	.set noreorder
	j	__past_exception_handlers
	nop
	
	/* MAKING SPACE FOR HANDLERS */
	.align 9, 0
	.rept (0x180)/4
	nop
	.endr
	.set reorder
		
	/* the handler itself (never exits, so no register saving).
	 * must insure all handler code executes kseg1.
	 */
	la	k0, __c_exception_handler
	la	a0, message
	or	k0, K1BASE
	or	a0, K1BASE
	SK_STACK_SET
	or	sp, K1BASE
	jr	k0
	nop

__past_exception_handlers:	 

	/***************************************
	 *     EXCEPTION HANDLING OVERHEAD END
	 ***************************************/

	/* once here, v0 must hold dram address execution will
	 * ultimately go to when exiting secure mode.
	 */
__sk_exit_app_launch:	
	CACHED_EXECUTION_USING_T0

	lw	t3, gExtraBits
	sw	zero, gExtraBits
	/* invalidate dcache (no cached loads may be issued 
	 *  after this).	
	 */
	DCACHE_INVAL_ON_EXIT_USING_T0
	
	/* Clear Status register BEV, SR, ERL, EXL, and IE bits.
	 */
        mfc0    t4, C0_SR
        and     t4, ~SR_SR
        and     t4, ~SR_BEV
        and     t4, ~(SR_ERL|SR_EXL|SR_IE)
	mtc0	t4, C0_SR

	/* setup value to write to secure mode reg for exit */
	li	t1, PHYS_TO_K1(MI_SEC_MODE_REG)
	lw	t0, (t1)
	move	a0, t0 /* record MI_SEC_MODE_REG for sysapp */
	or	a0, a0, t3
	and	t0, ~(MI_SEC_MODE_SECURE   |  MI_SEC_MODE_APP   | \
	              MI_SEC_MODE_MD_TRAP  |  MI_SEC_MODE_TIMER | \
	              MI_SEC_MODE_BUT_TRAP |  MI_SEC_MODE_TRAP  | \
	              MI_SEC_MODE_FATAL) 

	/* 32 byte alignment for I-cache line (must be consistent
	 * with ICACHE_LINESIZE in R4300.h), so instructions below
	 * can only result in 8 machine instructions. 
	 */
	.align 5
cache_exit_boot:
	.set noreorder
	sw	t0, (t1)   /* exit sm */
        lw      t1, -4(t1) /* insure previous sw leaves write buffer */
	jr	v0
	nop
	.set reorder

	
				
	/*****************************************************
	 *
	 *    A P I   E N T R Y
	 *
	 *****************************************************/

enter_api:	
	/* setup stack */
	.set push
	.set noat
	move	k0, sp
	/* since dcache invalidation occurs later, must save entry
	 * context to kseg1 stack addr (cannot allow at to be used).
	 */
	SK_STACK_SET
	lui	k1, 0xa000
	or	sp, k1
	
	/* store context for api entry:	
	 *         s0-s8, gp, sp, at, ra 
	 *  NOTE: assumes if called from int handler, handler does
	 *        NOT expect kX to be preserved! 
	 */
	SK_CONTEXT_SAVE_API
	SK_CONTEXT_SAVE_CP0_API(t0)
	.set pop

	la	gp, _gp

	/* invalidate icache:
	/* place cache invalidation code into cache then jump there
	 * running in cached mode.
	 */
	la	t2, __icache_inval
	cache	CACH_PI|C_FILL, (t2)
        addu    t2,ICACHE_LINESIZE
	cache	CACH_PI|C_FILL, (t2)
	sub	t2, ICACHE_LINESIZE
	jalr	t2

	/* switch to run cached */
	CACHED_EXECUTION_USING_T0

	/* invalidate dcache */
	DCACHE_INVAL_ON_ENTRY_USING_T0
			
	/* now safe to use kseg0 sp */
	REG_TO_K0(sp)

	/* check access rights */
        la      t2, gNumApiCalls
        lw      t3, (t2)
        bge     v0, t3, no_rights
	la	t2, gApiRights
	lw	t3, (t2)
	li	t2, 1
	sll	t2, v0
	and	t3, t2
	bgtz	t3, has_rights
no_rights:
	/* if here, no right to make this call */
	li	v0, SK_API_NO_ENTRY_FOUND
	j	api_exit_cleanup
	
	/* call the C api function in cached mode (return cached). */
	/* we link cached, so this table holds cached addresses    */
has_rights:	
#ifdef SK_STACK_CHECK
	la	t0,PHYS_TO_K0(INTERNAL_RAM_START)
	la	t1,PHYS_TO_K0(INTERNAL_RAM_END-SK_CONTEXT_SIZE)
        li      t2, 0xdeadbeef
1:	sw	t2,0(t0)
	addu	t0,4
	bltu	t0,t1,1b
#endif
        sll     t0, v0, 2
        la      t1, skapi_call_table
        addu    t1, t1, t0
        lw      t0, (t1)
        jalr    t0

api_exit_cleanup:	
	/* invalidate dcache  (sp must be converted to KSEG1, and no
	 * cached loads should be issued after this). 
	 */
	DCACHE_INVAL_ON_EXIT_USING_T0

	/* convert sp to uncached address */
	REG_TO_K1(sp)

	/* setup value to write to secure mode reg for exit.
	 * Registers t0 and t1 cannot be changed till exit.
	 */
	li	t1, PHYS_TO_K1(MI_SEC_MODE_REG)
	lw	t0, (t1)
        /* re-arm entry via api call */
	and	t0, ~(MI_SEC_MODE_APP | MI_SEC_MODE_BUT_TRAP) 
	and	t0, ~MI_SEC_MODE_SECURE /* set to exit secure mode */

	/* Clear Status register BEV and SR bits.
	 */
        mfc0    t4, C0_SR
        and     t4, ~SR_SR
        and     t4, ~SR_BEV
	mtc0	t4, C0_SR
	
	/* restore context */
	.set push
	.set noat
	.set noreorder
	SK_CONTEXT_REST_CP0_API(t5)
	SK_CONTEXT_REST_API
        lw	sp, SK_SP_SP(sp)
	.set reorder
	
	/* 32 byte alignment for I-cache line (must be consistent
	 * with ICACHE_LINESIZE in R4300.h. 
	 */
	.align 5
cache_exit_api:
	.set noreorder
	sw	t0, (t1)   /* exit sm */
        lw      t1, -4(t1) /* insure previous sw leaves write buffer */
	eret  /* clears CO_SR[ERL] bit */
	.set reorder
	.set pop

		
				
	/*****************************************************
	 *
	 *    T I M E R   E N T R Y
	 *
	 *****************************************************/
enter_timer:
	/* setup stack */
	.set push
	.set noat
	move	k0, sp

	/* since dcache invalidation occurs later, must save entry
	 * context to kseg1 stack addr (cannot allow at to be used).
	 */
#ifndef NO_CACHE_SCRUB 
	SK_STACK_SET_KSEG1
#else
	SK_STACK_SET
#endif
	
	/* store context for timer entry - all registers except float	
	 */

	SK_CONTEXT_SAVE_ALL
	.set pop

	la	gp, _gp

#ifndef NO_CACHE_SCRUB 
	/* invalidate icache:
	/* place cache invalidation code into cache then jump there
	 * running in cached mode.
	 */
	la	t2, __icache_inval
	cache	CACH_PI|C_FILL, (t2)
        addu    t2,ICACHE_LINESIZE
	cache	CACH_PI|C_FILL, (t2)
	sub	t2, ICACHE_LINESIZE
	jalr	t2
#endif

	/* switch to run cached */
	CACHED_EXECUTION_USING_T0

#ifndef NO_CACHE_SCRUB 
	/* invalidate dcache */
	DCACHE_INVAL_ON_ENTRY_USING_T0
#endif

	/* now safe to use kseg0 sp */
	REG_TO_K0(sp)

	/* call the C handler */
	la	t0, skEntryTimer
	jalr	t0

	/* invalidate dcache - careful no kseg0 stores are made from
	 * here to exit
	 */
#ifndef NO_CACHE_SCRUB 
	DCACHE_INVAL_ON_EXIT_USING_T0
#endif

	/* setup k0 and k1 for sw to exit sm */
	li	k1, PHYS_TO_K1(MI_SEC_MODE_REG)
	lw	k0, (k1)
	and	k0, ~MI_SEC_MODE_TIMER  /* allow entry for next firing */
	and	k0, ~MI_SEC_MODE_SECURE /* set to exit secure mode */

	/* note: k0, k1 cannot be used until write to exit sm */

	/* since nmi entry, clear status register BEV and SR bits */
        mfc0    t4, C0_SR
        and     t4, ~(SR_SR | SR_BEV) 
	mtc0	t4, C0_SR  

	/* restore regs and regular stack (context switch).
	 * Macro restores all registers except k0, k1 and sp(sp last)
	 */
	.set noreorder
	.set push
	.set noat

	/* prime dcache with values for registers that must be restored
	 * after exit sm, but prior to eret. (target reg t4 chosen since
	 * will be restored by above macro below.) NOTE: this relies on
	 * contiguous region of stack used for storing context that is
	 * smaller than the dcache. with this assumption, these lines
	 * will not be swapped out due to SK_CONTEXT_REST_MOST to follow.
	 */
	lw	t4, SK_SP_K0(sp)
	lw	t4, SK_SP_K1(sp)
	lw	t4, SK_SP_SP(sp)

	SK_CONTEXT_REST_MOST

	/*
	 * 32 byte alignment for I-cache line (must be consistent
	 * with ICACHE_LINESIZE in R4300.h. 
	 */
	.align 5
cache_exit_timer:
	sw	k0, (k1)   /* exit sm */
        lw      k0, -4(k1) /* insure previous sw leaves write buffer */
	lw	k0, SK_SP_K0(sp)
	lw	k1, SK_SP_K1(sp)
	lw	sp, SK_SP_SP(sp)
	eret            /* eret clears CO_SR[ERL] bit */

	.set pop
	.set reorder
	

	
	/*****************************************************
	 *
	 *    T R A P   E N T R Y
	 *
	 *****************************************************/

enter_trap:
	/* no context must be saved since we do not return to app */
	
	/* setup stack */
	move	k0, sp
	/* since dcache invalidation occurs later, must save entry
	 * context to kseg1 stack addr (cannot allow at to be used).
	 */
	SK_STACK_SET
	lui	k1, 0xa000
	or	sp, k1
	
	la	gp, _gp

	/* invalidate icache:
	/* place cache invalidation code into cache then jump there
	 * running in cached mode.
	 */
	la	t2, __icache_inval
	cache	CACH_PI|C_FILL, (t2)
        addu    t2,ICACHE_LINESIZE
	cache	CACH_PI|C_FILL, (t2)
	sub	t2, ICACHE_LINESIZE
	jalr	t2

	/* switch to run cached */
	CACHED_EXECUTION_USING_T0
		
	/* invalidate dcache */
	DCACHE_INVAL_ON_ENTRY_USING_T0
			
	/* now safe to use kseg0 sp */
	REG_TO_K0(sp)

	/* disarm timer */
	la	t2, PHYS_TO_K1(MI_SEC_TIMER_REG)
	sw	zero, (t2)
	
	/* now relaunch sysapp as if entering first time,
	 * will pass MI_SEC_MODE_REG value to sysapp so
	 * true reason may be determined there.
	 */
	j	enter_boot
	
.end __start


/*
 * NOTE: the __icache_inval code can not be changed without taking
 *       into account the number of cache lines required. this is
 *       because when we enter for skapi call, we must insure no
 *       lines of code already in the cache can be executed (someone
 *       setting up the cache with their code). but, we also want
 *       to run the cache invalidation code cached (for speed). so,
 *       the appropriate number of lines, containing the code below,
 *       are invalidated before jumping here cached. (this could all
 *       be computed based on bracketing symbols, but since this code
 *       should not need to be changed we do it as described above)
 */
.ent __icache_inval
	/* 32 byte alignment for I-cache line (must be consistent
	 * with ICACHE_LINESIZE in R4300.h. 
	 */
	.align 5
__icache_inval:
        # Invalidate I cache
	.set reorder
        la      t0,K0BASE
        addu    t1,t0,ICACHE_SIZE
        subu    t1,ICACHE_LINESIZE
	.set noreorder
        mtc0    zero,C0_TAGLO
        mtc0    zero,C0_TAGHI
init_icache:
        cache   CACH_PI|C_IST,0(t0)     #  use index invalidate
        bltu    t0,t1,init_icache       #  on entire cache
        addu    t0,ICACHE_LINESIZE

	jr	ra
	nop
	.set reorder
.end __icache_inval


.ent __dcache_inval_sk_enter
__dcache_inval_sk_enter:	
	/* ok to use what is now ROM addr, below, since we never
	 * actually write any useful data to this address.
	 */
        la      t0,PHYS_TO_K0(BOOT_RAM_HI_START)
        addu    t1,t0,DCACHE_SIZE
        subu    t1,DCACHE_LINESIZE
	lui	t5,0x1fc0		#  internal mem start addr
	lui	t6,0x1fcb		#  internal mem end (past) addr
	.set noreorder
loop_dcache:
	cache   CACH_PD|C_ILT,0(t0)	# hazard - need 1 instr before mfc0
	nop
        mfc0    t4,C0_TAGLO

	and	t2,t4,PSTATEMASK        #  is this line valid?
	beqz	t2,1f
	
	and	t4,PADDRMASK		#  mask out non-addr bits
	sll	t4,PADDR_SHIFT		#  align phys tag to addr
	bltu	t4,t5,1f		#  < internal mem start
	nop
	bltu	t6,t4,1f		#  >= internal mem end (inclusive)
	nop

	/* ENTERing SK */
	/* tag indicates internal addr, use IST to invalidate */
	mtc0	zero,C0_TAGLO		#  setup to invalidate
        cache   CACH_PD|C_IST,0(t0)     #  use index-store-tag

1:					#  if jump here, no action on this line
        bltu    t0,t1,loop_dcache       #  next line
        addu    t0,DCACHE_LINESIZE
	.set reorder

	jr	ra
.end __dcache_inval_sk_enter


.ent __dcache_inval_sk_exit
__dcache_inval_sk_exit:
	/* on exit, zero most of iram. this will force writeback
	 * of all non-iram internal memory from dcache, since iram
	 * is 32KB and dcache is 16KB.
	 */	
	la	t0,PHYS_TO_K0(INTERNAL_RAM_START)
	la	t1,PHYS_TO_K0(INTERNAL_RAM_END-SK_CONTEXT_SIZE)
1:	sd	zero,0(t0)
	addu	t0,8
	bltu	t0,t1,1b
	
	/* now index writeback invalidate */
	la	t0,PHYS_TO_K0(INTERNAL_RAM_START)
	addu	t1,t0,DCACHE_SIZE
1:	cache	CACH_PD|C_IWBINV,0(t0)  #  index write-back invalidate.
        addu    t0,DCACHE_LINESIZE
        bltu    t0,t1,1b       #  next line

	jr	ra
.end __dcache_inval_sk_exit

	
#if !(defined(SK_LOG_IDE) || defined(SK_LOG_MEM) || defined(SK_LOG_RDB))
LEAF(message)
	jr	ra
END(message)
#endif