skload.c
1.53 KB
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#include <PR/bcp.h>
#include <PR/bbnand.h>
#include "boot.h"
#define PI_FLASH_DEV0_BUF0_READ_PAGE 0x9f008a10
#define PI_FLASH_DEV0_BUF1_READ_PAGE \
(PI_FLASH_DEV0_BUF0_READ_PAGE | PI_FLASH_CTRL_BUF1)
#define PI_AES_CTRL_BASE 0x80000000
#define PI_AES_DATA_SHIFT(data) ((data)<<PI_AES_CTRL_DATA_SHIFT)
#define PI_AES_IV_SHIFT(iv) ((iv)<<PI_AES_CTRL_IV_SHIFT)
#define PI_AES_SIZE_SHIFT(size) ((size)<<PI_AES_CTRL_SIZE_SHIFT)
#define POLL_AES_BUSY do{}while((IO_READ(PI_AES_CTRL_REG))&PI_AES_CTRL_BUSY)
#define FLASH_MODULE_PRESENT \
(!((IO_READ(MI_EINTR_REG)&MI_EINTR_MODULE_REMOVED)))
#define FLASH_MODULE_STATE_CHANGED \
(IO_READ(MI_EINTR_REG)&MI_INTR_MD)
/* NOTE: define below will clear everything in PI_ERROR_REG,
* but for boot code this is the desired effect.
*/
#define FLASH_MODULE_CLEAR_STATE_CHANGED \
(IO_WRITE(MI_EINTR_REG,MI_INTR_MD))
main()
{
u32 val,*p32;
TRACE(0x30);
/* flip bram and brom */
val = IO_READ(MI_SEC_MODE_REG);
val |= MI_SEC_MODE_SECURE;
val &= ~MI_SEC_MODE_BROM_LO;
IO_WRITE(MI_SEC_MODE_REG,val);
/* jump to SK running cached.
* XXX: since the sk is otherwise entered in un-cached mode,
* this entry will be slightly different. Since the sk code
* that runs un-cached will likely be asm, and since it will
* switch to cached very early, this should be transparent.
* But, it needs to be kept in mind while writing SK code.
*/
asm(".set noreorder; j 0x9fc00000; nop; .set reorder");
}