boot.c
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#include "cpusim.h"
#include <rdb.h>
#if 0
#define RAM_ADDR 0x80000400
#else
#define RAM_ADDR 0x80500000
#endif
#define ROM_ADDR 0xbfc00800 /* assume boot is <= 2KB */
#define PROBE_IDE_RDB() \
(IDE_WRITE(IDE_RDB_RDATA_REG+0,0xbabe), \
IDE_WRITE(IDE_RDB_RDATA_REG+2,0xcafe), \
((IDE_READ(IDE_RDB_RDATA_REG+0) == 0xbabe) & \
(IDE_READ(IDE_RDB_RDATA_REG+2) == 0xcafe)))
void
nmesg(const char* buf) {
/* write 1 character at a time to debug port */
if (PROBE_IDE_RDB()) {
while(*buf) {
IDE_WRITE(IDE_RDB_RDATA_REG, ((RDB_TYPE_GtoH_PRINT << 2)|1) << 8 | *buf++);
IDE_WRITE(IDE_RDB_CTRL_REG, IDE_RDB_CTRL_SET_BB_REQ|IDE_RDB_CTRL_CLR_HOST_ACK);
while((IDE_READ(IDE_RDB_STATUS_REG) & IDE_RDB_STATUS_HOST_ACK) == 0)
;
}
}
}
int
main() {
int i;
u32* src, *dst;
void (*f0)(void);
if (getcp0reg(C0_SR) & SR_SR) {
/* nmi */
IO_WRITE(VIRAGE0_RAM_START, getcp0reg(C0_EPC));
nmesg("\nsec trap\n");
}
IO_WRITE(PI_GPIO_REG, (PI_GPIO_POWER_BIT<<PI_GPIO_ENABLE_SHIFT)|PI_GPIO_POWER_BIT);
/* The slower settings are necessary for 96MHz, should still work on 80MHz */
//IO_WRITE(PI_IDE_CONFIG_REG, 2 << 0 | 0xa << 5 | 0xc << 10);
IO_WRITE(PI_IDE_CONFIG_REG, 2 << 0 | 16 << 5 | 20 << 10);
IDE_WRITE(IDE_RDB_CTRL_REG, IDE_RDB_CTRL_RESET);
setcp0reg(C0_SR, SR_CU0|SR_CU1|SR_BEV);
setcp0reg(C0_CONFIG, CONFIG_BE|CONFIG_NONCOHRNT);
init_ddr();
restart:
nmesg("copy ...\n");
src = (void*)ROM_ADDR;
dst = (void*)K0_TO_K1(RAM_ADDR);
for(i = 0; i < 62*1024/4; i++) {
*dst++ = *src++;
}
#if 0
src = (void*)ROM_ADDR;
dst = (void*)K0_TO_K1(RAM_ADDR);
for(i = 0; i < 62*1024/4; i++) {
if (*dst++ != *src++) {
nmesg("bad copy :(\n");
goto restart;
}
}
#endif
nmesg("jump ...\n");
f0 = (void(*))(RAM_ADDR);
setreg($30, 0); /* zero frame pointer */
setreg($29, 0x80800000); /* stack pointer at end of memory */
(*f0)();
return 0;
}