fldma.c
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#include "cpusim.h"
#include "bbnand.h"
void
passed(void) {
message("test fldma passed\n");
DBG_JTAG_PASS("test fldma passed\n");
test_postamble();
}
void
failed(const char* code) {
message("test fldma failed (");
message(code);
DBG_JTAG_FAIL(code);
message(")\n");
test_postamble();
}
static int wait_page(void) {
do {
if (IO_READ(MI_EINTR_REG)&MI_INTR_MD) return 1;
} while(IO_READ(PI_FLASH_CTRL_REG)&PI_FLASH_CTRL_BUSY);
return (IO_READ(PI_FLASH_CTRL_REG) & PI_FLASH_CTRL_DBERR) ? 1 : 0;
}
static int
read_page(unsigned addr, int which_buf, int wait) {
IO_WRITE(PI_FLASH_ADDR_REG, addr << PI_FLASH_PAGE_ADDR_SHIFT);
IO_WRITE(PI_FLASH_CTRL_REG, PI_FLASH_CTRL_START |
PI_FLASH_CTRL_RDPH |
0xf << PI_FLASH_CTRL_ADPH_SHIFT |
0x0 << PI_FLASH_CTRL_CMD_SHIFT |
PI_FLASH_CTRL_WRDY |
which_buf << PI_FLASH_CTRL_BUF_SHIFT |
0 << PI_FLASH_CTRL_DEV_SHIFT |
PI_FLASH_CTRL_ECC |
528);
return wait ? wait_page() : 0;
}
static void
aes_setup(int buffer, int chain) {
IO_WRITE(PI_AES_CTRL_REG, PI_AES_CTRL_START |
((512/16)-1) << PI_AES_CTRL_SIZE_SHIFT |
(buffer ? 32 : 0) << PI_AES_CTRL_DATA_SHIFT |
(chain ? PI_AES_CTRL_HC :
(PI_AES_INIT_INDX16 << PI_AES_CTRL_IV_SHIFT)));
}
static const unsigned int aes_ekey[44] = {
0xbabecafe, 0xfeedbeef, 0xbad22dad, 0xdeadd00d,
0xd729d838, 0x700ebb99, 0x99370e14, 0x307feebb,
0x9aed5431, 0xeae3efa8, 0x73d4e1bc, 0x43ab0f07,
0xa63fcd14, 0x4cdc22bc, 0x3f08c300, 0x7ca3cc07,
0xe19a7022, 0xad46529e, 0x924e919e, 0xeeed5d99,
0x9aa5496d, 0x37e31bf3, 0xa5ad8a6d, 0x4b40d7f4,
0x52ca4230, 0x652959c3, 0xc084d3ae, 0x8bc4045a,
0x4e8c2dc2, 0x2ba57401, 0xeb21a7af, 0x60e5a3f5,
0x00c39741, 0x2b66e340, 0xc04744ef, 0xa0a2e71a,
0x68f0195f, 0x4396fa1f, 0x83d1bef0, 0x237359ea,
0xb721863f, 0x755f9da8, 0x4e4ca3a2, 0x2e886422,
};
static const unsigned int aes_iv[4] = {
0xdeadd00d, 0xdad22bad, 0xdeadbeef, 0xcafebabe,
};
int
main() {
int i, j;
unsigned short csum = 0;
test_preamble();
/* initialize memory and caches */
init_ddr();
initICache();
initDCache();
setcp0reg(C0_SR, SR_CU0|SR_CU1|SR_BEV);
setcp0reg(C0_CONFIG, CONFIG_BE|CONFIG_NONCOHRNT);
/* configure flash */
IO_WRITE(PI_FLASH_CONFIG_REG, 7 << 28 | // end of cycle time - 2
5 << 24 | // read data sample time - 1
0x3e << 16 | // RE active time
0x1f << 8 | // WE active time
0x3f << 0); // CLE/ALE active time
for(i = 0; i < 11; i++)
for(j = 0; j < 4; j++)
IO_WRITE(PI_AES_EKEY_REG+(i*4+j)*4, aes_ekey[(10-i)*4+j]);
for(i = 0; i < 4; i++)
IO_WRITE(PI_AES_INIT_REG+4*i, aes_iv[i]);
/* overlap transfer and aes */
if (read_page(0, 0, 1)) failed("2");
for(i = 1; i < 33; i++) {
int which = (i-1)&1;
if (i < 32 && read_page(i, (which+1)&1, 0)) failed("3");
aes_setup(which, i == 1 ? 0 : 1);
while((IO_READ(PI_AES_CTRL_REG))&PI_AES_CTRL_BUSY) ;
invalDCache((void*)K0BASE, 512);
IO_WRITE(PI_DRAM_ADDR_REG, K0_TO_PHYS(K0BASE));
IO_WRITE(PI_CART_ADDR_REG, which ? 512 : 0);
IO_WRITE(PI_DMA_BUFFER_WR_REG, 512);
while (IO_READ(PI_STATUS_REG) & (PI_STATUS_IO_BUSY | PI_STATUS_DMA_BUSY)) ;
for(j = 0; j < 512/4; j++) {
unsigned x = *((volatile unsigned *)K0BASE+j);
csum += (x >> 24) + ((x >> 16)&0xff) + ((x >> 8)&0xff) + (x&0xff);
}
IO_WRITE(PI_IDE3_BASE_REG, csum);
if (wait_page()) failed("4");;
}
if (csum != 0x1c22) failed("5");
passed();
return 0;
}