#include "pi_util.h"
#include "pi_tests.h"




#define DBG_acc 1


#define EXT_OP_FAIL  3
#define SKIPPED 4

#define ExpectPass  0
#define ExpectFail  1

#define PI_ALL_ACC_BITS ( \
    PI_ACCESS_ERROR     | \
    PI_ACCESS_IO        | \
    PI_ACCESS_GPIO      | \
    PI_ACCESS_BDMA      | \
    PI_ACCESS_AES       | \
    PI_ACCESS_ATB       | \
    PI_ACCESS_FLASH     | \
    PI_ACCESS_BUFFER    )

#define PI_NO_ACC_BITS  (0)


/*  in accTestMod, ExtOp refers to Extended operation */
typedef enum { CheckAccess, StartExtOp, CheckExtOp } accTestMode;

typedef enum { e_None, e_accChkBuf, e_accChkFlash, e_accChkAes, e_accChkBDMA, e_accChkAtb } accTestEnum;

static u32 flashSimDevSize[4];

static int piBufInUseBy;


int accChk (u32 addr, u32 rwbits, accTestMode mode, int expect_fail)
{
    int ret;
    u32 org, mod, now;

    if(mode!=CheckAccess) {
        printf("accChk doesn't do an extended operation test\n");
        fflush(NULL);
        return TESTERROR;
    }

    org = IO_READ(addr);
    mod = org ^ rwbits;
    IO_WRITE(addr,mod);
    now = IO_READ(addr);
    #if DBG_acc
        printf("rwbits %08x   addr %08x    org %08x   mod %08x  now %08x\n",rwbits, addr, org, mod, now);
    #endif
    if( (mod & rwbits) != (now & rwbits) )
        ret = expect_fail ? PASS : FAIL;
    else {
        ret = expect_fail ? FAIL : PASS;
        IO_WRITE(addr,org);
        now = IO_READ(addr);
        if( (org & rwbits) != (now & rwbits)) {
            printf("After restore: rwbits %08x   addr %08x    org %08x   mod %08x  now %08x\n",rwbits, addr, org, mod, now);
            ret = FAIL;
        }
    }
    fflush(NULL);
    return ret;
}

int ChkAcessBDMA (u32 addr, u32 bytes, int expect_fail)
{
    int ret, i, changed;
    u32 org, mod, now, dram_addr, buf_off;

    #if DBG_acc
        printf("PI_DRAM_ADDR_REG %08x   PI_CART_ADDR_REG %08x    PI_STATUS_REG %08x\n",
                IO_READ(PI_DRAM_ADDR_REG), IO_READ(PI_CART_ADDR_REG), IO_READ(PI_STATUS_REG));
    #endif

    IO_WRITE(PI_DRAM_ADDR_REG, (dram_addr=rand()&0x000FFFF8));
    IO_WRITE(PI_CART_ADDR_REG, (buf_off=(rand()%(1024-bytes))&~7));

    IO_WRITE(addr,0);
    org = IO_READ(addr);
    if(org==bytes) bytes+=8;
    mod = bytes;


    IO_WRITE(addr,mod);

    #if DBG_acc
        printf("PI_DRAM_ADDR_REG %08x   PI_CART_ADDR_REG %08x    PI_STATUS_REG %08x\n",
                IO_READ(PI_DRAM_ADDR_REG), IO_READ(PI_CART_ADDR_REG), IO_READ(PI_STATUS_REG));
    #endif

    changed = FALSE; 
    for(i=0; i<3; ++i) {
        now = IO_READ(addr);
        #if DBG_acc
            printf("bytes %08x   addr %08x    org %08x   mod %08x  now %08x dram_addr %08x buf_off %08x\n",
                    bytes, addr, org, mod, now, dram_addr, buf_off);
            printf("PI_STATUS_REG %08x\n", IO_READ(PI_STATUS_REG));
        #endif
        if(now!=0) {
            changed = TRUE;
            break;
        }
    }
    if(org!=0 || changed)
        ret = expect_fail ? FAIL : PASS;
    else
        ret = expect_fail ? PASS : FAIL;
    fflush(NULL);

    return ret;
}


int accChkBDMA (u32 extra1, u32 extra2, accTestMode mode, int expect_fail)
{
    static u8  data1[2048];
    static u32 pi_addr;
    u32        num_bytes = 128;
    u8         data2[2048];
    int        i;

    int ret = TESTERROR;

    switch(mode) {
        case CheckAccess:
            if (piBufInUseBy==e_accChkBDMA) {
                for(i=0; i<num_bytes; i+=4){
                    *((u32 *)(data2 + i)) = rand();
                   // printf("data2[%4d] %02x  %02x  %02x  %02x\n",i, data2[i], data2[i+1], data2[i+2], data2[i+3]); fflush(NULL);
                }
                startDmaToBuf(data2, pi_addr, num_bytes);
                if(checkDmaToBuf(data2, pi_addr, num_bytes)==PASS) {
                    ret = FAIL;
                    break;
                }
                ret=CheckDmaToDramAccess(pi_addr, num_bytes, expect_fail);
                if(ret!=PASS)
                    break;
            }
            ret = ChkAcessBDMA(PI_DMA_BUFFER_WR_REG,16,expect_fail);
            if(ret==PASS && (piBufInUseBy==e_None || piBufInUseBy==e_accChkBDMA))
                ret = ChkAcessBDMA(PI_DMA_BUFFER_RD_REG,16,expect_fail);
            break;

        case StartExtOp:
            piBufInUseBy = e_accChkBDMA;
            pi_addr = (rand()%(2*(512) - num_bytes))&~7;
            _TRACE(DSTATUS,fprintf(LogFp,"accChkBDMA starting Buf Dma: pi buf offset=%08x  num_bytes=%d\n", pi_addr,num_bytes));
            for(i=0; i<num_bytes; i+=4){
                *((u32 *)(data1 + i)) = rand();
                // printf("data1[%4d] %02x  %02x  %02x  %02x\n",i, data1[i], data1[i+1], data1[i+2], data1[i+3]); fflush(NULL);
            }
            ret=CheckDmaToDramAccess(pi_addr, num_bytes, expect_fail);
            if(ret!=PASS)
                break;
            ret = startDmaToBuf(data1, pi_addr, num_bytes);
            if(ret!=PASS && ret!= TESTERROR)
                ret = EXT_OP_FAIL;
            break;

        case CheckExtOp:
            _TRACE(DSTATUS,fprintf(LogFp,"accChkBDMA checking Buf Dma\n"));
            ret = checkDmaToBuf(data1, pi_addr, num_bytes);
            piBufInUseBy = e_None;
            if(ret!=PASS && ret!= TESTERROR)
                ret = EXT_OP_FAIL;
            break;
    }

    fflush(NULL);
    return ret;
}

int ChkAcessAtb (int expect_fail)
{
    u32 addrOffset, wordLow_w, bits9_w, wordLow_r, bits9_r;
    int ret;

    wordLow_w = rand();
    bits9_w   = rand() & 0x1FF;
    addrOffset = (rand() % PI_ATB_NUM_ENTRIES)*4;

    atbWrite(wordLow_w,bits9_w,addrOffset);
    atbRead(&wordLow_r,&bits9_r,addrOffset);

    if (wordLow_r != wordLow_w || bits9_r != bits9_w) {
        #if DBG_acc
            printf("\naccChkAtb:"
                "\n\tatb addrOffeset: %x"
                "\n\tatb write: word = %x, bits = %x"
                "\n\tatb read : word = %x, bits = %x\n"
                , addrOffset, wordLow_w, bits9_w, wordLow_r, bits9_r);
        #endif
        ret = expect_fail ? PASS : FAIL;
    } else
        ret = expect_fail ? FAIL : PASS;

    fflush(NULL);
    return ret;
}

int accChkAtb (u32 extra1, u32 extra2, accTestMode mode, int expect_fail)
{
    int ret = TESTERROR;

    switch(mode) {
        case CheckAccess:
            /*
            if (piDmaInUseBy==e_accChkAtb) {
                if (StartAtbDma()==PASS && CheckAtbDma()==PASS) {
                    ret = FAIL;
                    break;
                }
            }
            */
            ret = ChkAcessAtb(expect_fail);
            break;

        case StartExtOp:
            printf("accChkAtb extended operation test not ready\n");
            #if 0
                _TRACE(DSTATUS,fprintf(LogFp,"accChkAtb starting Atb Dma()\n"));
                piDmaInUseBy = e_accChkAtb;
                ret = StartAtbDma();
                if(ret!=PASS && ret!= TESTERROR)
                    ret = EXT_OP_FAIL;
            #endif
            break;

        case CheckExtOp:
            printf("accChkAtb extended operation test not ready\n");
            ret = FAIL;
            #if 0
                _TRACE(DSTATUS,fprintf(LogFp,"accChkAtb checking Atb Dma()\n"));
                ret = CheckAtbDma();
                piDmaInUseBy = e_None;
                if(ret!=PASS && ret!= TESTERROR)
                    ret = EXT_OP_FAIL;
            #endif
            break;
    }

    fflush(NULL);
    return ret;
}



void accChkBufFill(u8 *data, u32 num_bytes, u32 buf_addr)
{
    int i;
    _TRACE(DSTATUS,fprintf(LogFp,"accChkBufFill: filling PI Buf\n"));
    for(i=0; i<num_bytes; i+=4){
        *((u32 *)(data + i)) = rand();
    }

    ioWriteBuffer(data, num_bytes, buf_addr);
}

int accChkBufCheck(u8 *data, u32 num_bytes, u32 buf_addr)
{
    int i, ret = PASS;
    u8 buf[num_bytes];

    _TRACE(DSTATUS,fprintf(LogFp,"accChkBufCheck: checking PI Buf\n"));
    ioReadBuffer(buf, num_bytes, buf_addr);
    for(i=0; i<num_bytes; i++) {
        if(buf[i]!=data[i]) {
            _TRACE(DSTATUS,fprintf(LogFp,"accChkBufCheck: miscompare:  buf[%d]= %02x dram=%02x\n",i,buf[i],data[i]));
            ret =  FAIL;
            break;
        }
    }
    return ret;
}

int accChkBuf (u32 extra1, u32 extra2, accTestMode mode, int expect_fail)
{
    #define ACCCHKBUF_DATA_SIZE  ((512+16)*2)

    static u8 data1[ACCCHKBUF_DATA_SIZE];
           u8 data2[ACCCHKBUF_DATA_SIZE];

    int ret = TESTERROR;

    if (piBufInUseBy!=e_None && piBufInUseBy!=e_accChkBuf)
        return SKIPPED;

    switch(mode) {
        case CheckAccess:
            if (piBufInUseBy==e_accChkBuf) {
                accChkBufFill(data2,sizeof data2,PI_BUFFER_0_START);
                if (accChkBufCheck(data2,sizeof data2,PI_BUFFER_0_START)==PASS) {
                    ret = FAIL;
                    break;
                }
            }
            if (accChk(PI_BUFFER_0_START,    rand(),CheckAccess,expect_fail)==PASS &&
                accChk(PI_BUFFER_1_START,    rand(),CheckAccess,expect_fail)==PASS &&
                accChk(PI_BUFFER_0_OOB_START,rand(),CheckAccess,expect_fail)==PASS &&
                accChk(PI_BUFFER_1_OOB_START,rand(),CheckAccess,expect_fail)==PASS
            )
                ret = PASS;
            else
                ret = FAIL;
            break;

        case StartExtOp:
            piBufInUseBy = e_accChkBuf;
            /* Unlike flash or dma, this is done when the fill func returns
             * The extended aspect we are checking is that nothing
             * unexpectedly changes the pi buf
            */
            accChkBufFill(data1,sizeof data1,PI_BUFFER_0_START);
            ret = accChkBufCheck(data1,sizeof data1,PI_BUFFER_0_START);
            if(ret!=PASS && ret!= TESTERROR)
                ret = EXT_OP_FAIL;
            break;

        case CheckExtOp:
            ret = accChkBufCheck(data1,sizeof data1,PI_BUFFER_0_START);
            piBufInUseBy = e_None;
            if(ret!=PASS && ret!= TESTERROR)
                ret = EXT_OP_FAIL;
            break;
    }

    fflush(NULL);
    return ret;
}





int checkFlashOp(int dev, int block, int page, int bigDevice, int piBuffer, int enableIntr, u8 buf[528])
{
    int status;
    u8 bufback[528];


    _TRACE(DSTATUS,fprintf(LogFp,"checkFlashOp, begin check extended Flash op\n"));
    if(flashCtrlPollBusy()!=PASS) {
        _TRACE(DSTATUS, fprintf(LogFp,"checkflashProg: program address phase timed out\n"));
        return FAIL;
    } else {
        _TRACE(DSTATUS, fprintf(LogFp,"checkflashProg: program address phase didn't time out\n"));

        if(enableIntr) {
            if(flashCheckClearIntr()!=PASS) {
                return FAIL;
            }
        } else if(flashCheckNoIntr()!=PASS) {
            return FAIL;
        }

        /* address still has bit 8 zero, so OK here */
        IO_WRITE(PI_FLASH_CTRL_REG,0x80108800 | (enableIntr*PI_FLASH_CTRL_INTR)
            |PI_CTRL_DEV_SHIFT(dev));

        if(flashCtrlPollBusy()!=PASS) {
            _TRACE(DSTATUS, fprintf(LogFp,"page program timed out\n"));
            return FAIL;
        } else {
            _TRACE(DSTATUS, fprintf(LogFp,"page programmed\n"));

            status = statusRead(0,dev,0,enableIntr);
            _TRACE(DSTATUS, fprintf(LogFp,"checkflashProg: status %08x  config %08x  fctrl %08x  ereg %08x\n"
                                  , status, IO_READ(PI_FLASH_CONFIG_REG), IO_READ(PI_FLASH_CTRL_REG), IO_READ(PI_ERROR_REG)));
            if(FLASH_STATUS_SUCCESS(status)==PASS) {
                if(PASS!=fullPageCompareBuf(dev,page,piBuffer,bigDevice,enableIntr,buf,bufback)) {
                    printf("checkflashProg: fullPageCompareBuf failed\n");
                    fflush(NULL);
                    return FAIL;
                }
            }
        }
    }
    fflush(NULL);
    return PASS;
}


int startFlashOp(int dev, int block, int page, int bigDevice, int piBuffer, int enableIntr, u8 buf[528])
{
    int i, ret;
    u32 flashCtrlCmd;
    u32 addr = page*PI_FLASH_PAGE_DATA_SIZE;

    _TRACE(DSTATUS,fprintf(LogFp,"startFlashOp, device %d\n",dev));
    if(PASS!=flashBlockEraseVerify(dev, block, piBuffer, bigDevice, enableIntr, 1))
        return FAIL;

    for(i=0;i<PI_FLASH_PAGE_DATA_SIZE;i+=4)
        IO_WRITE(PI_BUFFER_0_START+piBuffer*PI_FLASH_PAGE_DATA_SIZE+i,
                 H2BE4(*((u32 *)(&buf[i]))));

    for(i=0;i<PI_FLASH_OOB_SIZE;i+=4)
        IO_WRITE(PI_BUFFER_0_OOB_START+piBuffer*PI_FLASH_OOB_SIZE+i,
                 H2BE4(*((u32 *)(&buf[PI_FLASH_PAGE_DATA_SIZE+i]))));

    _TRACE(DSTATUS, fprintf(LogFp,
           "startFlashOp: full page program: data written to pi buffer\n"));

    IO_WRITE(PI_FLASH_ADDR_REG,addr);

    /* multi-cycle command */
    IO_WRITE(PI_FLASH_CTRL_REG, 0x80000000 |
             PI_CTRL_DEV_SHIFT(dev)  |
             PI_CTRL_BUF_SHIFT(piBuffer) |
             (enableIntr*PI_FLASH_CTRL_INTR));

    if((ret=flashCtrlPollBusy())!=PASS) return ret;
    if(enableIntr) {
        if(flashCheckClearIntr()!=PASS)
            return FAIL;
    } else if(flashCheckNoIntr()!=PASS)
        return FAIL;

    /* must insure address bit 8 is zero or the 0x80 command will
       become 0x81 */
    IO_WRITE(PI_FLASH_ADDR_REG,addr&0xfffffeff);
#ifdef TOSHIBA_FLASH
    flashCtrlCmd = 0xaf800610;
#else
    if(bigDevice){
        flashCtrlCmd = 0xaf800610;
    }else{
        flashCtrlCmd = 0xa7800610;
    }
#endif
    flashCtrlCmd |= PI_CTRL_DEV_SHIFT(dev);
    flashCtrlCmd |= PI_CTRL_BUF_SHIFT(piBuffer);
    flashCtrlCmd |= enableIntr*PI_FLASH_CTRL_INTR;

    /* start cmd */
    IO_WRITE(PI_FLASH_CTRL_REG,flashCtrlCmd);
    fflush(NULL);
    return PASS;
}




int accChkFlash (u32 extra1, u32 extra2, accTestMode mode, int expect_fail)
{
    static u8  buf[528];
    u8  buf2[528];
    static int dev, page, block, bigDevice;
    int ret = TESTERROR;
    int enableIntr = rand()%2; /* toggle intr testing */
    int blocksize, devSize, i;
    u32 flash_ctrl_bits;

    enableIntr = 0;

    switch(mode) {
        case CheckAccess:
            flash_ctrl_bits = expect_fail ? PI_FLASH_CTRL_START : PI_FLASH_CTRL_BUF1;
            if( (piBufInUseBy!=e_accChkFlash ||
                    startFlashOp(dev,block,page,bigDevice,0,enableIntr,buf2)==FAIL) &&
                accChk(PI_FLASH_CTRL_REG,             flash_ctrl_bits,CheckAccess,expect_fail)==PASS &&
                accChk(PI_FLASH_ADDR_REG,           rand()&0x3FFFFFFF,CheckAccess,expect_fail)==PASS &&
                accChk(PI_FLASH_CONFIG_REG,PI_FLASH_CONFIG_WR_PROTECT,CheckAccess,expect_fail)==PASS
            )
                ret = PASS;
            else
                ret = FAIL;
            break;

        case StartExtOp:
            piBufInUseBy = e_accChkFlash;
            for(i=0;i<sizeof buf;++i) {
                buf[i] = rand();
            }
            dev       = rand()%4;
            devSize   = flashSimDevSize[dev];
            bigDevice = IS_BIG_DEVICE(devSize);
            blocksize = PI_FLASH_PAGES_PER_BLOCK*PI_FLASH_PAGE_DATA_SIZE;
            block     = rand() % (devSize/blocksize);
            page      = block*PI_FLASH_PAGES_PER_BLOCK + rand() % PI_FLASH_PAGES_PER_BLOCK;
            ret = startFlashOp(dev,block,page,bigDevice,0,enableIntr,buf);
            if(ret!=PASS && ret!= TESTERROR)
                ret = EXT_OP_FAIL;
            break;

        case CheckExtOp:
            ret = checkFlashOp(dev,block,page,bigDevice,1,enableIntr,buf);
            piBufInUseBy = e_None;
            if(ret!=PASS && ret!= TESTERROR)
                ret = EXT_OP_FAIL;
            break;
    }

    fflush(NULL);
    return ret;
}



int accChkAes (u32 extra1, u32 extra2, accTestMode mode, int expect_fail)
{
    int ret = TESTERROR;
    static u8 *decdata;
    static u8 *indata;


    switch(mode) {
        case CheckAccess:
            if( (piBufInUseBy!=e_accChkAes ||
                    piAesTestRandomKeyDataIv(0,PI_AES_INIT_INDX16,1,2,NULL,NULL)==FAIL) &&
                accChk(PI_AES_CTRL_REG,PI_AES_CTRL_HC,CheckAccess,expect_fail)==PASS &&
                accChk(PI_AES_EKEY_REG,        rand(),CheckAccess,expect_fail)==PASS &&
                accChk(PI_AES_INIT_REG,        rand(),CheckAccess,expect_fail)==PASS
            )
                ret = PASS;
            else
                ret = FAIL;
            break;

        case StartExtOp:
            _TRACE(DSTATUS,fprintf(LogFp,"accChkAes starting piAesTestRandomKeyDataIv\n"));
            piBufInUseBy = e_accChkAes;
            ret = piAesTestRandomKeyDataIv(0,PI_AES_INIT_INDX16,1,2,&decdata,&indata);
            if(ret!=PASS && ret!= TESTERROR)
                ret = EXT_OP_FAIL;
            break;

        case CheckExtOp:
            ret = piAesTestRandomKeyDataIvCheck(0,1,2,decdata,indata);
            piBufInUseBy = e_None;
            if(ret!=PASS && ret!= TESTERROR)
                ret = EXT_OP_FAIL;
            break;
    }

    fflush(NULL);
    return ret;
}




typedef int (*AccCk)(u32 addr, u32 rwbits, accTestMode mode, int expect_fail);

typedef struct {
    char *name;
    u32   bit;
    AccCk accChk;
    int   addr;
    int   rwbits;
    u32   extOpAccMask; /* includes at least bit if has extended op */
} AccessTestInfo;

#define EXTRA 0

#define FLASH_EXT_OP_ACC_MASK (PI_ACCESS_FLASH | PI_ACCESS_BUFFER)
#define AES_EXT_OP_ACC_MASK   (PI_ACCESS_AES   | PI_ACCESS_BUFFER)
#define BDMA_EXT_OP_ACC_MASK  (PI_ACCESS_BDMA  | PI_ACCESS_BUFFER | PI_ACCESS_ERROR)
#define BUF_EXT_OP_ACC_MASK   (PI_ACCESS_BUFFER)



AccessTestInfo acc_bit[] = {
    { "PI_ACCESS_ERROR" , PI_ACCESS_ERROR ,  accChk,     PI_ERROR_REG     , PI_ERROR_SYS_INTR  , 0 },
    { "PI_ACCESS_IO"    , PI_ACCESS_IO    ,  accChk,     PI_IDE_CONFIG_REG, PI_IDE_CONFIG_RESET, 0 },
    { "PI_ACCESS_GPIO"  , PI_ACCESS_GPIO  ,  accChk,     PI_GPIO_REG      , PI_GPIO_ENABLE_MASK, 0 },
    { "PI_ACCESS_BDMA"  , PI_ACCESS_BDMA  ,  accChkBDMA, EXTRA            , EXTRA              , BDMA_EXT_OP_ACC_MASK },
    { "PI_ACCESS_AES"   , PI_ACCESS_AES   ,  accChkAes,  EXTRA            , EXTRA              , AES_EXT_OP_ACC_MASK },
    { "PI_ACCESS_ATB"   , PI_ACCESS_ATB   ,  accChkAtb,  EXTRA            , EXTRA              , 0 },
    { "PI_ACCESS_FLASH" , PI_ACCESS_FLASH ,  accChkFlash,EXTRA            , EXTRA              , FLASH_EXT_OP_ACC_MASK },
    { "PI_ACCESS_BUFFER", PI_ACCESS_BUFFER,  accChkBuf,  EXTRA            , EXTRA              , BUF_EXT_OP_ACC_MASK }
};




#if 0
    PI_ACCESS_ERROR    allows access to the PI_ERROR register in non-secure mode;
    PI_ACCESS_IO       allows access to the ide controller in non-secure mode, PIO_IOC_CONF, PI_IDE0, PI_IDE1, PI_IDE2, PI_IDE3;
    PI_ACCESS_GPIO     allows access to the gpio hardware in non-secure mode, PI_GPIO;
    PI_ACCESS_BDMA     enables the buffer dma, PI_DMA_BREAD, PI_DMA_BWRITE;
    PI_ACCESS_AES      allows access to aes controller in non-secure mode, PI_AES_EKEY, PI_AES_INIT, PI_AES_CTRL;
    PI_ACCESS_ATB      allows access to atb hardware in non-secure mode, PI_ATBU, PI_BUF_ATB, PI_BUF_ATBU;
    PI_ACCESS_FLASH    allows access to flash controller in non-secure mode, PI_FLASH_CTRL, PI_FLASH_CONF;
    PI_ACCESS_BUFFER   allows access to pi data buffer 0 and 1 in non-secure mode, PI_BUF0, PI_BUF1, PI_SP0, PI_SP1;
#endif



void accTest (u32   acc_mask, int to_toggle)
{
    int  ret, i;
    int  num_acc_bits = sizeof(acc_bit)/sizeof(acc_bit[0]);
    u32  val;
    char buf[512];

    char *name;
    u32   bit;
    AccCk accChk;
    int   addr;
    int   rwbits;
    int   on;

    char *t_name       = acc_bit[to_toggle].name;
    u32   t_bit        = acc_bit[to_toggle].bit;
    AccCk t_accChk     = acc_bit[to_toggle].accChk;
    int   t_addr       = acc_bit[to_toggle].addr;
    int   t_rwbits     = acc_bit[to_toggle].rwbits;
    u32   extOpAccMask = acc_bit[to_toggle].extOpAccMask;
    /* extOpAccMask is the mask of pi acc bits required to do
     * an extended op associted with t_bit.  An extended op
     * is left in progress while access tests are done with
     * the extOpAccMask access bits off.
     * extOpAccMask indludes at least t_bit if extended op should be run.
     * Must also include all other acc bits required for extended op.
     * Can prevent extended op by setting extOpAccMask to zero
     * or by not including all extOpAccMask bits in acc_mask.
     * emask is an adjusted mask of extended op acc bits.
     * If an extended op will not be run for t_bit,
     * emask will be 0, else it will be extOpAccMask.
     */
    u32   emask   = ((extOpAccMask & acc_mask)==extOpAccMask) ? extOpAccMask : 0;
    u32   smask   = acc_mask | t_bit;  /* mask for seting bits on */
    u32   xmask   = acc_mask & ~(t_bit|emask); /* mask for clearing */

    _TRACE(DSTATUS,fprintf(LogFp,"Starting accTest for %s with"
        "\n\t acc_mask     %08x"
        "\n\t extOpAccMask %08x"
        "\n\t emask        %08x"
        "\n\t smask        %08x"
        "\n\t xmask        %08x\n"
        , t_name, acc_mask, extOpAccMask, emask, smask, xmask));

    /* enter secure mode */
    IO_READ(MI_SEC_MODE_REG);
    IO_READ(BOOT_RAM_LO_START);

    /* set access on for t_bit */
    IO_WRITE(PI_ACCESS_REG,smask);
    #if DBG_acc
        printf("set access on: %s %08x\n", t_name,t_bit);
        printf("               emask           %08x\n", emask);
        printf("               PI_ACCESS_REG   %08x\n", IO_READ(PI_ACCESS_REG));
        printf("               MI_SEC_MODE_REG %08x\n", IO_READ(MI_SEC_MODE_REG));
        fflush(NULL);
    #endif

    /* enter non-secure mode */
    val = IO_READ(MI_SEC_MODE_REG);
    val = val & 0x42;
    IO_WRITE(MI_SEC_MODE_REG, val);

    /* for each pi access bit
    *     if on, verify can access
    *     else   verify can't access
    * if applicable, start acc_bit extended operation
    */
    for(i=0;  i < num_acc_bits; i++) {
        name   = acc_bit[i].name;
        bit    = acc_bit[i].bit;
        accChk = acc_bit[i].accChk;
        addr   = acc_bit[i].addr;
        rwbits = acc_bit[i].rwbits;
        on     = smask & bit;
        buf[0] =0;

        printf("PI Control Access %s on: %s %s:\t%s  ", t_name, name, (on?"on":"off"), "start test\n");
        fflush(NULL);
        if(on) {
            /* verify can access */
            if((ret=accChk(addr,rwbits,CheckAccess,ExpectPass))==FAIL) {
                sprintf(buf, "couldn't access in non-secure mode with pi acc bit on:");
            } else if(ret==PASS) {
                #if DBG_acc
                    printf("accessed in non-secure mode with pi acc bit on\n");
                    printf("    PI_ACCESS_REG   %08x\n",IO_READ(PI_ACCESS_REG));
                    printf("    MI_SEC_MODE_REG %08x\n",IO_READ(MI_SEC_MODE_REG));
                #endif
            }
        } else {
            /* verify can't access */
            if((ret=accChk(addr,rwbits,CheckAccess,ExpectFail))==FAIL) {
                sprintf(buf, "accessed in non-secure mode with pi acc bit off:");
            } else if(ret==PASS) {
                #if DBG_acc
                    printf("couldn't access in non-secure mode with pi acc bit off\n");
                    printf("    PI_ACCESS_REG   %08x\n",IO_READ(PI_ACCESS_REG));
                    printf("    MI_SEC_MODE_REG %08x\n",IO_READ(MI_SEC_MODE_REG));
                #endif
            }
        }
        printf("PI Control Access %s on: %s %s:\t%s  ", t_name, name, (on?"on":"off"), buf);
        if(ret==SKIPPED)
            printf("SKIPPED\n");
        else
            OUTPUT_TEST_PASSFAIL(ret);
        fflush(NULL);
    }
    /* start t_bit extended operation if applicable*/
    if(emask) {
        if((ret=t_accChk(t_addr,t_rwbits,StartExtOp,ExpectPass))!=PASS ) {
            printf("PI Control Access %s:\tproblem starting extended operation, ret %d:  ", t_name, ret);
            OUTPUT_TEST_PASSFAIL(FAIL);
            emask = 0;
        } else {
            _TRACE(DSTATUS,fprintf(LogFp,"PI Control Access %s:\textended operation started\n", t_name));
        }
        fflush(NULL);
    }

    /* enter secure mode */
    IO_READ(MI_SEC_MODE_REG);
    IO_READ(BOOT_RAM_LO_START);

    /* set access off for t_bit and ext op bits*/
    IO_WRITE(PI_ACCESS_REG,xmask);
    #if DBG_acc
        printf("set access off: %s %08x\n", t_name,t_bit);
        printf("                emask           %08x\n", emask);
        printf("                PI_ACCESS_REG   %08x\n",IO_READ(PI_ACCESS_REG));
        printf("                MI_SEC_MODE_REG %08x\n",IO_READ(MI_SEC_MODE_REG));
        fflush(NULL);
    #endif

    /* enter non secure mode */
    val = IO_READ(MI_SEC_MODE_REG);
    val = val & 0x42;
    IO_WRITE(MI_SEC_MODE_REG, val);

    /* for each pi access bit
    *     if on, verify can access
    *     else   verify can't access
    *            if bit being toggled
    *               try to set access on
    *               verify can't set on
    *               verify can't access
    *  Since extended op may be in progress, test
    *  the associated access bit first. Check access
    *  and try starting same op (with access off).
    */
    for(i=to_toggle;
            i < num_acc_bits;
                i=(i==to_toggle ? 0:i+1), i=(i==to_toggle ? i+1:i) ){

        name   = acc_bit[i].name;
        bit    = acc_bit[i].bit;
        accChk = acc_bit[i].accChk;
        addr   = acc_bit[i].addr;
        rwbits = acc_bit[i].rwbits;
        on     = xmask & bit;
        buf[0] =0;
        ret    = PASS;

        printf("PI Control Access %s off: %s %s:\t%s  ", t_name, name, (on?"on":"off"), "start test\n");
        fflush(NULL);
        if(on) {
            /* verify can access */
            if((ret=accChk(addr,rwbits,CheckAccess,ExpectPass))==FAIL) {
                sprintf(buf, "couldn't access in non-secure mode with pi acc bit on:");
            } else if(ret==PASS) {
                #if DBG_acc
                    printf("accessed in non-secure mode with pi acc bit on\n");
                    printf("    PI_ACCESS_REG   %08x\n",IO_READ(PI_ACCESS_REG));
                    printf("    MI_SEC_MODE_REG %08x\n",IO_READ(MI_SEC_MODE_REG));
                #endif
            }
        } else {
            /* verify can't access */
            if((ret=accChk(addr,rwbits,CheckAccess,ExpectFail))==FAIL ) {
                sprintf(buf, "accessed in non-secure mode with pi acc bit off:");
            } else if(ret==PASS) {
                #if DBG_acc
                    printf("couldn't access in non-secure mode with pi acc bit off\n");
                    printf("    PI_ACCESS_REG   %08x\n",IO_READ(PI_ACCESS_REG));
                    printf("    MI_SEC_MODE_REG %08x\n",IO_READ(MI_SEC_MODE_REG));
                #endif
            }
            if(ret==PASS && i==to_toggle) {
                /* try to set access on */
                IO_WRITE(PI_ACCESS_REG, IO_READ(PI_ACCESS_REG) | t_bit );
                /* verify can't set on */
                if( IO_READ(PI_ACCESS_REG) != xmask ) {
                    sprintf(buf, "able to turn on access in non-secure mode:");
                    ret = FAIL;
                } else {
                    #if DBG_acc
                        printf("couldn't turn on access in non-secure mode\n");
                        printf("    PI_ACCESS_REG   %08x\n",IO_READ(PI_ACCESS_REG));
                        printf("    MI_SEC_MODE_REG %08x\n",IO_READ(MI_SEC_MODE_REG));
                    #endif
                }
                fflush(NULL);
                /* verify can't access */
                if(ret==PASS) {
                    if((ret=accChk(addr,rwbits,CheckAccess,ExpectFail))==FAIL) {
                        sprintf(buf, "accessed in non-secure mode with pi acc bit off after attempt to set:");
                    } else if(ret==PASS) {
                        #if DBG_acc
                            printf("couldn't access in non-secure mode with pi acc bit off after attempt to set\n");
                            printf("    PI_ACCESS_REG   %08x\n",IO_READ(PI_ACCESS_REG));
                            printf("    MI_SEC_MODE_REG %08x\n",IO_READ(MI_SEC_MODE_REG));
                        #endif
                    }
                }
                fflush(NULL);
            }
        }
        printf("PI Control Access %s off: %s %s:\t%s  ", t_name, name, (on?"on":"off"), buf);
        if(ret==SKIPPED)
            printf("SKIPPED\n");
        else
            OUTPUT_TEST_PASSFAIL(ret);
        fflush(NULL);
    }


    /* enter secure mode */
    IO_READ(MI_SEC_MODE_REG);
    IO_READ(BOOT_RAM_LO_START);

    /* set access on for t_bit & ext op bits*/
    IO_WRITE(PI_ACCESS_REG,smask);
    #if DBG_acc
        printf("set access on: %s %08x\n", t_name,t_bit);
        printf("               emask           %08x\n", emask);
        printf("               PI_ACCESS_REG   %08x\n", IO_READ(PI_ACCESS_REG));
        printf("               MI_SEC_MODE_REG %08x\n", IO_READ(MI_SEC_MODE_REG));
        fflush(NULL);
    #endif

    /* enter non secure mode */
    val = IO_READ(MI_SEC_MODE_REG);
    val = val & 0x42;
    IO_WRITE(MI_SEC_MODE_REG, val);

    /* check t_bit extended operation */
    if(emask) {
        if((ret=t_accChk(t_addr,t_rwbits,CheckExtOp,ExpectPass))!=PASS ) {
            printf("PI Control Access %s:\textended operation problem ret %d:  ", t_name, ret);
            OUTPUT_TEST_PASSFAIL(FAIL);
        } else {
            _TRACE(DSTATUS,fprintf(LogFp,"PI Control Access %s:\textended operation finished successfully\n", t_name));
        }
        fflush(NULL);
    }

    /* for each pi access bit
    *     if on, verify can access
    *     else   verify can't access
    */
    for(i=0;  i < num_acc_bits; i++) {
        name   = acc_bit[i].name;
        bit    = acc_bit[i].bit;
        accChk = acc_bit[i].accChk;
        addr   = acc_bit[i].addr;
        rwbits = acc_bit[i].rwbits;
        on     = smask & bit;
        buf[0] =0;

        printf("PI Control Access, 2nd attempt %s on: %s %s:\t%s  ", t_name, name, (on?"on":"off"), "start test\n");
        fflush(NULL);
        if(on) {
            /* verify can access */
            if((ret=accChk(addr,rwbits,CheckAccess,ExpectPass))==FAIL) {
                sprintf(buf, "couldn't access in non-secure mode with pi acc bit on:");
            } else if(ret==PASS) {
                #if DBG_acc
                    printf("accessed in non-secure mode with pi acc bit on, 2nd attempt\n");
                    printf("    PI_ACCESS_REG   %08x\n",IO_READ(PI_ACCESS_REG));
                    printf("    MI_SEC_MODE_REG %08x\n",IO_READ(MI_SEC_MODE_REG));
                #endif
            }
            if(ret==PASS && i==to_toggle) {
                /* check t_bit ability to turn access off and not back on */
                /* set access off */
                IO_WRITE(PI_ACCESS_REG, IO_READ(PI_ACCESS_REG) & ~t_bit );
                /* verify acc bit off */
                if( IO_READ(PI_ACCESS_REG) & t_bit ) {
                    sprintf(buf, "not able to turn access off in non-secure mode:");
                    ret = FAIL;
                } else {
                    #if DBG_acc
                        printf("able to turn access off in non-secure mode\n");
                        printf("    PI_ACCESS_REG   %08x\n",IO_READ(PI_ACCESS_REG));
                        printf("    MI_SEC_MODE_REG %08x\n",IO_READ(MI_SEC_MODE_REG));
                    #endif
                }
                fflush(NULL);
                /* verify can't access */
                if(ret==PASS) {
                    if((ret=accChk(addr,rwbits,CheckAccess,ExpectFail))==FAIL) {
                        sprintf(buf, "accessed in non-secure mode with pi acc bit off:");
                    } else if(ret==PASS) {
                        #if DBG_acc
                            printf("couldn't access in non-secure mode with pi acc bit off, 2nd attempt\n");
                            printf("    PI_ACCESS_REG   %08x\n",IO_READ(PI_ACCESS_REG));
                            printf("    MI_SEC_MODE_REG %08x\n",IO_READ(MI_SEC_MODE_REG));
                        #endif
                    }
                }
                fflush(NULL);
                /* try to set access on */
                IO_WRITE(PI_ACCESS_REG, IO_READ(PI_ACCESS_REG) | t_bit );
                /* verify can't set on */
                if(ret==PASS) {
                    if(IO_READ(PI_ACCESS_REG) & t_bit) {
                        sprintf(buf, "able to turn on access in non-secure mode:");
                        ret = FAIL;
                    } else {
                        #if DBG_acc
                            printf("couldn't turn on access in non-secure mode, 2nd attempt\n");
                            printf("    PI_ACCESS_REG   %08x\n",IO_READ(PI_ACCESS_REG));
                            printf("    MI_SEC_MODE_REG %08x\n",IO_READ(MI_SEC_MODE_REG));
                        #endif
                    }
                }
                fflush(NULL);
                /* verify can't access */
                if(ret==PASS) {
                    if((ret=accChk(addr,rwbits,CheckAccess,ExpectFail))==FAIL) {
                        sprintf(buf, "accessed in non-secure mode with pi acc bit off after attempt to set:");
                    } else if(ret==PASS) {
                        #if DBG_acc
                            printf("couldn't access in non-secure mode with pi acc bit off after attempt to set\n");
                            printf("    PI_ACCESS_REG   %08x\n",IO_READ(PI_ACCESS_REG));
                            printf("    MI_SEC_MODE_REG %08x\n",IO_READ(MI_SEC_MODE_REG));
                        #endif
                    }
                }
                fflush(NULL);
            }
        } else {
            /* verify can't access */
            if((ret=accChk(addr,rwbits,CheckAccess,ExpectFail))==FAIL) {
                sprintf(buf, "accessed in non-secure mode with pi acc bit off:");
            } else if(ret==PASS) {
                #if DBG_acc
                    printf("couldn't access in non-secure mode with pi acc bit off\n");
                    printf("    PI_ACCESS_REG   %08x\n",IO_READ(PI_ACCESS_REG));
                    printf("    MI_SEC_MODE_REG %08x\n",IO_READ(MI_SEC_MODE_REG));
                #endif
            }
            fflush(NULL);
        }
        printf("PI Control Access, 2nd attempt %s on: %s %s:\t%s  ", t_name, name, (on?"on":"off"), buf);
        if(ret==SKIPPED)
            printf("SKIPPED\n");
        else
            OUTPUT_TEST_PASSFAIL(ret);
        fflush(NULL);
    }
}



/*  for masks: none, all, and random
*
*      for each acc_bit in PI_ACCESS_REG
*
*          xmask = mask & ~(acc_bit|ext_bits)
*          smask = mask | acc_bit
*
*          enter secure mode
*          write smask to PI_ACCESS_REG (sets acc_bit)
*
*          enter non secure mode
*          for each pi access bit
*              if on, verify can access
*              else   verify can't access
*          if applicable, start acc_bit extended operation
*
*          enter secure mode
*          write xmask to PI_ACCESS_REG (clears acc_bit and ext_bits)
*
*          enter non secure mode
*          for each pi access bit
*              if on, verify can access
*              else   verify can't access
*                     if bit being toggled
*                       try to set access on
*                       verify can't set on
*                       verify can't access
*
*          enter secure mode
*          write smask to PI_ACCESS_REG (sets acc_bit)
*
*          enter non-secure mode
*          if applicable, check acc_bit extended operation
*          for each pi access bit
*              if on, verify can access
*              else   verify can't access
*          for acc_bit
*              set access off
*              verify can't access
*              try to set access on
*              verify can't set on
*              verify can't access
*/



void accCtrlTest(const u32 flashSimDeviceSize[])
{

    int  i, j;
    u32  masks[] = {PI_ALL_ACC_BITS,       PI_NO_ACC_BITS,
                    FLASH_EXT_OP_ACC_MASK, AES_EXT_OP_ACC_MASK,
                    BDMA_EXT_OP_ACC_MASK,  BUF_EXT_OP_ACC_MASK};
    int  num_masks = sizeof(masks)/sizeof(masks[0]);
    int  num_acc_bit = sizeof(acc_bit)/sizeof(acc_bit[0]);
    int  num_randoms = 1;

    for(i=0;i<4;i++)
        flashSimDevSize[i] = flashSimDeviceSize[i];

    for(j=0; j < num_masks + num_randoms; ++j) {

        u32 acc_mask = j < num_masks ? masks[j] : PI_ALL_ACC_BITS & rand();

        for( i=0; i < num_acc_bit; ++i)
            accTest( acc_mask, i);
    }
}