reg_test.c
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#include "pi_util.h"
int RegResetStateCheck(u32 reg, u32 mask, u32 expect, const char* reg_name)
{
int result = PASS;
u32 state;
printf("RegResetStateTest: %s: ", reg_name);
state = IO_READ(reg);
if ((state & mask) != (expect & mask))
result = FAIL;
OUTPUT_TEST_PASSFAIL(result);
if (result == FAIL) {
printf("\tExpected bits %08x of reg %08x to be %08x, but were %08x\n"
, mask, reg, expect, state);
}
fflush(NULL);
return result;
}
int RegResetStateTest()
{
/* regs that are not initialized on reset
* PI_DRAM_ADDR_REG;
* PI_FLASH_ADDR_REG
* PI_DEV_ADDR (aka PI_CART_ADDR_REG)
* PI_DMA_READ (aka PI_RD_LEN_REG)
* PI_DMA_WRITE (aks PI_WR_LEN_REG)
* PI_DMA_BREAD (aka PI_DMA_BUFFER_RD_REG)
* PI_DMA_BWRITE (aka PI_DMA_BUFFER_WR_REG)
* PI_ATBU
* PI_BUF_ATB
* PI_BUF_ATBU
* PI_AES_EKEY
* PI_AES_INIT
* PI_IDE_CTRL
* PI_IDE0
* PI_IDE1
* PI_IDE2
* PI_IDE3
* PI_IDE_FC
*/
int i, result = PASS;
int r[] = {
RegResetStateCheck(PI_STATUS_REG, 0xFFFFFFFF, 0x00000000, "PI_DMA_STATUS (aka PI_STATUS_REG): "),
RegResetStateCheck(PI_AES_CTRL_REG, 0xC0000000, 0x00000000, "PI_AES_CTRL_REG: "),
RegResetStateCheck(PI_FLASH_CTRL_REG, 0xC0000000, 0x00000000, "PI_FLASH_CTRL_REG: "),
RegResetStateCheck(PI_FLASH_CONFIG_REG, 0xF7FFFFFF, 0xF53E3EFF, "PI_FLASH_CONFIG_REG: "),
RegResetStateCheck(PI_ERROR_REG, 0xC000003F, 0x00000000, "PI_ERROR_REG: "),
RegResetStateCheck(PI_ACCESS_REG, 0x000000FF, 0x00000000, "PI_ACCESS_REG: "),
RegResetStateCheck(PI_IDE_CONFIG_REG, 0xFFFFFFFF, 0xA0E22501, "PI_IDE_CONFIG_REG: "),
RegResetStateCheck(PI_GPIO_REG, 0x0000FF00, 0x00000000, "PI_GPIO_REG:: "),
RegResetStateCheck(PI_BSD_DOM1_LAT_REG, 0xFFFFFFFF, 0x00000000, "PI_DOM1_LAT (aka PI_BSD_DOM1_LAT_REG): "),
RegResetStateCheck(PI_BSD_DOM1_PWD_REG, 0xFFFFFFFF, 0x00000000, "PI_DOM1_PWD (aka PI_BSD_DOM1_PWD_REG): "),
RegResetStateCheck(PI_BSD_DOM1_PGS_REG, 0xFFFFFFFF, 0x00000000, "PI_DOM1_PGS (aka PI_BSD_DOM1_PGS_REG): "),
RegResetStateCheck(PI_BSD_DOM1_RLS_REG, 0xFFFFFFFF, 0x00000000, "PI_DOM1_RLS (aka PI_BSD_DOM1_RLS_REG): "),
RegResetStateCheck(PI_BSD_DOM2_LAT_REG, 0xFFFFFFFF, 0x00000000, "PI_DOM2_LAT (aka PI_BSD_DOM2_LAT_REG): "),
RegResetStateCheck(PI_BSD_DOM2_PWD_REG, 0xFFFFFFFF, 0x00000000, "PI_DOM2_PWD (aka PI_BSD_DOM2_PWD_REG): "),
RegResetStateCheck(PI_BSD_DOM2_PGS_REG, 0xFFFFFFFF, 0x00000000, "PI_DOM2_PGS (aka PI_BSD_DOM2_PGS_REG): "),
RegResetStateCheck(PI_BSD_DOM2_RLS_REG, 0xFFFFFFFF, 0x00000000, "PI_DOM2_RLS (aka PI_BSD_DOM2_RLS_REG): ")
};
for (i=0; i<sizeof r; ++i) {
if (r[i] != PASS) {
result = r[i];
if (r[i] != FAIL)
break;
}
}
return result;
}
int ConstantRegIoTest(u32 reg_addr, u32 pattern, const char * description)
{
int result = PASS;
u32 val;
printf(description);
if ((val=IO_READ(reg_addr)) != pattern) {
result = FAIL;
printf("initial read %#08x, expected %#08x ", val, pattern);
} else {
IO_WRITE(reg_addr, ~pattern);
if ((val=IO_READ(reg_addr)) != pattern) {
result = FAIL;
printf("wrote %#08x, but read %#08x ", ~pattern, val);
}
}
if (register_test(reg_addr, 0, 0xFFFFFFFF, 0) != PASS)
result = FAIL;
OUTPUT_TEST_PASSFAIL(result);
fflush(NULL);
return result;
}
int piRegIoTest()
{
int result = PASS;
int tmp_result, i, r[8];
u32 rw;
u32 ro;
u32 saved;
if ( (tmp_result=piBufIoTest()) != PASS ) {
result = tmp_result;
if (result != FAIL)
goto end;
}
printf("\nRegIoTest: PI_DRAM_ADDR_REG: ");
if ((tmp_result=register_test(PI_DRAM_ADDR_REG, 0x03FFFFF8, 0, 0)) != PASS)
result = tmp_result = FAIL;
OUTPUT_TEST_PASSFAIL(tmp_result);
fflush(NULL);
printf("\nRegIoTest: PI_FLASH_ADDR_REG: ");
if ((tmp_result=register_test(PI_FLASH_ADDR_REG, 0x3FFFFFFF, 0, 0)) != PASS)
result = tmp_result = FAIL;
OUTPUT_TEST_PASSFAIL(tmp_result);
fflush(NULL);
printf("\nRegIoTest: PI_DEV_ADDR (aka PI_CART_ADDR_REG): ");
if ((tmp_result=register_test(PI_CART_ADDR_REG, 0x3FFFFFFF, 0, 0)) != PASS)
result = tmp_result = FAIL;
OUTPUT_TEST_PASSFAIL(tmp_result);
fflush(NULL);
// no RW without serious side effects
// unused bits that always return 0: [31:4]
// ro bits that return a status [3:2] and ignore write
rw = 0;
ro = 0xFFFFFFFC;
printf("\nRegIoTest: PI_DMA_STATUS (aka PI_STATUS_REG):\t rw: %08x ro: %08x: ",rw,ro);
if ((tmp_result=register_test(PI_STATUS_REG, rw, ro, 0)) != PASS)
result = tmp_result = FAIL;
OUTPUT_TEST_PASSFAIL(tmp_result);
fflush(NULL);
r[0]=ConstantRegIoTest(PI_BSD_DOM1_LAT_REG, 0, "\nRegIoTest: PI_DOM1_LAT (aka PI_BSD_DOM1_LAT_REG): ");
r[1]=ConstantRegIoTest(PI_BSD_DOM1_PWD_REG, 0, "\nRegIoTest: PI_DOM1_PWD (aka PI_BSD_DOM1_PWD_REG): ");
r[2]=ConstantRegIoTest(PI_BSD_DOM1_PGS_REG, 0, "\nRegIoTest: PI_DOM1_PGS (aka PI_BSD_DOM1_PGS_REG): ");
r[3]=ConstantRegIoTest(PI_BSD_DOM1_RLS_REG, 0, "\nRegIoTest: PI_DOM1_RLS (aka PI_BSD_DOM1_RLS_REG): ");
r[4]=ConstantRegIoTest(PI_BSD_DOM2_LAT_REG, 0, "\nRegIoTest: PI_DOM2_LAT (aka PI_BSD_DOM2_LAT_REG): ");
r[5]=ConstantRegIoTest(PI_BSD_DOM2_PWD_REG, 0, "\nRegIoTest: PI_DOM2_PWD (aka PI_BSD_DOM2_PWD_REG): ");
r[6]=ConstantRegIoTest(PI_BSD_DOM2_PGS_REG, 0, "\nRegIoTest: PI_DOM2_PGS (aka PI_BSD_DOM2_PGS_REG): ");
r[7]=ConstantRegIoTest(PI_BSD_DOM2_RLS_REG, 0, "\nRegIoTest: PI_DOM2_RLS (aka PI_BSD_DOM2_RLS_REG): ");
for (i=0; i<8; ++i) {
if (r[i] != PASS) {
result = r[i];
if (r[i] != FAIL)
goto end;
}
}
// RW bits that read what was written [21:9,7:1,0]
// bit 30, INTR is RW, but read is not what was written
// unused bits that always return 0 [29:22,8]
rw = PI_AES_CTRL_SIZE_MASK | PI_AES_CTRL_DATA_MASK | PI_AES_CTRL_IV_MASK | PI_AES_CTRL_HC;
ro = PI_AES_CTRL_INTR | 0x3FC00000;
printf("\nRegIoTest: PI_AES_CTRL_REG:\t rw: %08x ro: %08x: ",rw,ro);
saved = IO_READ(PI_AES_CTRL_REG);
if ((tmp_result=register_test(PI_AES_CTRL_REG, rw, ro, 0)) != PASS)
result = tmp_result = FAIL;
IO_WRITE(PI_AES_CTRL_REG, saved & ~PI_AES_CTRL_BUSY);
OUTPUT_TEST_PASSFAIL(tmp_result);
fflush(NULL);
// PI_AES_EKEY and PI_AES_INIT were tested by piBufIoTest
// RW bits that read what was written [29:12,9:0]
// bit 30, 11, 10 are RW, but read is not what was written
// but can test as ro bits
rw = PI_FLASH_CTRL_WDPH | PI_FLASH_CTRL_RDPH | PI_FLASH_CTRL_ADPH_MASK |
PI_FLASH_CTRL_CMD_MASK | PI_FLASH_CTRL_WRDY | PI_FLASH_CTRL_BUF1 |
PI_FLASH_CTRL_DEV_MASK | PI_FLASH_CTRL_SIZE_MASK;
ro = PI_FLASH_CTRL_INTR | PI_FLASH_CTRL_SBERR | PI_FLASH_CTRL_DBERR;
printf("\nRegIoTest: PI_FLASH_CTRL_REG:\t rw: %08x ro: %08x: ",rw,ro);
saved = IO_READ(PI_FLASH_CTRL_REG);
if ((tmp_result=register_test(PI_FLASH_CTRL_REG, rw, ro, 0)) != PASS)
result = tmp_result = FAIL;
IO_WRITE(PI_FLASH_CTRL_REG, saved & ~PI_FLASH_CTRL_START);
OUTPUT_TEST_PASSFAIL(tmp_result);
fflush(NULL);
// RW bits that read what was written [31:28,26:0]
rw = PI_FLASH_CONFIG_WR_PROTECT | PI_FLASH_CONFIG_EO_CYC_T_MASK |
PI_FLASH_CONFIG_RD_SAM_T_MASK | PI_FLASH_CONFIG_RE_ACT_T_MASK |
PI_FLASH_CONFIG_WE_ACT_T_MASK | PI_FLASH_CONFIG_CA_ACT_T_MASK;
ro = 0;
printf("\nRegIoTest: PI_FLASH_CONFIG_REG:rw: %08x ro: %08x: ",rw,ro);
saved = IO_READ(PI_FLASH_CONFIG_REG);
if ((tmp_result=register_test(PI_FLASH_CONFIG_REG, rw, ro, 0)) != PASS)
result = tmp_result = FAIL;
IO_WRITE(PI_FLASH_CONFIG_REG, saved);
OUTPUT_TEST_PASSFAIL(tmp_result);
fflush(NULL);
// RW bits that read what was written [31:30]
rw = PI_ERROR_KERNEL_INTR | PI_ERROR_SYS_INTR;
ro = PI_ERROR_ADDR_MASK;
printf("\nRegIoTest: PI_ERROR_REG:\t rw: %08x ro: %08x: ",rw,ro);
saved = IO_READ(PI_ERROR_REG);
if ((tmp_result=register_test(PI_ERROR_REG, rw, ro, 0)) != PASS)
result = tmp_result = FAIL;
IO_WRITE(PI_ERROR_REG, saved);
OUTPUT_TEST_PASSFAIL(tmp_result);
fflush(NULL);
// RW bits that read what was written [7:0] without serious side effects
// unused bits that always return 0: [31:8]
rw = PI_ACCESS_ERROR | PI_ACCESS_IO | PI_ACCESS_GPIO | PI_ACCESS_BDMA |
PI_ACCESS_AES | PI_ACCESS_ATB | PI_ACCESS_FLASH | PI_ACCESS_BUFFER;
ro = ~rw;
printf("\nRegIoTest: PI_ACCESS_REG:\t rw: %08x ro: %08x: ",rw,ro);
saved = IO_READ(PI_ACCESS_REG);
if ((tmp_result=register_test(PI_ACCESS_REG, rw, ro, 0)) != PASS)
result = tmp_result = FAIL;
IO_WRITE(PI_ACCESS_REG, saved);
OUTPUT_TEST_PASSFAIL(tmp_result);
fflush(NULL);
// RW bits that read what was written [30:0] without serious side effects
// bits to be skipped due to side effects: [31]
rw = 0x7FFFFFFF;
ro = 0;
printf("\nRegIoTest: PI_IDE_CONFIG_REG:\t rw: %08x ro: %08x: ",rw,ro);
saved = IO_READ(PI_IDE_CONFIG_REG);
if ((tmp_result=register_test(PI_IDE_CONFIG_REG, rw, ro, 0)) != PASS)
result = tmp_result = FAIL;
IO_WRITE(PI_IDE_CONFIG_REG, saved);
OUTPUT_TEST_PASSFAIL(tmp_result);
fflush(NULL);
// no RW without serious side effects
// ro bits that always return same value [31:16]
// unused bits that always return 0: [15:8]
rw = 0;
ro = PI_GPIO_ID_MASK | 0x0000FF00;
printf("\nRegIoTest: PI_GPIO_REG:\t rw: %08x ro: %08x: ",rw,ro);
if ((tmp_result=register_test(PI_GPIO_REG, rw, ro, 0)) != PASS)
result = tmp_result = FAIL;
OUTPUT_TEST_PASSFAIL(tmp_result);
fflush(NULL);
end:
return result;
}