bcp_ri.tst
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//****************************************************************************
//
// File: bcp_ri.tst
// Test file for BCP ri interface
//
// File Format:
//
// t <id> <arg1> <arg2> <arg3> <arg4> - Run test id with the 4 args
// where id = decimal number
// argX = hex number
// k keep socket open/close
// d display message
// q - Quit testing and shutdown verilog
// server
//
//****************************************************************************
// Make persist socket
k 1
//****************************************************************************
// (1) Configure DDR
//
//D Init DDR memory
//D It is the same as Dough memory test
//t 0200 00000000 00000000 00000000 00000000
//****************************************************************************
// (2) Single bit test
//
D rwMemCompare to test single bit(1, x, z)
t 0902 1 0 0 0
t 0216 0000002C 00000000 00000000 00000000
t 0902 0 0 0 0
//****************************************************************************
// (3) Word read and write test
// write word contain x and z value and read back
t 0211 00000000 12345f08 A0413f20 00000000
t 0210 00000000 B2757f28 A0413f20 00000000
t 0212 00000000 B2757f28 A0413f20 5fBE30DF
//****************************************************************************
// (4) The same test but through memory backdoor
// write word contain x and z value and read back
// Before bdoor access, please wait for a while to
// let write finished
t 0211 00000004 12345f08 A0413f20 00000000
t 0014 00000004 00000000 00000000 00000000
t 0300 00000004 B2757f28 A0413f20 00000000
t 0302 00000004 B2757f28 A0413f20 5fBE30DF
t 0301 00000008 12345f08 A0413f20 00000000
t 0210 00000008 B2757f28 A0413f20 00000000
t 0212 00000008 B2757f28 A0413f20 5fBE30DF
//***************************************************************************
// (5) memory single walk test
// 230 -- regular 231 --- include xz value
// code base_addr addr_bits(23 in x36) size stall_cycles
// X36 single bytes access
t 0230 00000000 0 0 0
t 0231 00000000 0 0 0
t 0230 00000000 0 0 1
t 0231 00000000 0 0 1
// x36 double bytes(half word) access
t 0230 00000000 0 1 0
t 0231 00000000 0 1 0
t 0230 00000000 0 1 1
t 0231 00000000 0 1 1
// x36 triple bytes(3 bytes) access
t 0230 00000000 0 2 0
t 0231 00000000 0 2 0
t 0230 00000000 0 2 1
t 0231 00000000 0 2 1
// x36 word accrss
t 0230 00000000 0 3 0
t 0231 00000000 0 3 0
t 0230 00000000 0 3 1
t 0231 00000000 0 3 1
//***************************************************************************
// Access via x64 mode
t 0230 01000000 0 0 0
t 0230 01000000 0 0 1
t 0230 80000000 0 0 0
t 0230 80000000 0 0 1
t 0230 01000000 0 1 0
t 0230 01000000 0 1 1
t 0230 80000000 0 1 0
t 0230 80000000 0 1 1
t 0230 01000000 0 2 0
t 0230 01000000 0 2 1
t 0230 80000000 0 2 0
t 0230 80000000 0 2 1
t 0230 01000000 0 3 0
t 0230 01000000 0 3 1
t 0230 80000000 0 3 0
t 0230 80000000 0 3 1
//****************************************************************************
// (6) memory block walk test
// 232 --- regular 233 --- xz
t 0232 00000000 0 0 0
t 0232 00000000 0 0 1
t 0233 00000000 0 0 0
t 0233 00000000 0 0 1
t 0232 00000000 0 1 0
t 0232 00000000 0 1 1
t 0233 00000000 0 1 0
t 0233 00000000 0 1 1
t 0232 00000000 0 2 0
t 0232 00000000 0 2 1
t 0233 00000000 0 2 0
t 0233 00000000 0 2 1
//****************************************************************************
// x64 mode
t 0232 80000000 0 0 0
t 0232 80000000 0 0 1
t 0232 01000000 0 0 0
t 0232 01000000 0 0 1
t 0232 80000000 0 1 0
t 0232 80000000 0 1 1
t 0232 01000000 0 1 0
t 0232 01000000 0 1 1
t 0232 80000000 0 2 0
t 0232 80000000 0 2 1
t 0232 01000000 0 2 0
t 0232 01000000 0 2 1
/***************************************************************************
// (7) memory single walk test checked via memory backdoor
// 330 -- regular 331 --- include xz value
// code base_addr addr_bits(23 in x36) size stall_cycles
// X36 single bytes access
t 0330 00000000 0 0 0
t 0331 00000000 0 0 0
t 0330 00000000 0 0 1
t 0331 00000000 0 0 1
// x36 double bytes(half word) access
t 0330 00000000 0 1 0
t 0331 00000000 0 1 0
t 0330 00000000 0 1 1
t 0331 00000000 0 1 1
// x36 triple bytes(3 bytes) access
t 0330 00000000 0 2 0
t 0331 00000000 0 2 0
t 0330 00000000 0 2 1
t 0331 00000000 0 2 1
// x36 word accrss
t 0330 00000000 0 3 0
t 0331 00000000 0 3 0
t 0330 00000000 0 3 1
t 0331 00000000 0 3 1
//****************************************************************************
// x64 mode
t 0330 80000000 0 0 0
t 0331 80000000 0 0 0
t 0330 01000000 0 0 0
t 0331 01000000 0 0 0
t 0330 80000000 0 1 0
t 0331 80000000 0 1 0
t 0330 01000000 0 1 0
t 0331 01000000 0 1 0
t 0330 80000000 0 2 0
t 0331 80000000 0 2 0
t 0330 01000000 0 2 0
t 0331 01000000 0 2 0
t 0330 80000000 0 3 0
t 0331 80000000 0 3 0
t 0330 01000000 0 3 0
t 0331 01000000 0 3 0
//****************************************************************************
// (8) memory block walk test checked via memory backdoor
// 332 --- regular 333 --- xz
t 0332 00000000 0 0 0
t 0332 00000000 0 0 1
t 0333 00000000 0 0 0
t 0333 00000000 0 0 1
t 0332 00000000 0 1 0
t 0332 00000000 0 1 1
t 0333 00000000 0 1 0
t 0333 00000000 0 1 1
t 0332 00000000 0 2 0
t 0332 00000000 0 2 1
t 0333 00000000 0 2 0
t 0333 00000000 0 2 1
t 0332 80000000 0 0 0
t 0332 01000000 0 0 0
t 0333 80000000 0 0 0
t 0333 01000000 0 0 0
t 0332 80000000 0 1 0
t 0332 01000000 0 1 0
t 0333 80000000 0 1 0
t 0333 01000000 0 1 0
t 0332 80000000 0 2 0
t 0332 01000000 0 2 0
t 0333 80000000 0 2 0
t 0333 01000000 0 2 0
//****************************************************************************
// (9) Memory backdoor read/write test
// 312(read) address times(!=0 random) address_range debug_?
// 313 (write) address times(!=0 random) address_range debug_?
//
t 0312 00000000 00000100 0001000 00000001
t 0312 00000000 0000100 00800000 00000001
t 0313 00000000 0000100 00001000 00000001
t 0313 00000000 0000100 00800000 00000001
//*****************************************************************************
// (20) close persistent socket and exit
k 0
//q