ebus.tst
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//****************************************************************************
//
// File: ebus.tst
// Check ability to read E-bus data via M-bus
//
// $Revision: 1.2 $
//
// File Format:
//
// t <id> <arg1> <arg2> <arg3> <arg4> - Run test id with the 4 args
// where id = decimal number
// argX = hex number
// q - Quit testing and shutdown verilog
// server
//
//****************************************************************************
//****************************************************************************
// Configure RDRAMs: 6 MB (MUST MATCH VERILOG BUILD!)
// If Verilog only contains 4MB RDRAM, then change 3rd argument to 00000004
//t 0000 00000001 00000006 00000000 00000000
//Haishan change to make it worked on 4Mbytes system
t 0000 00000001 00000004 00000000 00000000
// Set E-bus test mode on MI
t 0102 04300000 00000400 00000000 00000000
// Check MI mode register
t 0108 04300000 00000100 00000380 00000000
//****************************************************************************
// Do two pages of each bank of each RAM, each bank
t 0015 00000000 00000000 00000000 00000000
//****************************************************************************
// Check unaligned writes
// Fill some words with all ones
t 0102 00000000 0000000f 00000000 00000000
t 0102 00000004 0000000f 00000000 00000000
t 0102 00000008 0000000f 00000000 00000000
t 0102 0000000c 0000000f 00000000 00000000
t 0102 00000010 0000000f 00000000 00000000
t 0102 00000014 0000000f 00000000 00000000
t 0102 00000018 0000000f 00000000 00000000
t 0102 0000001c 0000000f 00000000 00000000
// Check them
t 0101 00000000 0000000f 00000000 00000000
t 0101 00000004 0000000f 00000000 00000000
t 0101 00000008 0000000f 00000000 00000000
t 0101 0000000c 0000000f 00000000 00000000
t 0101 00000010 0000000f 00000000 00000000
t 0101 00000014 0000000f 00000000 00000000
t 0101 00000018 0000000f 00000000 00000000
t 0101 0000001c 0000000f 00000000 00000000
// Write zeros to varying alignments
t 0102 00000000 00000000 00000000 00000000
t 0102 00000009 00000000 00000000 00000000
t 0102 00000012 00000000 00000000 00000000
t 0102 0000001b 00000000 00000000 00000000
// Check results
t 0101 00000000 00000000 00000000 00000000
t 0101 00000004 0000000f 00000000 00000000
t 0101 00000008 00000008 00000000 00000000
t 0101 0000000c 00000007 00000000 00000000
t 0101 00000010 0000000c 00000000 00000000
t 0101 00000014 00000003 00000000 00000000
t 0101 00000018 0000000e 00000000 00000000
t 0101 0000001c 00000001 00000000 00000000
//****************************************************************************
// Check unaligned reads
// Fill some words with known pattern
t 0102 00000000 0000000f 00000000 00000000
t 0102 00000004 00000000 00000000 00000000
// Check them
t 0101 00000000 0000000f 00000000 00000000
t 0101 00000004 00000000 00000000 00000000
// Read from varying alignments - verify lower bits are ignored
t 0101 00000000 0000000f 00000000 00000000
t 0101 00000001 0000000f 00000000 00000000
t 0101 00000002 0000000f 00000000 00000000
t 0101 00000003 0000000f 00000000 00000000
//****************************************************************************
// Clear E-bus test mode on MI and make sure everything is back to normal
t 0102 04300000 00000200 00000000 00000000
// Check MI mode register
t 0108 04300000 00000000 00000380 00000000
// Make sure MI is back to normal by writing some patterns there
t 0103 00000000 01234567 01234567 00000000
t 0103 00100000 12345678 12345678 00000000
t 0103 00200000 23456789 23456789 00000000
t 0103 00300000 3456789a 3456789a 00000000
//****************************************************************************
// QUIT
//****************************************************************************
q