rdp_2stall.tst
2.31 KB
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// Run a display list in a .rdram file through the rdp
// with stalls caused by ai DMA's
// AND stalls caused by Video DMA
// config rdram
t 0000 00000000 00000000 00000000 00000000
// halt sp
t 0103 04040010 00000002 00000001 00000000
// Init Video Interface (VI) to get proper video clock signal into AI
t 0102 04400000 00000000 00000000 00000000
//****************************TURN ON VIDEO DMA*******************************
// Do a mem dump to make sure rdram was loaded correctly
t 0106 00001000 00000002 00000000 00000000
t 0106 00001080 00000002 00000000 00000000
t 0106 00001100 00000002 00000000 00000000
t 0106 00001180 00000002 00000000 00000000
// Read VI_CTRL, make sure is zeroed out
t 0101 04400000 00000000 00000000 00000000
// Write-Read VI_ORIGIN
t 0103 04400004 00001000 00001000 00000000
// Write-Read VI_WIDTH
t 0103 04400008 00000020 00000020 00000000
// Write-Read VI_V_INT
t 0103 0440000c 000003ff 000003ff 00000000
// Write-Read VI_BURST
t 0103 04400014 00820404 00820404 00000000
// Write-Read VI_V_SYNC
t 0103 04400018 00000011 00000011 00000000
// Write-Read VI_H_SYNC
t 0103 0440001c 00000130 00000130 00000000
// Write-Read VI_LEAP
t 0103 04400020 01300130 01300130 00000000
// Write-Read VI_H_START
t 0103 04400024 00200040 00200040 00000000
// Write-Read VI_V_START
t 0103 04400028 0005000d 0005000d 00000000
// Write-Read VI_V_BURST
t 0103 0440002c 0005000d 0005000d 00000000
// Write-Read VI_X_SCALE
t 0103 04400030 00000400 00000400 00000000
// Write-Read VI_Y_SCALE
t 0103 04400034 00000400 00000400 00000000
// Write-Read VI_CTRL
t 0103 04400000 00000303 00000303 00000000
// Write VI_V_CURRENT
t 0102 04400010 00000000 00000000 00000000
// Read VI_V_CURRENT
t 0100 04400010 00000000 00000000 00000000
//*****************************************************
// increase the frequency of the AI DMAs for more stalls
t 0102 04400000 00000130 00000000 00000000
//
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// DMA 20 Bytes (RDRAM -> AI) (8 byte aligned address & data)
// do as many of these as needed to introduce stalls
t 0043 00000000 000FFFF8 00000000 00000000
t 0043 00000000 000FFFF8 00000000 00000000
t 0043 00000000 000FFFF8 00000000 00000000
t 0043 00000000 000FFFF8 00000000 00000000
// Run DP list
t 0070 00000000 00000000 00000000 00000000
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