display.v
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//
// Display for Verilog version of RDP
//
//
// 9/16/94 RJM
//
`define MAX_X 320
`define MAX_Y 240
`define DISP_Y_DELAY y_d27
`define DISP_X_DELAY x_d27
module display(gclk, span_r, span_g, span_b, span_a, span_clr_we, st_span, start_x, new_prim, y_h);
//
// Inputs
//
input gclk;
input [7:0] span_r;
input [7:0] span_g;
input [7:0] span_b;
input [2:0] span_a;
input span_clr_we;
input st_span;
input [11:0] start_x;
input new_prim;
input [63:0] y_h;
//
// Delay x/y
//
reg left;
reg [11:0] y_d1;
reg [11:0] y_d2;
reg [11:0] y_d3;
reg [11:0] y_d4;
reg [11:0] y_d5;
reg [11:0] y_d6;
reg [11:0] y_d7;
reg [11:0] y_d8;
reg [11:0] y_d9;
reg [11:0] y_d10;
reg [11:0] y_d11;
reg [11:0] y_d12;
reg [11:0] y_d13;
reg [11:0] y_d14;
reg [11:0] y_d15;
reg [11:0] y_d16;
reg [11:0] y_d17;
reg [11:0] y_d18;
reg [11:0] y_d19;
reg [11:0] y_d20;
reg [11:0] y_d21;
reg [11:0] y_d22;
reg [11:0] y_d23;
reg [11:0] y_d24;
reg [11:0] y_d25;
reg [11:0] y_d26;
reg [11:0] y_d27;
reg [11:0] x_d1;
reg [11:0] x_d2;
reg [11:0] x_d3;
reg [11:0] x_d4;
reg [11:0] x_d5;
reg [11:0] x_d6;
reg [11:0] x_d7;
reg [11:0] x_d8;
reg [11:0] x_d9;
reg [11:0] x_d10;
reg [11:0] x_d11;
reg [11:0] x_d12;
reg [11:0] x_d13;
reg [11:0] x_d14;
reg [11:0] x_d15;
reg [11:0] x_d16;
reg [11:0] x_d17;
reg [11:0] x_d18;
reg [11:0] x_d19;
reg [11:0] x_d20;
reg [11:0] x_d21;
reg [11:0] x_d22;
reg [11:0] x_d23;
reg [11:0] x_d24;
reg [11:0] x_d25;
reg [11:0] x_d26;
reg [11:0] x_d27;
integer x;
integer y;
integer r;
integer g;
integer b;
integer a;
reg [1:256*8] filename;
integer ret_val;
//
// Initialize frame buffer
//
initial
begin
if ($open_frame_buffer(`MAX_X, `MAX_Y) == -1)
begin
$write("Cannot open frame buffer\n");
$finish();
end
end
//
// Grab start x
//
always @(posedge gclk)
begin
if(st_span)
x_d1 <= start_x;
else
begin
if(left)
x_d1 <= x_d1 + 1; /* 1 cycle for now */
else // right major
x_d1 <= x_d1 - 1; /* 1 cycle for now */
end
end
//
// Grab start y
// make a named event so we can test for it in an if statement
//
always @(posedge new_prim)
begin
y_d1 <= y_h[12:2]; /* load */
left <= y_h[55];
end
//
// Increment y every span
//
always @(posedge gclk)
begin
if(st_span)
y_d1 <= y_d1 + 1; /* increment */
else
y_d1 <= y_d1; /* hold */
end
//
// Delay start x, y
//
always @(posedge gclk)
begin
x_d2 <= x_d1;
x_d3 <= x_d2;
x_d4 <= x_d3;
x_d5 <= x_d4;
x_d6 <= x_d5;
x_d7 <= x_d6;
x_d8 <= x_d7;
x_d9 <= x_d8;
x_d10 <= x_d9;
x_d11 <= x_d10;
x_d12 <= x_d11;
x_d13 <= x_d12;
x_d14 <= x_d13;
x_d15 <= x_d14;
x_d16 <= x_d15;
x_d17 <= x_d16;
x_d18 <= x_d17;
x_d19 <= x_d18;
x_d20 <= x_d19;
x_d21 <= x_d20;
x_d22 <= x_d21;
x_d23 <= x_d22;
x_d24 <= x_d23;
x_d25 <= x_d24;
x_d26 <= x_d25;
x_d27 <= x_d26;
y_d2 <= y_d1;
y_d3 <= y_d2;
y_d4 <= y_d3;
y_d5 <= y_d4;
y_d6 <= y_d5;
y_d7 <= y_d6;
y_d8 <= y_d7;
y_d9 <= y_d8;
y_d10 <= y_d9;
y_d11 <= y_d10;
y_d12 <= y_d11;
y_d13 <= y_d12;
y_d14 <= y_d13;
y_d15 <= y_d14;
y_d16 <= y_d15;
y_d17 <= y_d16;
y_d18 <= y_d17;
y_d19 <= y_d18;
y_d20 <= y_d19;
y_d21 <= y_d20;
y_d22 <= y_d21;
y_d23 <= y_d22;
y_d24 <= y_d23;
y_d25 <= y_d24;
y_d26 <= y_d25;
y_d27 <= y_d26;
end
//
// Write Frame Buffer per pixel
//
always @(posedge gclk)
begin
x = `DISP_X_DELAY;
y = (`DISP_Y_DELAY - 1);
r = span_r;
g = span_g;
b = span_b;
a = span_a;
if(span_clr_we)
ret_val = $put_pixel(x, y, r, g, b, a);
if(ret_val == -1)
$write("Error in put_pixel\n");
end
//
// Close Frame Buffer
//
always @(top_level.driver.WriteFrameBuffer)
begin
if ($getstr$plusarg("fb=", filename) == 1)
begin
$write("Writing frame buffer\n");
if ($write_frame_buffer(filename) == -1)
begin
$write("Cannot write frame buffer\n");
end
else
$finish();
end
end
endmodule