test.0 2.62 KB
####################################################
#  this file produced by tab2sim                   #
#                                                  #
#  tab2sim written by Rob Moore                    #
#  Silicon Graphics, Inc.                          #
#  November  1994                                  #
####################################################

alias i inputs
alias c charged
alias t test

forced high vdd
forced low vss

echo #
echo #  Test all signal types, tab2sim
echo #
clock gclk 0(8.00) 1(8.00) 
echo #sig_g[63:0]		@V
echo #  Tristate output example
echo #sig_f[8:0]       	@O @S 14 @V tsig_f_dv
echo #sig_f_dv		@O @S 2
echo #tsig_f_dv		@V
echo #original sim at cycle :0 absolute time:0.00
s 1.00
l sig_d
s 1.00
i 'h0 sig_a
s 1.00
c * sig_c
s 2.00
t sig_c 'h00
s 10.00
t sig_b 'h0
s 2.00
h sig_d
s 1.00
i 'h1 sig_a
s 1.00
i 'h00 sig_c
s 12.00
t sig_b 'h1
s 2.00
l sig_d
s 1.00
i 'h2 sig_a
s 1.00
c * sig_c
s 12.00
t sig_b 'h0
t sig_e 'h555
s 2.00
h sig_d
s 1.00
i 'h3 sig_a
s 1.00
i 'h11 sig_c
s 12.00
t sig_b 'h1
t sig_e 'haaa
s 2.00
l sig_d
s 1.00
i 'h4 sig_a
s 1.00
c * sig_c
s 2.00
t sig_c 'h22
s 10.00
t sig_b 'h1
s 2.00
h sig_d
s 2.00
i 'h22 sig_c
s 12.00
t sig_b 'h1
s 2.00
l sig_d
s 2.00
c * sig_c
s 2.00
t sig_c 'h33
s 10.00
t sig_b 'h0
t sig_e 'h555
s 2.00
h sig_d
s 1.00
i 'h7 sig_a
s 1.00
i 'h33 sig_c
s 12.00
t sig_b 'h0
t sig_e 'haaa
s 3.00
i 'h8 sig_a
s 1.00
i 'h44 sig_c
s 12.00
t sig_b 'h1
s 4.00
i 'h44 sig_c
s 12.00
t sig_b 'h1
s 2.00
l sig_d
s 1.00
i 'ha sig_a
s 1.00
c * sig_c
s 12.00
t sig_b 'h1
t sig_e 'h555
s 2.00
h sig_d
s 1.00
i 'hb sig_a
s 1.00
i 'h55 sig_c
s 12.00
t sig_b 'h0
t sig_e 'haaa
s 3.00
i 'hc sig_a
s 1.00
i 'h66 sig_c
s 12.00
t sig_b 'h0
s 3.00
i 'hd sig_a
s 1.00
i 'h66 sig_c
s 12.00
t sig_b 'h1
s 3.00
i 'he sig_a
s 1.00
i 'h77 sig_c
s 12.00
t sig_b 'h1
t sig_e 'h555
s 3.00
i 'hf sig_a
s 1.00
i 'h77 sig_c
s 12.00
t sig_b 'h0
t sig_e 'haaa
s 4.00
i 'h77 sig_c
s 12.00
t sig_b 'h0
t sig_e 'haaa
s 4.00
i 'h77 sig_c
s 12.00
t sig_b 'h0
t sig_e 'haaa
s 4.00
i 'h77 sig_c
s 12.00
t sig_b 'h0
t sig_e 'haaa
s 4.00
i 'h77 sig_c
s 12.00
t sig_b 'h0
t sig_e 'haaa
s 1.00
echo #original sim at cycle :20 absolute time:320.00
s 3.00
i 'h77 sig_c
s 12.00
t sig_b 'h0
t sig_e 'haaa
s 4.00
i 'h77 sig_c
s 12.00
t sig_b 'h0
t sig_e 'haaa
s 4.00
i 'h77 sig_c
s 12.00
t sig_b 'h0
t sig_e 'haaa
s 4.00
i 'h77 sig_c
s 12.00
t sig_b 'h0
t sig_e 'haaa
s 4.00
i 'h77 sig_c
s 12.00
t sig_b 'h0
t sig_e 'haaa
s 4.00
i 'h77 sig_c
s 12.00
t sig_b 'h0
t sig_e 'haaa
s 4.00
i 'h77 sig_c
s 12.00
t sig_b 'h0
t sig_e 'haaa
s 4.00
i 'h77 sig_c
s 12.00
t sig_b 'h0
t sig_e 'haaa
s 4.00
i 'h77 sig_c
s 12.00
t sig_b 'h0
t sig_e 'haaa
s 0.00