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/*********************************************************************
 *								     *
 *  Title:   AVP.h.						     *
 *  Author:  Mike Gupta.					     *
 *  Date:    01/01/92.						     *
 *  SCCS:    %W% %G%
 *  Adapted by Evan Y. Wang for Project Reality SU Verification.     *
 *  (07/14/94)							     *
 *********************************************************************/

/*********************************************************************
 *								     *
 *  Description:						     *
 *	This file is modified from the AVP.h written by Mike Gupta   *
 *	which defines various macros to test MIPS R-Series ISA.	 It  *
 *	is used here for testing the scalar unit of the Reality	     *
 *	Signal Processing unit.					     *
 *								     *
 *  The operands passed into the macros are:			     *
 *	Op:	 Instruction to be tested.			     *
 *	Op[1|2]: Operators to be used to test each other.	     *
 *	r[A|B]:	 Register to be used as an operand to instruction.   *
 *	r[T|X]:	 Register to be used as Temporary Register.	     *
 *	Op[A|B]: Operand to be used for r[A|B].			     *
 *	Imm:	 16 bit Immediate value for Instructions.	     *
 *	Res:	 Expected result of the Operation.		     *
 *								     *
 *	Note:  All 64 bit Operands / Results are specified as two    *
 *	       consecutive 32 bit values.			     *
 *								     *
 *  The macro name is defined as Check_[Function]_[Op Type].	     *
 *	Function is one of ALU, Br, BrL, Div, Exc, J, JAL, JALR, JR, *
 *			   Ld, LdLR, LL, MTMF, Mul, SC, St, StLR,    *
 *			   Sync, Trap.				     *
 *	Op Type	 is one of W = Word, D = Double, I = Immediate.	     *
 *								     *
 *								     *
 *  Compile Options:						     *
 *								     *
 *								     *
 *  Special Notes:						     *
 *	This file should be maintained Micro-Architecture independent*
 *    for portability reasons.					     *
 *								     *
 *  (C) Copyright 1992 by MIPS Computer Systems, Inc.		     *
 *  All Rights Reserved.					     *
 *********************************************************************/
#ifndef _suregre_h_
#define _suregre_h_

#define r0          $0		/* reserved - always zero	*/
#define r1          $1		/* if (0x5A5A) passed; else tno;*/
#define r2          $2
#define r3          $3
#define r4          $4
#define r5          $5
#define r6          $6
#define r7          $7
#define r8          $8
#define r9          $9
#define r10         $10
#define r11         $11
#define r12         $12
#define r13         $13
#define r14         $14
#define r15         $15
#define r16         $16
#define r17         $17
#define r18         $18
#define r19         $19
#define r20         $20
#define r21         $21
#define r22         $22
#define r23         $23
#define r24         $24
#define r25         $25
#define r26         $26
#define r27         $27
#define r28         $28
#define r29         $29
#define r30         $30
#define r31         $31		/* reserved as link register	*/

#define e0          0
#define e1          1
#define e2          2
#define e3          3
#define e4          4
#define e5          5
#define e6          6
#define e7          7
#define e8          8
#define e9          9
#define e10         10
#define e11         11
#define e12         12
#define e13         13
#define e14         14
#define e15         15

#define v0	    $v0
#define v1	    $v1
#define v2          $v2
#define v3          $v3
#define v4          $v4
#define v5          $v5
#define v6          $v6
#define v7          $v7
#define v8          $v8
#define v9          $v9
#define v10         $v10
#define v11         $v11
#define v12         $v12
#define v13         $v13
#define v14         $v14
#define v15         $v15
#define v16         $v16
#define v17         $v17
#define v18         $v18
#define v19         $v19
#define v20         $v20
#define v21         $v21
#define v22         $v22
#define v23         $v23
#define v24         $v24
#define v25         $v25
#define v26         $v26
#define v27         $v27
#define v28         $v28
#define v29         $v29
#define v30         $v30
#define v31         $v31		/* reserved as link register	*/

#define vcc	    $v1

#define	LBL(n)	"L" ## n

/****************************************************************
 * Load Immediate macro (LI)					*
 ****************************************************************/
#define LI_NUMLINES	2
#define LI(rR,OpH,OpL)						  \
	lui	 rR, OpH;					  \
	ori	 rR, rR,   OpL;

/****************************************************************
 *  This TestCaseID macro puts the assigned test number into	*
 *  the high half-word of register 30, so when a test Fails, it	*
 *  could easily be determine which test case it is.		*
 ****************************************************************/
#define TCID_NUMLINES	1
#define TestCaseID(n)						  \
	lui	 r1, n;

/****************************************************************
 * Used for:	LUI.						*
 ****************************************************************/
#define ALUWI_NUMLINES	(TCID_NUMLINES+0*LI_NUMLINES+12)
#define MAX_ALU_WI_TCS	(MAX_INSTR_PER_FILE / ALUWI_NUMLINES)
#define ChkAluWI(n,Op,rR,RH,RL,Imm,rT)				  \
	TestCaseID(n);			/* Load test number	*/\
	LI	(rT, RH,  RL);		/* Load supposed rR val	*/\
	bne	 rT, rR,  Fail;		/* Prelim check on rR	*/\
	nop				/* Fill delay slot	*/\
	and	 rT, r0,  r0;		/* Place zero into rT	*/\
	nor	 rR, r0,  r0;		/* Place -1   into rR	*/\
	beq	 rT, rR,  Fail;		/* Prelim check		*/\
	nop				/* Fill delay slot	*/\
	Op	 rT, Imm;		/* Load expected result	*/\
	Op	 rR, Imm;		/* Perform Req'ted Op	*/\
	bne	 rT, rR,  Fail;		/* Check Result		*/\
	nop				/* Fill delay slot	*/

/****************************************************************
 * Used for:	ADD, ADDU, AND, NOR, OR, SLLV, SLT, SLTU,	*
 *		SRAV, SRLV, SUB, SUBU, XOR.			*
 ****************************************************************/
#define ALUWWW_NUMLINES	(TCID_NUMLINES+7*LI_NUMLINES+7)
#define MAX_ALU_WWW_TCS	(MAX_INSTR_PER_FILE / ALUWWW_NUMLINES)
#define ChkAluWWW(n,Op,rR,RoH,RoL,rA,rB,RH,RL,AH,AL,BH,BL,rT)	  \
	TestCaseID(n);			/* Load test number	*/\
	LI	(rT, RoH, RoL);		/* Load supposed rR val	*/\
	bne	 rT, rR,  Fail;		/* Prelim check failed	*/\
	nop	 ;			/* Fill delay slot	*/\
	LI	(rT, RH,  RL);		/* Load predicted result*/\
	LI	(rA, AH,  AL);		/* Load Operand A	*/\
	LI	(rB, BH,  BL);		/* Load Operand B	*/\
	Op	 rR, rA,  rB;		/* Execute test instr	*/\
	bne	 rT, rR,  Fail;		/* Check result		*/\
	nop	;			/* Fill delay slot	*/\
	LI	(rT, AH,  AL);		/* Reload Op A into rT	*/\
	bne	 rT, rA,  Fail;		/* Modified input reg	*/\
	LI	(rT, BH,  BL);		/* Reload Op A into rT	*/\
	bne	 rT, rB,  Fail;		/* Modified input reg	*/\
	LI	(rT, RH,  RL);		/* Restore rT		*/

/****************************************************************
 * Used for:	ADDI, ADDIU, ANDI, ORI, SLL, SLTI, SLTIU, SRA,	*
 *		SRL, XORI.					*
 ****************************************************************/
#define ALUWWI_NUMLINES	(TCID_NUMLINES+5*LI_NUMLINES+5)
#define MAX_ALU_WWI_TCS	(MAX_INSTR_PER_FILE / ALUWWI_NUMLINES)
#define ChkAluWWI(n,Op,rR,RoH,RoL,rA,Imm,RH,RL,AH,AL,rT)	  \
	TestCaseID(n);			/* Load test number	*/\
	LI	(rT, RoH, RoL);		/* Load supposed rR val	*/\
	bne	 rT, rR,  Fail;		/* Prelim check field	*/\
	LI	(rT, RH,  RL);		/* Load Result		*/\
	LI	(rA, AH,  AL);		/* Load Operand		*/\
	Op	 rR, rA,  Imm;		/* Perform Req'ted Op	*/\
	bne	 rT, rR,  Fail;		/* Check Result		*/\
	nop	;			/* Fill delay slot	*/\
	LI	(rT, AH,  AL);		/* Reload Op A into rT	*/\
	bne	 rT, rA,  Fail;		/* Modified input reg	*/\
	LI	(rT, RH,  RL);		/* Restore rT		*/

/****************************************************************
 * Used for:	BEQ, BNE.					*
 ****************************************************************/
#define BRWWF_NUMLINES	(TCID_NUMLINES+2*LI_NUMLINES+5)
#define ChkBrWWF(n,Op,rA,rB,AH,AL,BH,BL,rT)			  \
	TestCaseID(n);			/* Load test number	*/\
	nor	 rT, r0,  r0;		/* Trace Execution	*/\
	LI	(rA, AH,  AL);		/* Load Operand A	*/\
	LI	(rB, BH,  BL);		/* Load Operand B	*/\
	Op	 rA, rB,  Fail;		/* Perform Requested Op	*/\
	nor	 rT, rT,  rT;		/* Check Delay Slot Exec*/\
	bne	 r0, rT,  Fail;		/* Check Result		*/\
	nop				/* Fill delay slot	*/

/****************************************************************
 * Used for:	BEQ, BEQL, BNE, BNEL.				*
 ****************************************************************/
#define BRWWT_NUMLINES	(TCID_NUMLINES+2*LI_NUMLINES+7)
#define MAX_BR_WW_TCS	(MAX_INSTR_PER_FILE / BRWWT_NUMLINES)
#define ChkBrWWT(n,Op,rA,rB,AH,AL,BH,BL,rT)			  \
	TestCaseID(n);			/* Load test number	*/\
	nor	 rT, r0,  r0;		/* Trace Execution	*/\
	LI	(rA, AH,  AL);		/* Load Operand		*/\
	LI	(rB, BH,  BL);		/* Load Operand		*/\
	Op	 rA, rB,  L##n;		/* Perform Req.ted Oper	*/\
	nor	 rT, rT,  rT;		/* Check Delay Slot Exec*/\
	j	 Fail;			/* Shouldn't Execute	*/\
	nor	 rT, rT,  rT;		/* Shouldn't Execute	*/\
L##n:	bne	 r0, rT,  Fail;		/* Check Result		*/\
	nop				/* Fill delay slot	*/

/****************************************************************
 * Used for:	BGEZ, BGEZL, BGTZ, BGTZL,			*
 *		BLEZ, BLEZL, BLTZ, BLTZL.			*
 ****************************************************************/
#define BRWF_NUMLINES	(TCID_NUMLINES+LI_NUMLINES+5)
#define ChkBrWF(n,Op,rA,AH,AL,rT)				  \
	TestCaseID(n);			/* Load test number	*/\
	nor	 rT, r0,  r0;		/* Trace Execution	*/\
	LI	(rA, AH,  AL);		/* Load Operand.	*/\
	Op	 rA, Fail;		/* Perform Requested Op	*/\
	nor	 rT, rT,  rT;		/* Check Delay Slot Exec*/\
	bne	 r0, rT,  Fail;		/* Check Result		*/\
	nop				/* Fill delay slot	*/

/****************************************************************
 * Used for:	BGEZ, BGEZL, BGTZ, BGTZL,			*
 *		BLEZ, BLEZL, BLTZ, BLTZL.			*
 ****************************************************************/
#define BRWT_NUMLINES	(TCID_NUMLINES+LI_NUMLINES+7)
#define MAX_BR_W_TCS	(MAX_INSTR_PER_FILE / BRWT_NUMLINES)
#define ChkBrWT(n,Op,rA,AH,AL,rT)				  \
	TestCaseID (n);			/* Load test number	*/\
	nor	 rT, r0,  r0;		/* Trace Execution	*/\
	LI	(rA, AH,  AL);		/* Load Operand		*/\
	Op	 rA, L##n;		/* Perform Requested Op	*/\
	nor	 rT, rT,  rT;		/* Check Delay Slot Exec*/\
	j	 Fail;			/* Shouldn't Execute	*/\
	nor	 rT, rT,  rT;		/* Shouldn't Execute	*/\
L##n:	bne	 r0, rT,  Fail;		/* Check Result		*/\
	nop				/* Fill delay slot	*/

/****************************************************************
 * Used for:	BGEZAL, BLTZAL.					*
 ****************************************************************/
#define BRLWF_NUMLINES	(TCID_NUMLINES+LI_NUMLINES+11)
#define ChkBrlWF(n,Op,rA,AH,AL,rT)				  \
	TestCaseID(n);			/* Load test number	*/\
	LI	(rA, AH,  AL);		/* Load Operand.	*/\
	nor	 rT, r0,  r0;		/* Trace Execution	*/\
	beq	 rT, r0,  L##n##1;	/* Return when done	*/\
	nop	;			/* Fill delay slot	*/\
	Op	 rA, Fail;		/* Perform Req'ted Oper	*/\
	nor	 rT, rT,  rT;		/* Check Delay Slot Exec*/\
	bne	 r0, rT,  Fail;		/* Check Result		*/\
	addi	 r31,r31, 0xFFF0;	/* Point to Ret Address	*/\
	jr	 r31;			/* Return to Normal Code*/\
	nop	;			/* Fill delay slot	*/\
	j	 Fail;			/* Shouldn't Execute.	*/\
	nor	 rT, rT,  rT;		/* Shouldn't Execute.	*/\
L##n##1:

/****************************************************************
 * Used for:	BGEZAL, BGEZALL, BLTZAL, BLTZALL.		*
 ****************************************************************/
#define BRLWT_NUMLINES	(TCID_NUMLINES+LI_NUMLINES+13)
#define MAX_BRL_W_TCS	(MAX_INSTR_PER_FILE / BRLWT_NUMLINES)
#define ChkBrlWT(n,Op,rA,AH,AL,rT)				  \
	TestCaseID(n);			/* Load test number	*/\
	LI	(rA, AH,  AL);		/* Load Operand		*/\
	nor	 rT, r0,  r0;		/* Trace Execution	*/\
	beq	 rT, r0,  L##n##2;	/* Return when done	*/\
	nop	;			/* Fill delay slot	*/\
	Op	 rA, L##n##1;		/* Perform Requested Op	*/\
	nor	 rT, rT,  rT;		/* Check Delay Slot Exec*/\
	j	 Fail;			/* Shouldn't Execute	*/\
	nor	 rT, rT,  rT;		/* Check Delay Slot Exec*/\
L##n##1:bne	 r0, rT,  Fail;		/* Check Result		*/\
	addi	 r31,r31, 0xFFF0;	/* Point to Return Addr	*/\
	jr	 r31;			/* Ret to Normal Code	*/\
	nop	;						  \
	j	 Fail;			/* Shouldn't Execute	*/\
	nor	 rT, rT,  rT;		/* Shouldn't Execute	*/\
L##n##2:

/****************************************************************
 * Used for:	J.						*
 ****************************************************************/
#define J_NUMLINES	(TCID_NUMLINES+15)
#define MAX_J_TCS	(MAX_INSTR_PER_FILE / J_NUMLINES)
#define ChkJ(n,Op,rT)						  \
	TestCaseID(n);			/* Load test number	*/\
	nor	 rT, r0,   r0;		/* Trace Execution	*/\
	Op	 L##n##1;		/* Test forward jump	*/\
	nor	 rT, rT,   rT;		/* Delay Slot #1 (DS1)	*/\
	j	 Fail;			/* Shouldn't Execute	*/\
	nor	 rT, rT,   rT;		/* Shouldn't Execute	*/\
L##n##2:bne	 r0, rT,   Fail;	/* Check DS2 execution	*/\
	nop	;			/* Delay slot filler	*/\
	j	 L##n##3;		/* Exit test		*/\
	nop	;			/* Delay slot filler	*/\
L##n##1:bne	 r0, rT,   Fail;	/* Check DS1 execution	*/\
	nor	 rT, rT,   rT;		/* Trace Execution	*/\
	Op	 L##n##2;		/* Test backward jump	*/\
	nor	 rT, rT,   rT;		/* Delay Slot #2 (DS2)	*/\
	j	 Fail;			/* Shouldn't Execute	*/\
	nor	 rT, rT,   rT;		/* Shouldn't Execute	*/\
L##n##3:

/****************************************************************
 * Used for:	JAL.						*
 ****************************************************************/
#define JAL_NUMLINES	(TCID_NUMLINES+23)
#define MAX_JAL_TCS	(MAX_INSTR_PER_FILE / JAL_NUMLINES)
#define ChkJAL(n,Op,rT)						  \
	TestCaseID(n);			/* Load test number	*/\
	nor	 rT, r0,   r0;		/* Trace Execution	*/\
	beq	 rT, r0,   L##n##2;	/* Goto next case if dn	*/\
	nop	;			/* Fill delay slot	*/\
	Op	 L##n##1;		/* Test forward jump	*/\
	nor	 rT, rT,   rT;		/* Delay Slot #1 (DS1)	*/\
	j	 Fail;			/* Shouldn't Execute	*/\
	nor	 rT, rT,   rT;		/* Shouldn't Execute	*/\
L##n##3:beq	 r0, rT,   Fail;	/* Check Result		*/\
	addi	 r31,r31,  0xFFF0;	/* Point to Return Addr	*/\
	jr	 r31;			/* Return to Normal Code*/\
	nop	;			/* Fill delay slot	*/\
L##n##1:bne	 r0, rT,   Fail;	/* Check DS1 execution	*/\
	addi	 r31,r31,  0xFFF0;	/* Point to Return Addr	*/\
	jr	 r31;			/* Return.		*/\
	nop	;			/* Fill delay slot	*/\
	j	 Fail;			/* Shouldn't Execute	*/\
	nor	 rT, rT,   rT;		/* Shouldn't Execute	*/\
L##n##2:bne	 rT, r0,   L##n##4;	/* Return if done	*/\
	nop	;			/* Fill delay slot	*/\
	Op	 L##n##3;		/* Perform Requested Op	*/\
	nor	 rT, rT,   rT;		/* Check Delay Slot Exec*/\
	j	 Fail;			/* Shouldn't Execute	*/\
	nor	 rT, rT,   rT;		/* Shouldn't Execute	*/\
L##n##4:

/****************************************************************
 * Used for:	JALR.						*
 ****************************************************************/
#define JALR_NUMLINES	(TCID_NUMLINES+28)
#define MAX_JALR_TCS	(MAX_INSTR_PER_FILE / JALR_NUMLINES)
#define ChkJALR(n,Op,rA,rB,rT)					  \
	TestCaseID(n);			/* Load test number	*/\
	nor	 rT, r0,   r0;		/* Don't jump yet	*/\
	bgezal	 rT, L##n##1;		/* Load Jump Target Addr*/\
	addi	 rA, r31,  0x28;	/* - our hack for la	*/\
	nor	 rT, r0,   r0;		/* Trace Execution	*/\
	beq	 rT, r0,   L##n##2;	/* Next case if done	*/\
	nop	;			/* Fill delay slot	*/\
	Op	 rB, rA;		/* Perform Requested Op	*/\
	nor	 rT, rT,   rT;		/* Check Delay Slot Exec*/\
	j	 Fail;			/* Shouldn't Execute	*/\
	nor	 rT, rT,   rT;		/* Shouldn't Execute	*/\
L##n##3:beq	 r0, rT,   Fail;	/* Check Result.	*/\
	addi	 rB, rB,   0xFFF0;	/* Point to Return Addr	*/\
	jr	 rB;			/* Return to Normal Code*/\
	nop	;			/* Fill delay slot	*/\
L##n##1:bne	 r0, rT,   Fail;	/* Check Result		*/\
	addi	 rB, rB,   0xFFF0;	/* Point to Return Addr	*/\
	jr	 rB;			/* Return.		*/\
	nop	;			/* Fill delay slot	*/\
	j	 Fail;			/* Shouldn't Execute	*/\
	nor	 rT, rT,   rT;		/* Shouldn't Execute	*/\
L##n##2:bltzal	 rT, L##n##3;		/* Load Jump Target Addr*/\
	addi	 rA, r31,  0xFFD4;	/* - our hack for la	*/\
	bne	 rT, r0,   L##n##4;	/* Return if done.	*/\
	nop	;			/* Fill delay slot	*/\
	Op	 rB, rA;		/* Perform Requested Op	*/\
	nor	 rT, rT,   rT;		/* Check Delay Slot Exec*/\
	j	 Fail;			/* Shouldn't Execute	*/\
	nor	 rT, rT,   rT;		/* Shouldn't Execute	*/\
L##n##4:

/****************************************************************
 * Used for:	JR.						*
 ****************************************************************/
#define JR_NUMLINES	(TCID_NUMLINES+18)
#define MAX_JR_TCS	(MAX_INSTR_PER_FILE / JR_NUMLINES)
#define ChkJR(n,Op,rA,rT)					  \
	TestCaseID(n);			/* Load test number	*/\
	nor	 rT, r0,   r0;		/* Trace Execution	*/\
	bgezal	 rT, Fail;		/* Load Jump Target Addr*/\
	addi	 rA, r31,  0x20;	/* - our hack for la(1f)*/\
	Op	 rA;			/* Perform Requested Op	*/\
	nor	 rT, rT,   rT;		/* Check Delay Slot Exec*/\
	j	 Fail;			/* Shouldn't Execute	*/\
	nor	 rT, rT,   rT;		/* Shouldn't Execute	*/\
L##n##2:beq	 r0, rT,   Fail;	/* Check Result.	*/\
	nop	;			/* Fill delay slot	*/\
	j	 L##n##3;		/* Return to Normal Code*/\
	nop	;			/* Fill delay slot	*/\
L##n##1:bne	 r0, rT,   Fail;	/* Check Result		*/\
	bltzal	 rT, Fail;		/* Load Jump Target Addr*/\
	addi	 rA, r31,  0xFFE8;	/* - our hack for la(2b)*/\
	Op	 rA;			/* Perform Requested Op	*/\
	nor	 rT, rT,   rT;		/* Check Delay Slot Exec*/\
	j	 Fail;			/* Shouldn't Execute	*/\
	nor	 rT, rT,   rT;		/* Shouldn't Execute	*/\
L##n##3:

/****************************************************************
 * Used for:	LB, LBU, LH, LHU, LW.				*
 ****************************************************************/
#define LD_NUMLINES	(TCID_NUMLINES+3*LI_NUMLINES+5)
#define MAX_LD_TCS	(MAX_INSTR_PER_FILE / LD_NUMLINES)
#define ChkLd(n,Op,rR,RoH,RoL,Imm,rB,BH,BL,RH,RL,rT)		  \
	TestCaseID(n);			/* Load test number	*/\
	LI	(rT, RoH, RoL);		/* Load supposed rR val	*/\
	bne	 rT, rR,  Fail;		/* Prelim check failed	*/\
	nop	 ;			/* Fill delay slot	*/\
	LI	(rT, RH,  RL);		/* Load expected result	*/\
	LI	(rB, BH,  BL);		/* Load load address	*/\
	Op	 rR, Imm (rB);		/* Load from address	*/\
	bne	 rR, rT,  Fail;		/* Check result		*/\
	nop				/* Fill delay slot	*/

/****************************************************************
 * Used for:	SB, SH, SW.					*
 ****************************************************************/
#define ST_NUMLINES	(TCID_NUMLINES+4*LI_NUMLINES+6)
#define MAX_ST_TCS	(MAX_INSTR_PER_FILE / ST_NUMLINES)
#define ChkSt(n,Op,rR,RoH,RoL,Imm,IAn,rA,rB,AH,AL,BH,BL,RH,RL,rT) \
	TestCaseID(n);			/* Load test number	*/\
	LI	(rT, RoH, RoL);		/* Load expected rR val	*/\
	bne	 rR, rT,  Fail;		/* Prelim check on rR	*/\
	nop	 ;			/* Fill delay slot	*/\
	LI	(rT, RH,  RL);		/* Load expected result	*/\
	LI	(rB, BH,  BL);		/* Load store address	*/\
	LI	(rA, AH,  AL);		/* Load store operand	*/\
	Op	 rA, Imm (rB);		/* Store it out		*/\
	lw	 rR, IAn (rB);		/* Read whole word in	*/\
	bne	 rR, rT,  Fail;		/* Check result		*/\
	nop				/* Fill delay slot	*/

/****************************************************************
 * Used for:	LBV, LSV, LLV, LDV, LQV, LRV, LPV, LUV, LHV, LFV*
 ****************************************************************/
#define VLD_NUMLINES	(TCID_NUMLINES+2*LI_NUMLINES+18)
#define MAX_VLD_TCS	(MAX_VECINST_PER_FILE / VLD_NUMLINES)
#define ChkVld(n,Op,rA,rB,rR,rT,vA,vT,AH,AL,BH,BL,Offs,El,VCC)	  \
	TestCaseID(n);			/* Load test number	*/\
	LI	(rB, BH, BL);		/* Load test base reg	*/\
	LI	(rA, AH, AL);		/* Load result base reg	*/\
	ori	 rT, r0, VCC;		/* Load exp'd VCC value	*/\
	vnxor	 vA, vA, vA;		/* Set vA to -1's	*/\
	nop	 ;			/* Fill delay slot	*/\
	nop	 ;			/* Fill delay slot	*/\
	nop	 ;			/* Fill delay slot	*/\
	Op	 vT[El], Offs (rB);	/* Perform test op	*/\
	lqv	 vA[0], 0 (rA);		/* Load expected result	*/\
	nop	 ;			/* Fill delay slot	*/\
	nop	 ;			/* Fill delay slot	*/\
	nop	 ;			/* Fill delay slot	*/\
	nop	 ;			/* Fill delay slot	*/\
	veq	 vA, vA, vT;		/* Check result		*/\
	nop	 ;			/* Fill delay slot	*/\
	cfc2	 rR, vcc;		/* Load VCC into rR	*/\
	nop	 ;			/* Fill delay slot	*/\
	bne	 rR, rT,  Fail;		/* If not all equal	*/\
	nop				/* Fill delay slot	*/
	
/****************************************************************
 * Used for:	SBV, SSV, SLV, SDV, SQV, SRV, SPV, SUV, SHV, SFV*
 *	NOTE:	For simplicity we assume LQV and LRV work	*
 *		correctly.					*
 ****************************************************************/
#define VST_NUMLINES	(TCID_NUMLINES+3*LI_NUMLINES+29)
#define MAX_VST_TCS	(MAX_VECINST_PER_FILE / VST_NUMLINES)
#define ChkVst(n,Op,rA,rB,rR,rT,vA,vB,vC,vT,AH,AL,BH,BL,RH,RL,Offs,El,VCC) \
	TestCaseID(n);			/* Load test number	*/\
	LI	(rA, AH, AL);		/* Pt to test mem data	*/\
	LI	(rB, BH, BL);		/* Real test address	*/\
	LI	(rR, RH, RL);		/* Real result address	*/\
	ori	 rT, r0, VCC;		/* Load exp'd VCC value	*/\
	vnxor	 vA, vA, vA;		/* Set vA to -1's	*/\
	lqv	 vT[0],   0   (rA);	/* Read in data		*/\
	lqv	 vB[0],  16   (rA);	/* Load expected result	*/\
	lqv	 vC[0],  32   (rA);	/* Load expected result	*/\
	nop	 ;			/* Fill delay slot	*/\
	Op	 vT[El], Offs (rB);	/* Perform test op	*/\
	nop	 ;			/* Fill delay slot	*/\
	lqv	 vA[0],   0   (rR);	/* Load actual result	*/\
	vne	 vC, vC, vC;		/* reset VCC		*/\
	nop	 ;			/* Fill delay slot	*/\
	nop	 ;			/* Fill delay slot	*/\
	veq	 vT, vA, vB;		/* Check result		*/\
	nop	 ;			/* Fill delay slot	*/\
	cfc2	 rA, vcc;		/* Load VCC into rR	*/\
	nop	 ;			/* Fill delay slot	*/\
	bne	 rA, rT,  Fail;		/* If not all equal	*/\
	nop	 ;			/* Fill delay slot	*/\
	lqv	 vA[0],  16   (rR);	/* Load actual result	*/\
	vne	 vB, vB, vB;		/* reset VCC		*/\
	nop	 ;			/* Fill delay slot	*/\
	nop	 ;			/* Fill delay slot	*/\
	veq	 vT, vA, vC;		/* Check result		*/\
	nop	 ;			/* Fill delay slot	*/\
	cfc2	 rB, vcc;		/* Load VCC into rR	*/\
	nop	 ;			/* Fill delay slot	*/\
	bne	 rB, rT,  Fail;		/* If not all equal	*/\
	nop				/* Fill delay slot	*/
	
#endif	/* _suregre_h_ */