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/************************************************************************
DMA BLOCK WRITE TESTS: File #2
************************************************************************/
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/****************************************************************
DMA TEST #2.25
****************************************************************/
ori $1, $0, 0x0019 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0808 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $13, 0x0500 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x2017
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0050 /* number of skips */
Prep25: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep25 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont25 /* exit loop if 0 span */
ori $3, $0, 0x0018 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep25 /* go look */
Cont25:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write25: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write25 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x1A68 /* load random number */
ori $9, $9, 0x6945
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x0014
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read25: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read25 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0050 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk25: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk25 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done25 /* exit if zero span */
ori $3, $0, 0x0018 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk25 /* go loop */
Done25:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln25: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln25 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #2.26
****************************************************************/
ori $1, $0, 0x001A /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0FE0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x0017
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep26: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep26 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont26 /* exit loop if 0 span */
ori $3, $0, 0x0018 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep26 /* go look */
Cont26:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write26: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write26 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x7C7E /* load random number */
ori $9, $9, 0x777C
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read26: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read26 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk26: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk26 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done26 /* exit if zero span */
ori $3, $0, 0x0018 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk26 /* go loop */
Done26:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln26: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln26 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #2.27
****************************************************************/
ori $1, $0, 0x001B /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0FE8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x3000
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x0017
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep27: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep27 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont27 /* exit loop if 0 span */
ori $3, $0, 0x0018 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep27 /* go look */
Cont27:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write27: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write27 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x58E2 /* load random number */
ori $9, $9, 0x4253
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read27: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read27 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk27: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk27 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done27 /* exit if zero span */
ori $3, $0, 0x0018 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk27 /* go loop */
Done27:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln27: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln27 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #2.28
****************************************************************/
ori $1, $0, 0x001C /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2780
lui $13, 0x0900 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x1077
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0090 /* number of skips */
Prep28: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep28 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont28 /* exit loop if 0 span */
ori $3, $0, 0x0078 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep28 /* go look */
Cont28:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write28: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write28 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x333F /* load random number */
ori $9, $9, 0x2B8C
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x0074
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read28: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read28 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0090 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk28: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk28 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done28 /* exit if zero span */
ori $3, $0, 0x0078 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk28 /* go loop */
Done28:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln28: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln28 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #2.29
****************************************************************/
ori $1, $0, 0x001D /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2788
lui $13, 0x1100 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x2077
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0110 /* number of skips */
Prep29: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep29 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont29 /* exit loop if 0 span */
ori $3, $0, 0x0078 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep29 /* go look */
Cont29:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write29: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write29 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x6FC5 /* load random number */
ori $9, $9, 0x4464
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x0074
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read29: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read29 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0110 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk29: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk29 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done29 /* exit if zero span */
ori $3, $0, 0x0078 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk29 /* go loop */
Done29:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln29: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln29 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #2.30
****************************************************************/
ori $1, $0, 0x001E /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0780 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2790
lui $13, 0x2100 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x1077
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0210 /* number of skips */
Prep30: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep30 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont30 /* exit loop if 0 span */
ori $3, $0, 0x0078 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep30 /* go look */
Cont30:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write30: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write30 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x369C /* load random number */
ori $9, $9, 0x1F73
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x0074
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read30: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read30 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0210 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk30: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk30 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done30 /* exit if zero span */
ori $3, $0, 0x0078 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk30 /* go loop */
Done30:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln30: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln30 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #2.31
****************************************************************/
ori $1, $0, 0x001F /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0788 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27E8
lui $13, 0x4100 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x2077
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0410 /* number of skips */
Prep31: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep31 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont31 /* exit loop if 0 span */
ori $3, $0, 0x0078 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep31 /* go look */
Cont31:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write31: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write31 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x026E /* load random number */
ori $9, $9, 0x5034
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x0074
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read31: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read31 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0410 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk31: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk31 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done31 /* exit if zero span */
ori $3, $0, 0x0078 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk31 /* go loop */
Done31:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln31: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln31 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #2.32
****************************************************************/
ori $1, $0, 0x0020 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0790 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F0
lui $13, 0x8100 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x1077
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0810 /* number of skips */
Prep32: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep32 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont32 /* exit loop if 0 span */
ori $3, $0, 0x0078 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep32 /* go look */
Cont32:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write32: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write32 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x7464 /* load random number */
ori $9, $9, 0x6D5F
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x0074
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read32: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read32 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0810 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk32: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk32 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done32 /* exit if zero span */
ori $3, $0, 0x0078 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk32 /* go loop */
Done32:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln32: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln32 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #2.33
****************************************************************/
ori $1, $0, 0x0021 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07E8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $13, 0x0600 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x2077
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0060 /* number of skips */
Prep33: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep33 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont33 /* exit loop if 0 span */
ori $3, $0, 0x0078 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep33 /* go look */
Cont33:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write33: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write33 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x78E7 /* load random number */
ori $9, $9, 0x6CD7
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x0074
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read33: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read33 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0060 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk33: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk33 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done33 /* exit if zero span */
ori $3, $0, 0x0078 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk33 /* go loop */
Done33:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln33: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln33 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #2.34
****************************************************************/
ori $1, $0, 0x0022 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $13, 0x0A00 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x1077
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x00A0 /* number of skips */
Prep34: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep34 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont34 /* exit loop if 0 span */
ori $3, $0, 0x0078 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep34 /* go look */
Cont34:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write34: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write34 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x071A /* load random number */
ori $9, $9, 0x67D2
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x0074
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read34: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read34 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x00A0 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk34: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk34 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done34 /* exit if zero span */
ori $3, $0, 0x0078 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk34 /* go loop */
Done34:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln34: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln34 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #2.35
****************************************************************/
ori $1, $0, 0x0023 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $13, 0x1200 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x2077
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0120 /* number of skips */
Prep35: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep35 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont35 /* exit loop if 0 span */
ori $3, $0, 0x0078 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep35 /* go look */
Cont35:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write35: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write35 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x01AD /* load random number */
ori $9, $9, 0x3398
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x0074
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read35: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read35 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0120 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk35: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk35 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done35 /* exit if zero span */
ori $3, $0, 0x0078 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk35 /* go loop */
Done35:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln35: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln35 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #2.36
****************************************************************/
ori $1, $0, 0x0024 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0800 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F80
lui $13, 0x2200 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x1077
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0220 /* number of skips */
Prep36: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep36 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont36 /* exit loop if 0 span */
ori $3, $0, 0x0078 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep36 /* go look */
Cont36:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write36: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write36 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x2AA6 /* load random number */
ori $9, $9, 0x2ED9
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x0074
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read36: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read36 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0220 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk36: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk36 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done36 /* exit if zero span */
ori $3, $0, 0x0078 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk36 /* go loop */
Done36:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln36: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln36 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
Wrap up ...
****************************************************************/
nop
Done: ori $1, $0, 0xFEED /* Test passed */
break
Time: ori $1, $0, 0xDEAD /* Timed-out from DMA */
break
Fail: break