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/************************************************************************
DMA BLOCK READ TESTS: File #0
************************************************************************/
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/****************************************************************
DMA TEST #0.1
****************************************************************/
ori $1, $0, 0x0001 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F0
lui $12, 0x0080 /* R12 = READ DMA LEN */
ori $12, $12, 0x1007
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read1: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read1 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0008 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0008 /* number of skips */
Chk1: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk1 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done1 /* exit if zero span */
ori $3, $0, 0x0008 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk1 /* go loop */
Done1:
/****************************************************************
DMA TEST #0.2
****************************************************************/
ori $1, $0, 0x0002 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x2007
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read2: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read2 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0008 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk2: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk2 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done2 /* exit if zero span */
ori $3, $0, 0x0008 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk2 /* go loop */
Done2:
/****************************************************************
DMA TEST #0.3
****************************************************************/
ori $1, $0, 0x0003 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0x0100 /* R12 = READ DMA LEN */
ori $12, $12, 0x1007
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read3: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read3 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0008 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0010 /* number of skips */
Chk3: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk3 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done3 /* exit if zero span */
ori $3, $0, 0x0008 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk3 /* go loop */
Done3:
/****************************************************************
DMA TEST #0.4
****************************************************************/
ori $1, $0, 0x0004 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $12, 0x0200 /* R12 = READ DMA LEN */
ori $12, $12, 0x2007
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read4: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read4 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0008 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0020 /* number of skips */
Chk4: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk4 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done4 /* exit if zero span */
ori $3, $0, 0x0008 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk4 /* go loop */
Done4:
/****************************************************************
DMA TEST #0.5
****************************************************************/
ori $1, $0, 0x0005 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0800 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $12, 0x0400 /* R12 = READ DMA LEN */
ori $12, $12, 0x1007
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read5: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read5 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0008 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0040 /* number of skips */
Chk5: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk5 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done5 /* exit if zero span */
ori $3, $0, 0x0008 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk5 /* go loop */
Done5:
/****************************************************************
DMA TEST #0.6
****************************************************************/
ori $1, $0, 0x0006 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0808 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $12, 0x0800 /* R12 = READ DMA LEN */
ori $12, $12, 0x2007
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read6: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read6 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0008 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0080 /* number of skips */
Chk6: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk6 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done6 /* exit if zero span */
ori $3, $0, 0x0008 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk6 /* go loop */
Done6:
/****************************************************************
DMA TEST #0.7
****************************************************************/
ori $1, $0, 0x0007 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0FF0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x3000
lui $12, 0x1000 /* R12 = READ DMA LEN */
ori $12, $12, 0x1007
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read7: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read7 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0008 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0100 /* number of skips */
Chk7: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk7 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done7 /* exit if zero span */
ori $3, $0, 0x0008 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk7 /* go loop */
Done7:
/****************************************************************
DMA TEST #0.8
****************************************************************/
ori $1, $0, 0x0008 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0FF8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x3008
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0007
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read8: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read8 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0008 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk8: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk8 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done8 /* exit if zero span */
ori $3, $0, 0x0008 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk8 /* go loop */
Done8:
/****************************************************************
DMA TEST #0.9
****************************************************************/
ori $1, $0, 0x0009 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27E8
lui $12, 0x2000 /* R12 = READ DMA LEN */
ori $12, $12, 0x100F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read9: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read9 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0200 /* number of skips */
Chk9: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk9 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done9 /* exit if zero span */
ori $3, $0, 0x0010 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk9 /* go loop */
Done9:
/****************************************************************
DMA TEST #0.10
****************************************************************/
ori $1, $0, 0x000A /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F0
lui $12, 0x4000 /* R12 = READ DMA LEN */
ori $12, $12, 0x200F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read10: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read10 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0400 /* number of skips */
Chk10: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk10 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done10 /* exit if zero span */
ori $3, $0, 0x0010 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk10 /* go loop */
Done10:
/****************************************************************
DMA TEST #0.11
****************************************************************/
ori $1, $0, 0x000B /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07E8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $12, 0x8000 /* R12 = READ DMA LEN */
ori $12, $12, 0x100F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read11: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read11 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0800 /* number of skips */
Chk11: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk11 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done11 /* exit if zero span */
ori $3, $0, 0x0010 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk11 /* go loop */
Done11:
/****************************************************************
DMA TEST #0.12
****************************************************************/
ori $1, $0, 0x000C /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0xC000 /* R12 = READ DMA LEN */
ori $12, $12, 0x200F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read12: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read12 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0C00 /* number of skips */
Chk12: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk12 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done12 /* exit if zero span */
ori $3, $0, 0x0010 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk12 /* go loop */
Done12:
/****************************************************************
DMA TEST #0.13
****************************************************************/
ori $1, $0, 0x000D /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $12, 0xA000 /* R12 = READ DMA LEN */
ori $12, $12, 0x100F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read13: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read13 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0A00 /* number of skips */
Chk13: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk13 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done13 /* exit if zero span */
ori $3, $0, 0x0010 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk13 /* go loop */
Done13:
/****************************************************************
DMA TEST #0.14
****************************************************************/
ori $1, $0, 0x000E /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0800 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FE8
lui $12, 0x0180 /* R12 = READ DMA LEN */
ori $12, $12, 0x200F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read14: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read14 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0018 /* number of skips */
Chk14: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk14 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done14 /* exit if zero span */
ori $3, $0, 0x0010 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk14 /* go loop */
Done14:
/****************************************************************
DMA TEST #0.15
****************************************************************/
ori $1, $0, 0x000F /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0808 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $12, 0x0280 /* R12 = READ DMA LEN */
ori $12, $12, 0x100F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read15: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read15 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0028 /* number of skips */
Chk15: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk15 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done15 /* exit if zero span */
ori $3, $0, 0x0010 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk15 /* go loop */
Done15:
/****************************************************************
DMA TEST #0.16
****************************************************************/
ori $1, $0, 0x0010 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0FE8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x000F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read16: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read16 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk16: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk16 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done16 /* exit if zero span */
ori $3, $0, 0x0010 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk16 /* go loop */
Done16:
/****************************************************************
DMA TEST #0.17
****************************************************************/
ori $1, $0, 0x0011 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0FF0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x3000
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x000F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read17: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read17 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk17: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk17 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done17 /* exit if zero span */
ori $3, $0, 0x0010 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk17 /* go loop */
Done17:
/****************************************************************
DMA TEST #0.18
****************************************************************/
ori $1, $0, 0x0012 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27E0
lui $12, 0x0480 /* R12 = READ DMA LEN */
ori $12, $12, 0x1017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read18: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read18 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0048 /* number of skips */
Chk18: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk18 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done18 /* exit if zero span */
ori $3, $0, 0x0018 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk18 /* go loop */
Done18:
/****************************************************************
DMA TEST #0.19
****************************************************************/
ori $1, $0, 0x0013 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27E8
lui $12, 0x0880 /* R12 = READ DMA LEN */
ori $12, $12, 0x2017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read19: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read19 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0088 /* number of skips */
Chk19: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk19 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done19 /* exit if zero span */
ori $3, $0, 0x0018 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk19 /* go loop */
Done19:
/****************************************************************
DMA TEST #0.20
****************************************************************/
ori $1, $0, 0x0014 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07E0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F0
lui $12, 0x1080 /* R12 = READ DMA LEN */
ori $12, $12, 0x1017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read20: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read20 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0108 /* number of skips */
Chk20: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk20 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done20 /* exit if zero span */
ori $3, $0, 0x0018 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk20 /* go loop */
Done20:
/****************************************************************
DMA TEST #0.21
****************************************************************/
ori $1, $0, 0x0015 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07E8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $12, 0x2080 /* R12 = READ DMA LEN */
ori $12, $12, 0x2017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read21: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read21 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0208 /* number of skips */
Chk21: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk21 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done21 /* exit if zero span */
ori $3, $0, 0x0018 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk21 /* go loop */
Done21:
/****************************************************************
DMA TEST #0.22
****************************************************************/
ori $1, $0, 0x0016 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0x4080 /* R12 = READ DMA LEN */
ori $12, $12, 0x1017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read22: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read22 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0408 /* number of skips */
Chk22: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk22 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done22 /* exit if zero span */
ori $3, $0, 0x0018 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk22 /* go loop */
Done22:
/****************************************************************
DMA TEST #0.23
****************************************************************/
ori $1, $0, 0x0017 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $12, 0x8080 /* R12 = READ DMA LEN */
ori $12, $12, 0x2017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read23: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read23 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0808 /* number of skips */
Chk23: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk23 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done23 /* exit if zero span */
ori $3, $0, 0x0018 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk23 /* go loop */
Done23:
/****************************************************************
DMA TEST #0.24
****************************************************************/
ori $1, $0, 0x0018 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0800 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FE8
lui $12, 0x0300 /* R12 = READ DMA LEN */
ori $12, $12, 0x1017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read24: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read24 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0030 /* number of skips */
Chk24: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk24 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done24 /* exit if zero span */
ori $3, $0, 0x0018 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk24 /* go loop */
Done24:
/****************************************************************
DMA TEST #0.25
****************************************************************/
ori $1, $0, 0x0019 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0808 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $12, 0x0500 /* R12 = READ DMA LEN */
ori $12, $12, 0x2017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read25: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read25 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0050 /* number of skips */
Chk25: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk25 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done25 /* exit if zero span */
ori $3, $0, 0x0018 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk25 /* go loop */
Done25:
/****************************************************************
DMA TEST #0.26
****************************************************************/
ori $1, $0, 0x001A /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0FE0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read26: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read26 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk26: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk26 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done26 /* exit if zero span */
ori $3, $0, 0x0018 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk26 /* go loop */
Done26:
/****************************************************************
DMA TEST #0.27
****************************************************************/
ori $1, $0, 0x001B /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0FE8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x3000
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0017
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read27: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read27 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk27: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk27 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done27 /* exit if zero span */
ori $3, $0, 0x0018 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk27 /* go loop */
Done27:
/****************************************************************
DMA TEST #0.28
****************************************************************/
ori $1, $0, 0x001C /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2780
lui $12, 0x0900 /* R12 = READ DMA LEN */
ori $12, $12, 0x1077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read28: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read28 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0090 /* number of skips */
Chk28: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk28 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done28 /* exit if zero span */
ori $3, $0, 0x0078 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk28 /* go loop */
Done28:
/****************************************************************
DMA TEST #0.29
****************************************************************/
ori $1, $0, 0x001D /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2788
lui $12, 0x1100 /* R12 = READ DMA LEN */
ori $12, $12, 0x2077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read29: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read29 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0110 /* number of skips */
Chk29: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk29 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done29 /* exit if zero span */
ori $3, $0, 0x0078 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk29 /* go loop */
Done29:
/****************************************************************
DMA TEST #0.30
****************************************************************/
ori $1, $0, 0x001E /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0780 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2790
lui $12, 0x2100 /* R12 = READ DMA LEN */
ori $12, $12, 0x1077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read30: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read30 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0210 /* number of skips */
Chk30: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk30 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done30 /* exit if zero span */
ori $3, $0, 0x0078 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk30 /* go loop */
Done30:
/****************************************************************
Wrap up ...
****************************************************************/
nop
Done: ori $1, $0, 0xFEED /* Test passed */
break
Time: ori $1, $0, 0xDEAD /* Timed-out from DMA */
break
Fail: break