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/************************************************************************
DMA BLOCK WRITE TESTS: File #3
************************************************************************/
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/****************************************************************
DMA TEST #3.37
****************************************************************/
ori $1, $0, 0x0025 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0808 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F88
lui $13, 0x4200 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x2077
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0420 /* number of skips */
Prep37: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep37 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont37 /* exit loop if 0 span */
ori $3, $0, 0x0078 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep37 /* go look */
Cont37:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write37: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write37 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x46A5 /* load random number */
ori $9, $9, 0x5474
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x0074
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read37: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read37 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0420 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk37: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk37 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done37 /* exit if zero span */
ori $3, $0, 0x0078 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk37 /* go loop */
Done37:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln37: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln37 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #3.38
****************************************************************/
ori $1, $0, 0x0026 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0F80 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F90
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x0077
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep38: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep38 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont38 /* exit loop if 0 span */
ori $3, $0, 0x0078 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep38 /* go look */
Cont38:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write38: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write38 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x0919 /* load random number */
ori $9, $9, 0x247C
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read38: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read38 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk38: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk38 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done38 /* exit if zero span */
ori $3, $0, 0x0078 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk38 /* go loop */
Done38:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln38: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln38 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #3.39
****************************************************************/
ori $1, $0, 0x0027 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0F88 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x0077
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep39: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep39 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont39 /* exit loop if 0 span */
ori $3, $0, 0x0078 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep39 /* go look */
Cont39:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write39: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write39 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x0B8E /* load random number */
ori $9, $9, 0x1F0C
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0074 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read39: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read39 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk39: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk39 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done39 /* exit if zero span */
ori $3, $0, 0x0078 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk39 /* go loop */
Done39:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln39: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln39 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #3.40
****************************************************************/
ori $1, $0, 0x0028 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2778
lui $13, 0x0080 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x107F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0008 /* number of skips */
Prep40: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep40 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont40 /* exit loop if 0 span */
ori $3, $0, 0x0080 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep40 /* go look */
Cont40:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write40: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write40 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x4B73 /* load random number */
ori $9, $9, 0x7D4B
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x007C
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read40: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read40 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0008 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk40: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk40 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done40 /* exit if zero span */
ori $3, $0, 0x0080 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk40 /* go loop */
Done40:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln40: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln40 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #3.41
****************************************************************/
ori $1, $0, 0x0029 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2780
lui $13, 0x0100 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x207F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0010 /* number of skips */
Prep41: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep41 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont41 /* exit loop if 0 span */
ori $3, $0, 0x0080 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep41 /* go look */
Cont41:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write41: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write41 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x7105 /* load random number */
ori $9, $9, 0x5FB6
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x007C
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read41: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read41 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0010 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk41: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk41 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done41 /* exit if zero span */
ori $3, $0, 0x0080 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk41 /* go loop */
Done41:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln41: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln41 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #3.42
****************************************************************/
ori $1, $0, 0x002A /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0778 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2788
lui $13, 0x0180 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x107F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0018 /* number of skips */
Prep42: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep42 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont42 /* exit loop if 0 span */
ori $3, $0, 0x0080 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep42 /* go look */
Cont42:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write42: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write42 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x7D3A /* load random number */
ori $9, $9, 0x2B69
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x007C
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read42: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read42 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0018 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk42: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk42 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done42 /* exit if zero span */
ori $3, $0, 0x0080 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk42 /* go loop */
Done42:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln42: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln42 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #3.43
****************************************************************/
ori $1, $0, 0x002B /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0780 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27E8
lui $13, 0x0200 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x207F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0020 /* number of skips */
Prep43: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep43 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont43 /* exit loop if 0 span */
ori $3, $0, 0x0080 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep43 /* go look */
Cont43:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write43: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write43 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x29D3 /* load random number */
ori $9, $9, 0x5DAB
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x007C
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read43: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read43 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0020 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk43: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk43 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done43 /* exit if zero span */
ori $3, $0, 0x0080 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk43 /* go loop */
Done43:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln43: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln43 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #3.44
****************************************************************/
ori $1, $0, 0x002C /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0788 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F0
lui $13, 0x0280 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x107F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0028 /* number of skips */
Prep44: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep44 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont44 /* exit loop if 0 span */
ori $3, $0, 0x0080 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep44 /* go look */
Cont44:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write44: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write44 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x3B1A /* load random number */
ori $9, $9, 0x6BE8
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x007C
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read44: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read44 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0028 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk44: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk44 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done44 /* exit if zero span */
ori $3, $0, 0x0080 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk44 /* go loop */
Done44:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln44: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln44 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #3.45
****************************************************************/
ori $1, $0, 0x002D /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07E8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $13, 0x0300 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x207F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0030 /* number of skips */
Prep45: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep45 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont45 /* exit loop if 0 span */
ori $3, $0, 0x0080 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep45 /* go look */
Cont45:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write45: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write45 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x7B71 /* load random number */
ori $9, $9, 0x2FE6
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x007C
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read45: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read45 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0030 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk45: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk45 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done45 /* exit if zero span */
ori $3, $0, 0x0080 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk45 /* go loop */
Done45:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln45: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln45 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #3.46
****************************************************************/
ori $1, $0, 0x002E /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $13, 0x0380 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x107F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0038 /* number of skips */
Prep46: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep46 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont46 /* exit loop if 0 span */
ori $3, $0, 0x0080 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep46 /* go look */
Cont46:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write46: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write46 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x1FBC /* load random number */
ori $9, $9, 0x3FD3
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x007C
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read46: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read46 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0038 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk46: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk46 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done46 /* exit if zero span */
ori $3, $0, 0x0080 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk46 /* go loop */
Done46:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln46: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln46 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #3.47
****************************************************************/
ori $1, $0, 0x002F /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $13, 0x0400 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x207F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0040 /* number of skips */
Prep47: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep47 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont47 /* exit loop if 0 span */
ori $3, $0, 0x0080 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep47 /* go look */
Cont47:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write47: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write47 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x1853 /* load random number */
ori $9, $9, 0x5781
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x007C
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read47: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read47 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0040 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk47: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk47 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done47 /* exit if zero span */
ori $3, $0, 0x0080 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk47 /* go loop */
Done47:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln47: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln47 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #3.48
****************************************************************/
ori $1, $0, 0x0030 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0800 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F78
lui $13, 0x0480 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x107F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0048 /* number of skips */
Prep48: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep48 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont48 /* exit loop if 0 span */
ori $3, $0, 0x0080 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep48 /* go look */
Cont48:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write48: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write48 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x04F5 /* load random number */
ori $9, $9, 0x13EA
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x007C
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read48: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read48 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0048 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk48: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk48 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done48 /* exit if zero span */
ori $3, $0, 0x0080 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk48 /* go loop */
Done48:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln48: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln48 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
Wrap up ...
****************************************************************/
nop
Done: ori $1, $0, 0xFEED /* Test passed */
break
Time: ori $1, $0, 0xDEAD /* Timed-out from DMA */
break
Fail: break