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/************************************************************************
DMA BLOCK WRITE TESTS: File #6
************************************************************************/
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.word 0x1DF816CC
.word 0x0883293E
.word 0x25946B2D
.word 0x5F9E7E9D
.word 0x26673D01
.word 0x1FE34317
.word 0x372654DD
.word 0x2F1C38F6
.word 0x61845697
.word 0x736C52CE
.word 0x371811C7
.word 0x601A4E59
.word 0x490C5E00
.word 0x03212113
.word 0x6E8B7ECE
.word 0x5F731295
.word 0x05E84B6F
.word 0x201120B2
.word 0x1C8F1652
.word 0x6FCC0953
.word 0x29AC1051
.word 0x01D81612
.word 0x479D23AD
.word 0x17160599
.word 0x181802CD
.word 0x0C1E2EB9
.word 0x3F1C66B6
.word 0x3C0E3949
.word 0x20993949
.word 0x441408C5
.word 0x4CDE2740
.word 0x73BD34A2
.word 0x47C655E7
.word 0x75FC2A72
.word 0x16A2389A
.word 0x7EFA55BC
.word 0x40E54202
.word 0x0AA16999
.word 0x2F926D0E
.word 0x77E6280F
.word 0x176659B3
/****************************************************************
DMA TEST #6.73
****************************************************************/
ori $1, $0, 0x0049 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x0807
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0808 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep73: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep73 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont73 /* exit loop if 0 span */
ori $3, $0, 0x0808 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep73 /* go look */
Cont73:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write73: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write73 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x0CD9 /* load random number */
ori $9, $9, 0x432D
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0804 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read73: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read73 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0808 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk73: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk73 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done73 /* exit if zero span */
ori $3, $0, 0x0808 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk73 /* go loop */
Done73:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln73: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln73 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #6.74
****************************************************************/
ori $1, $0, 0x004A /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x0807
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0808 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep74: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep74 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont74 /* exit loop if 0 span */
ori $3, $0, 0x0808 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep74 /* go look */
Cont74:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write74: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write74 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x59C5 /* load random number */
ori $9, $9, 0x7964
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0804 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read74: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read74 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0808 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk74: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk74 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done74 /* exit if zero span */
ori $3, $0, 0x0808 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk74 /* go loop */
Done74:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln74: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln74 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #6.75
****************************************************************/
ori $1, $0, 0x004B /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x0807
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0808 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep75: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep75 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont75 /* exit loop if 0 span */
ori $3, $0, 0x0808 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep75 /* go look */
Cont75:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write75: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write75 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x2F6D /* load random number */
ori $9, $9, 0x33EA
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0804 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read75: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read75 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0808 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk75: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk75 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done75 /* exit if zero span */
ori $3, $0, 0x0808 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk75 /* go loop */
Done75:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln75: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln75 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #6.76
****************************************************************/
ori $1, $0, 0x004C /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x080F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0810 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep76: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep76 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont76 /* exit loop if 0 span */
ori $3, $0, 0x0810 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep76 /* go look */
Cont76:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write76: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write76 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x0865 /* load random number */
ori $9, $9, 0x0750
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x080C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read76: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read76 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0810 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk76: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk76 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done76 /* exit if zero span */
ori $3, $0, 0x0810 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk76 /* go loop */
Done76:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln76: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln76 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #6.77
****************************************************************/
ori $1, $0, 0x004D /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x0FF7
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0FF8 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep77: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep77 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont77 /* exit loop if 0 span */
ori $3, $0, 0x0FF8 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep77 /* go look */
Cont77:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write77: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write77 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x5F08 /* load random number */
ori $9, $9, 0x22BE
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0FF4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read77: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read77 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0FF8 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk77: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk77 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done77 /* exit if zero span */
ori $3, $0, 0x0FF8 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk77 /* go loop */
Done77:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln77: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln77 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #6.78
****************************************************************/
ori $1, $0, 0x004E /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x0FF7
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0FF8 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep78: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep78 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont78 /* exit loop if 0 span */
ori $3, $0, 0x0FF8 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep78 /* go look */
Cont78:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write78: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write78 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x77BC /* load random number */
ori $9, $9, 0x485F
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0FF4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read78: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read78 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0FF8 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk78: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk78 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done78 /* exit if zero span */
ori $3, $0, 0x0FF8 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk78 /* go loop */
Done78:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln78: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln78 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #6.79
****************************************************************/
ori $1, $0, 0x004F /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x0FFF
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x1000 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep79: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep79 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont79 /* exit loop if 0 span */
ori $3, $0, 0x1000 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep79 /* go look */
Cont79:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write79: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write79 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x3AC9 /* load random number */
ori $9, $9, 0x3DFE
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0FFC /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read79: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read79 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x1000 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk79: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk79 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done79 /* exit if zero span */
ori $3, $0, 0x1000 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk79 /* go loop */
Done79:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln79: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln79 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
Wrap up ...
****************************************************************/
nop
Done: ori $1, $0, 0xFEED /* Test passed */
break
Time: ori $1, $0, 0xDEAD /* Timed-out from DMA */
break
Fail: break