dma.s
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/*
* Copy 71 bytes from DRAM location 0x00000000 to DMEM location 0x10000100.
*/
addi $1, $0, 0x100
mtc0 $1, $0
mtc0 $0, $1
addi $2, $0, 70
mtc0 $2, $2
/*
* Start second transfer: DMA registers are double buffered so two pending
* transfers can be outstanding.
*
* Copy 2 lines of 5 bytes with a skip count of 3 bytes
* from DRAM location 0x00000000 to DMEM location 0x10000200.
*/
addi $3, $0, 0x200
mtc0 $3, $0
mtc0 $0, $1
lui $4, 0x0030
addi $4, 0x1004
mtc0 $4, $2
/*
* Wait until first transfer completes, and then program the third transfer.
*/
wait1: mfc0 $5, $4
bne $5, $0, wait1
nop
/*
* Copy 7 bytes from DMEM location 0x10000000 to DRAM location 0x00000100
*/
mtc0 $0, $0
addi $2, $0, 0x100
mtc0 $2, $1
addi $3, $0, 0x6
mtc0 $3, $3
/*
* Wait until second transfer completes, and then program the fourth transfer.
*/
wait2: mfc0 $4, $4
bne $4, $0, wait2
nop
/*
* Copy 3 lines of 4 bytes with skip count of 2 bytes
* from DMEM location 0x10000000 to DRAM location 0x00000200
*/
mtc0 $0, $0
addi $2, $0, 0x200
mtc0 $2, $1
lui $3, 0x0020
addi $3, 0x2003
mtc0 $3, $3
/*
* Wait until all transfers are complete
*/
wait4: bc0t wait4
nop