#!/usr/sbin/perl

if ($ENV{"ROOT"}) {
   $ROOT = $ENV{"ROOT"};
  }
else {
  die "ROOT env not set. Plaase set ROOT environment first \n";
  }

$VUREGRES =  $ROOT."/PR/rspsim/vuregre";
$hw2 = 1;
$HW = "hw2";
$REGRESSION_DIR =$VUREGRES."/regression2";
$MAKE_REAL_MAKEFILE  = "make_reality_makefile2";
$REALITY_PATH = $ROOT."/PR/hw2/chip/sim";

if ($ENV{"USE_HW_ROOT"}) {
   $hw2 = 0;
   $HW = "hw";
   $REGRESSION_DIR =$VUREGRES."/regression";
   $MAKE_REAL_MAKEFILE  = "make_reality_makefile";
   $REALITY_PATH = $ROOT."/PR/hw/chip/sim";
  }

$SUREGRES =  $ROOT."/PR/rspsim/suregre";
$DMAREGRES =  $ROOT."/PR/rspsim/dmaregre";
$TOOL =   $VUREGRES."/bin";
$RSPASM = $ROOT."/PR/rspasm1201";
$RSPSIM = $ROOT."/PR/rspsim";


$VCSDIR = "/ecad/vcs/vcs_2.2/sgi";

$WORKDIR = `pwd`;
chop($WORKDIR);
$TESTDIR = $WORKDIR."/tests";
$TESTDIR_VU = $WORKDIR."/tests/VU";
$TESTDIR_SU = $WORKDIR."/tests/SU";
$TESTDIR_DMA = $WORKDIR."/tests/DMA";
$TESTDIR_VUCT = $WORKDIR."/tests/VU/ctrace";
$TESTDIR_SUCT = $WORKDIR."/tests/SU/ctrace";
$TESTDIR_DMACT = $WORKDIR."/tests/DMA/ctrace";
$DESIGNC = $WORKDIR."/designc"; 


$OPTION_ASM = 1;
$OPTION_ASM_ONLY = 0;
$OPTION_VCSCOMPILE = 1;
$OPTION_VCSRUN = 1;
$OPTION_BATCH = 1;
$OPTION_VU = 0;
$OPTION_SU = 0;
$OPTION_DMA = 0;
$OPTION_ALL = 1;
$OPTION_GATE = 0;
$OPTION_CTRACE = 0;
@PlusArgs = ();
$ALL_DIAGS = 1;
$TEST_SRC_FILE = "";

while ($#ARGV >= 0) {

    if ($ARGV[0] eq '-noasm') {
      shift (@ARGV);
      $OPTION_ASM = 0;
     }
    elsif ($ARGV[0] eq '-nocompile') {
      shift (@ARGV);
      $OPTION_VCSCOMPILE = 0;
      $OPTION_ASM = 0;
    }
    elsif ($ARGV[0] eq '-SU') {
      shift (@ARGV);
      $OPTION_SU = 1;
      $OPTION_ALL = 0;
    }
    elsif ($ARGV[0] eq '-VU') {
      shift (@ARGV);
      $OPTION_VU = 1;
      $OPTION_ALL = 0;
    }
    elsif ($ARGV[0] eq '-DMA') {
      shift (@ARGV);
      $OPTION_DMA = 1;
      $OPTION_ALL = 0;
    }
    elsif ($ARGV[0] eq '-asmonly') {
      shift (@ARGV);
      $OPTION_ASM_ONLY = 1;
    }
    elsif ($ARGV[0] eq '-norun') {
      shift (@ARGV);
      $OPTION_VCSRUN = 0;
    }
    elsif ($ARGV[0] eq '+single_step') {
      $PlusArgs = push(@PlusArgs,shift(@ARGV));
    }
    elsif ($ARGV[0] eq '+ctrace') {
      shift (@ARGV);
      $OPTION_CTRACE = 1;
    }
    elsif ($ARGV[0] eq '+MBUS') {
      $PlusArgs = push(@PlusArgs,shift(@ARGV));
    }
    elsif ($ARGV[0] eq '+dumpvars') {
      $PlusArgs = push(@PlusArgs,shift(@ARGV));
    }
    elsif ($ARGV[0] eq '+rsp_mon') {
      $PlusArgs = push(@PlusArgs,shift(@ARGV));
    }
    elsif ($ARGV[0] =~ /^\+reality=/) {
      ($TEMP,$plus_arg) = split(/=/,shift(@ARGV));
      $PlusArgs = push(@PlusArgs,"+".$plus_arg);
    }
    elsif ($ARGV[0] =~ /^\+diag=/) {
      ($TEMP,$DIAG) = split(/=/,shift(@ARGV));
      $PlusArgs = push(@PlusArgs,"+diag_".$DIAG);
      $ALL_DIAGS = 0;
    }
    elsif ($ARGV[0] =~ /^\-test_src=/) {
      ($TEMP,$TEST_SRC_FILE) = split(/=/,shift(@ARGV));
    }
    elsif ($ARGV[0] eq '-h') {
      shift (@ARGV);
      print "\n";
      print "\n";
      print "Usage: rsp_regression [options]\n";
      print "\n";
      print "\n";
      print "  options:\n";
      print "  -h           //Help \n";
      print "\n";
      print "  -SU       //This chooses SU tests \n";
      print "\n";
      print "  -VU       //This chooses VU tests \n";
      print "\n";
      print "  -DMA       //This chooses DMA tests. (SU,VU and ctrace) are inhibited. \n";
      print "\n";
      print "  -noasm       //This skips assembler on .s files \n";
      print "\n";
      print "  -nocompile   //This skips VCS compile of your design. Useful if you want to only \n";
      print "                 re-run the previously compiled design \n";
      print "\n";
      print "  -norun       //This does not execute simulation. Only compiles. \n";
      print "\n";
      print "  +dumpvars     //This causes the \$dumpvars to take effect. default is no dump. \n";
      print "                  CAUTION: verilog.dump can be very large file for big simulation. \n";
      print "\n";
      print "  +single_step  //The test runs in single step mode \n";
      print "\n";
      print "  +MBUS         //DMEM,IMEM initialized by CPU through single writes. Default is DMA loads from RDRAM.\n";
      print "\n";
      print "  +ctrace       //This enables the regi/mem traces to compare with verilog\n";
      print "\n";
      print "  +diag=<diag_name>  //This passes the diag_name as +arg to simulation and \n";
      print "                       simulate only with given diag. You can provide more then \n";
      print "                       one diag name as shown below. \n";
      print "                        +diag=<diag_1> +diag=<diag_2> .... +diag=<diag_3> \n";
      print "\n";
      print "                       If this option is not given, then default is all the \n";
      print "                       diags specified in testssuite. \n";
      print "\n";
      print "                       With this feature, you can compile once with all the \n";
      print "                       diags in testsuite and choose to only run the ones you want. \n";
      print "\n";
      exit; 
    }
    else {
    die "Illigal option provided \n";
    }

} #while ($#ARGV >= 0)

if ($OPTION_DMA==1) {
    $OPTION_SU = 0;
    $OPTION_VU = 0;
    $OPTION_ALL = 0;
    $OPTION_CTRACE = 0;
    }

if ($OPTION_CTRACE==1) {
    $PlusArgs = push(@PlusArgs,"+ctrace");
    }

if ($ALL_DIAGS==1) {
    $PlusArgs = push(@PlusArgs,"+AllDiags");
    }

if (!(-e $TESTDIR && -d $TESTDIR)) {
  print "Creating the $TESTDIR directory\n";
  mkdir ($TESTDIR,0777)    || die "Cant make $TESTDIR \n";
  }
if (!(-e $TESTDIR_VU && -d $TESTDIR_VU)) {
  print "Creating the $TESTDIR_VU directory\n";
  mkdir ($TESTDIR_VU,0777)    || die "Cant make $TESTDIR_VU \n";
  }
if (!(-e $TESTDIR_SU && -d $TESTDIR_SU)) {
  print "Creating the $TESTDIR_SU directory\n";
  mkdir ($TESTDIR_SU,0777)    || die "Cant make $TESTDIR_SU \n";
  }
if (!(-e $TESTDIR_DMA && -d $TESTDIR_DMA)) {
  print "Creating the $TESTDIR_DMA directory\n";
  mkdir ($TESTDIR_DMA,0777)    || die "Cant make $TESTDIR_DMA \n";
  }
if (!(-e $TESTDIR_VUCT && -d $TESTDIR_VUCT)) {
  print "Creating the $TESTDIR_VUCT directory\n";
  mkdir ($TESTDIR_VUCT,0777)    || die "Cant make $TESTDIR_VUCT \n";
  }
if (!(-e $TESTDIR_SUCT && -d $TESTDIR_SUCT)) {
  print "Creating the $TESTDIR_SUCT directory\n";
  mkdir ($TESTDIR_SUCT,0777)    || die "Cant make $TESTDIR_SUCT \n";
  }
if (!(-e $TESTDIR_DMACT && -d $TESTDIR_DMACT)) {
  print "Creating the $TESTDIR_DMACT directory\n";
  mkdir ($TESTDIR_DMACT,0777)    || die "Cant make $TESTDIR_DMACT \n";
  }

if (!(-e $DESIGNC && -d $DESIGNC)) {
  print "Creating the $DESIGNC directory\n";
  mkdir ($DESIGNC,0777) || die "Cant make $DESIGNC \n";
  } 

if (!(-r $REALITY_PATH."/Makefile")){
  die "$REALITY_PATH/Makefile not found. Please p_tupdate $REALITY_PATH \n";
  }
if (!(-r $REGRESSION_DIR."/rcpgate_rsp_ctrace.v")){
  die "rcpgate_rsp_ctrace.v not found. Please p_tupdate $VUREGRES \n";
  }
if (!(-r $REGRESSION_DIR."/rcpgate_rsp_regr_include.v")){
  die "rcpgate_rsp_regr_include.v not found. Please p_tupdate $VUREGRES \n";
  }

if (-r $REALITY_PATH."/Makefile"){
    print "Getting file $REALITY_PATH/Makefile \n";
    system("cat $REALITY_PATH/Makefile | $TOOL/$MAKE_REAL_MAKEFILE > $WORKDIR/Makefile")==0
     || die " System Call interrupt";
    chmod(0666,$WORKDIR."/Makefile");
   }
else {
  die "$REALITY_PATH/Makefile not found. Please p_tupdate $REALITY_PATH \n";
   }

if ($OPTION_ASM) {

   if ($TEST_SRC_FILE ne "") {
     print "Getting file $VUREGRES/regression/$TEST_SRC_FILE \n";
     system("touch $WORKDIR/testsuite; rm $WORKDIR/testsuite")==0 || die " System Call interrupt";
     if (-r $REGRESSION_DIR."/".$TEST_SRC_FILE){
        system("cp $REGRESSION_DIR/$TEST_SRC_FILE $WORKDIR/testsuite")==0
          || die " System Call interrupt";
        chmod(0666,$WORKDIR."/testsuite");
       }
    }
   elsif (!(-r "testsuite")){
      print "Getting file $REGRESSION_DIR/testsuite \n";
      system("cp $REGRESSION_DIR/testsuite $WORKDIR")==0
       || die " System Call interrupt";
      chmod(0666,$WORKDIR."/testsuite");
    }

  open(TESTSUITE,"testsuite") || die "Cant open testsuite \n";
  open(TESTSKIPPED,">tests.skipped") || die "Cant open tests.skipped \n";

  $test_num=0;
  $DMA_ONETIME = 0;

  while ($_= <TESTSUITE>) {

     split;

     $INTYPE = 0; $STYPE = 0;
     $VUTEST = 0; $SUTEST = 0; $DMATEST = 0;

     $TEST_TYPE = $_[0]; #VU,SU,DMA
     $TEST =      $_[1]; #test

     if (($TEST_TYPE eq "VU"  && ($OPTION_ALL | $OPTION_VU)) || 
         ($TEST_TYPE eq "SU"  && ($OPTION_ALL | $OPTION_SU)) || 
         ($TEST_TYPE eq "DMA" && ($OPTION_DMA)) 
        ) {

        if ($TEST_TYPE eq "VU") {
	   $VUTEST = 1;
   	   $TESTNAME_FULL = $ROOT."/".$TEST;
	   $TESTDIR = $TESTDIR_VU;
           open(MAKEFILE,">$TESTDIR/Makefile") || die "Cant open $TESTDIR/Makefile \n";
         }
	elsif ($TEST_TYPE eq "SU") { 
	   $SUTEST = 1; 
	   $TESTNAME_FULL = $ROOT."/".$TEST;
	   $TESTDIR = $TESTDIR_SU;
           open(MAKEFILE,">$TESTDIR/Makefile") || die "Cant open $TESTDIR/Makefile \n";
           chmod(0666,$TESTDIR."/suregre.h");
	  }
	else {
	   $DMATEST = 1; 
	   $TESTNAME_FULL = $ROOT."/".$TEST;
	   $TESTDIR = $TESTDIR_DMA;
           open(MAKEFILE,">$TESTDIR/Makefile") || die "Cant open $TESTDIR/Makefile \n";
           chmod(0666,$TESTDIR."/suregre.h");
	   if ($DMA_ONETIME==0) {
	     $DMA_ONETIME = 1;
	     chdir ($TESTDIR) || die "Cant go to $TESTDIR \n";
             system("cp $DMAREGRES/ready/rdram_*.dat .;chmod +w rdram_*.dat;".
                    "cp $DMAREGRES/ready/rdram_*.bin .;chmod +w rdram_*.bin;".
                    "cp $DMAREGRES/ready/rdram_reordered_0.data .;".
                    "chmod +w rdram_reordered_0.data")==0 || die "System Interrupt";
	     chdir ($WORKDIR) || die "Cant go to $WORKDIR \n";
             system("cat $REALITY_PATH/Makefile | $TOOL/$MAKE_REAL_MAKEFILE -LARGE_TIMEOUT > $WORKDIR/Makefile")==0
              || die " System Call interrupt";
             chmod(0666,$WORKDIR."/Makefile");
	   }
	  }

	$TEST = `basename $TESTNAME_FULL`;
	chop($TEST);

	print "test is $TEST \n";
	
	($TEST,$FILE_TYPE) = split(/\./,$TEST);

        if ($FILE_TYPE eq "in") { 
	   $INTYPE = 1; 
          }
	else { 
	   $STYPE = 1; 
	  }

	if (-r $TESTNAME_FULL) {

	    chdir ($TESTDIR) || die "Cant go to $TESTDIR \n";
            
	    print MAKEFILE "\n";
	    print MAKEFILE "TARGET1 = $TEST.$FILE_TYPE\n";
	    print MAKEFILE "TARGET2 = $TEST.rdram_IMEM\n";
	    print MAKEFILE "TOOL = $TOOL/lst2IMEM $TOOL/dat2rdram $RSPASM/rspasm $TOOL/d2asm ".
		           "$TOOL/trace2ver $TOOL/make_rtsk $RSPSIM/rsp $TOOL/reorder ".
			   "$TOOL/make_dma_rtsk \n";
	    print MAKEFILE "INCLUDE = VU_AVP.h suregre.h\n";
	    print MAKEFILE "\n";
	    print MAKEFILE "\$(TARGET2): $TEST.$FILE_TYPE \$(TOOL) \$(INCLUDE)\n";
	    print MAKEFILE "\ttouch a.out\n";
	    print MAKEFILE "\trm a.out*\n";
	    if ($FILE_TYPE eq "in") {
	           print MAKEFILE "\t$TOOL/d2asm $TEST.in $TEST.s $TEST.inlst\n";
		  }
	    print MAKEFILE "\t$RSPASM/rspasm -b 0 $TEST.s\n";
	    print MAKEFILE "\tmv a.out $TEST.out\n";
	    print MAKEFILE "\tmv a.out.lst $TEST.lst\n";
	    print MAKEFILE "\tmv a.out.dat $TEST.dat\n";
	    if ($TEST_TYPE eq "SU") {
	          print MAKEFILE "\t$TOOL/make_rtsk $TEST 1 1\n";
		}
            elsif ($TEST_TYPE eq "VU") {
	          print MAKEFILE "\t$TOOL/make_rtsk $TEST 31 1\n";
		}
	    else  {
	          print MAKEFILE "\t$TOOL/make_dma_rtsk $TEST 1 1\n";
		}
	    print MAKEFILE "\t$RSPSIM/rsp -ntz $TEST.rtsk</dev/null> $TEST.simlog \n";
	    print MAKEFILE "\t$TOOL/cvtdmem $TEST.eoe_dmem | $TOOL/dat2rdram 1 > $TEST.eoe_DMEM;\n";
	    print MAKEFILE "\tmv trace_out ctrace/$TEST.ctrace\n";
	    print MAKEFILE "\t$TOOL/cvtdmem $TEST.dat | $TOOL/dat2rdram > rdram.DMEM;\n";
	    print MAKEFILE "\t(cd ctrace; $TOOL/trace2ver $TEST)\n";
	    print MAKEFILE "\t$TOOL/lst2IMEM $TEST.lst > rdram.IMEM\n";
	    print MAKEFILE "\t$TOOL/reorder;\n";
	    print MAKEFILE "\tmv dmem_reordered.data $TEST.rdram_DMEM; \n";
	    print MAKEFILE "\tmv imem_reordered.data $TEST.rdram_IMEM; \n";
	    print MAKEFILE "\n";
	    print MAKEFILE "\$(TARGET1): $TESTNAME_FULL\n";
	    print MAKEFILE "\tcp $TESTNAME_FULL $TEST.$FILE_TYPE\n";
	    print MAKEFILE "\tchmod +w $TEST.$FILE_TYPE\n";
	    print MAKEFILE "\n";
	    print MAKEFILE "\suregre.h: $SUREGRES/csrc/suregre.h \n";
	    print MAKEFILE "\tcp $SUREGRES/csrc/suregre.h suregre.h\n";
	    print MAKEFILE "\tchmod +w suregre.h\n";
	    print MAKEFILE "\n";
	    print MAKEFILE "\VU_AVP.h: $VUREGRES/src/include/VU_AVP.h \n";
	    print MAKEFILE "\tcp $VUREGRES/src/include/VU_AVP.h VU_AVP.h\n";
	    print MAKEFILE "\tchmod +w VU_AVP.h\n";
	    close(MAKEFILE);
		
            if (system("make")==0) {
	       $ARRY0[$test_num] = $TEST_TYPE;
	       $ARRY1[$test_num] = $FILE_TYPE;
	       $ARRY2[$test_num] = $TEST;
	       $test_num++;
	       }
	    else {
	       print "\n\n****ERROR:asm steps: test skipped\n\n";
	       print TESTSKIPPED "$_ skipped due to Error\n";
               system("touch $TESTDIR/$TEST.rdram_IMEM")==0 || die "System Interrupt";
               system("rm $TESTDIR/$TEST.rdram_IMEM")==0 || die "System Interrupt";
	       }
	 } #if (-r $TESTNAME_FULL)

	chdir ($WORKDIR) || die "Cant go to parent \n";


      }
  } #while

close(TESTSKIPPED);
if (-z $WORKDIR."/tests.skipped") {
   system("rm $WORKDIR/tests.skipped")==0 || die "System Interrupt";
   }    

  if ($test_num==0) {
   die "NO TESTS found in testsuite \n";
   }

  if ($OPTION_ASM_ONLY==1) {
   print "DONE compiling tests \n";
   exit;
   }
  open(OUT,">rsp_tests.v") || die "Cant open rsp_tests.v";
  open(TLIST,">rsp_tests.list") || die "Cant open rsp_tests.list";
  
  $TEMP = "rcpgate_rsp_regr_include.v";
  
  print OUT "\n";
  print OUT "`timescale 1ns / 10ps \n";
  print OUT "\n";
  print OUT "module rsp_tests;\n";
  print OUT "\n";
  print OUT "\n";
  print OUT "`include  \"$TEMP\""; 
  print OUT "\n";
  print OUT "\n";

  for ($i=0; $i<$test_num; $i++) {
     $TEST      = $ARRY2[$i];
     print OUT "reg diag_$TEST;\n";

     print TLIST "$TEST\n";
    }
  print OUT "initial\n";
  print OUT "    begin\n";
  for ($i=0; $i<$test_num; $i++) {
     $TEST      = $ARRY2[$i];
     print OUT "       diag_$TEST=0;\n";
     print OUT "       if (\$test\$plusargs(\"diag_$TEST\"))\n";
     print OUT "           diag_$TEST=1;\n";
     print OUT "\n";
   }
  print OUT "    end\n";
  print OUT "\n";

  print OUT "initial \n";
  print OUT "begin \n";
  print OUT "\n";
  print OUT "\n";
  print OUT "\$fwrite(fp,\"\\n\\n\");\n";
  print OUT "#16 \n";
  print OUT "reality.r4200b_0.test_selected = 1;\n";
  print OUT "wait(`SYSTEM_READY);\n";
  print OUT "repeat (4) @(posedge `CLK);\n";
  print OUT "reality.r4200b_0.config_rdram;\n";

  print OUT "\n";
  print OUT "\n";
  
  for ($i=0; $i<$test_num; $i++) {
     $TEST_TYPE = $ARRY0[$i];
     $FILE_TYPE = $ARRY1[$i];
     $TEST      = $ARRY2[$i];
     if ($TEST_TYPE eq "VU") {
       $TESTDIR = "tests/VU";
       $test_code = "2'b00";
       }
     elsif ($TEST_TYPE eq "SU"){
       $TESTDIR = "tests/SU";
       $test_code = "2'b01";
       }
     else {
       $TESTDIR = "tests/DMA";
       $test_code = "2'b11";
       }
      
     $j = $i+1;
     print OUT "\n";
     print OUT "/*********************************************\n";
     print OUT " * (Test# $j)  Test Name: $TEST \n";
     print OUT " *********************************************/\n";
     print OUT "\n";
     print OUT "if (diag_$TEST || AllDiags) \n";
     print OUT "begin \n";
     print OUT "   \$display(\$time,\" TEST $TEST starts\"); \n";
     if ($TEST_TYPE eq "DMA") {
        print OUT "   \$readmemh(\"$TESTDIR/rdram_reordered_0.data\",`rdram_0.core.core); \n";
       }
     print OUT "   \$readmemh(\"$TESTDIR/$TEST.rdram_IMEM\",`rdram_0.core.core); \n";
     print OUT "   \$readmemh(\"$TESTDIR/$TEST.rdram_DMEM\",`rdram_0.core.core); \n";
     if ($TEST_TYPE eq "SU" || $TEST_TYPE eq "VU") {
        print OUT "   \$readmemh(\"$TESTDIR/$TEST.eoe_DMEM\",`rdram_0.core.core); \n";
        }
     print OUT "   if (ctrace) \n";
     print OUT "   begin \n";
     print OUT "     \$readmemh(\"$TESTDIR/ctrace/$TEST.trSU\",`tr.su_mem); \n";
     print OUT "     \$readmemh(\"$TESTDIR/ctrace/$TEST.trVU\",`tr.vu_mem); \n";
     print OUT "     \$readmemh(\"$TESTDIR/ctrace/$TEST.trDM\",`tr.dm_mem); \n";
     print OUT "   end \n";
     print OUT "   rundiag($test_code,\"$TEST.$FILE_TYPE\, 'hfff, 'hfff, 'b10");\n";
     print OUT "   \$display(\$time,\"TEST $TEST ends\"); \n";
     print OUT "end\n";
  }
  print OUT "\n";
  print OUT "\n";
  print OUT "test_report; \n";
  print OUT "\$finish; \n";
  print OUT "\n";
  print OUT "end \n";
  print OUT "\n";
  print OUT "endmodule \n";
  
  close(TESTSUITE);
  close(OUT);

} #if ($OPTION_ASM)  

if ($OPTION_VCSCOMPILE) {
  print "\n\nVCS Compile in progress\n\n";
  chdir ("$WORKDIR");

  if ($OPTION_DMA) {
    if (-r "designc/rcpgate_rsp_simv_dma"){
      system("rm designc/rcpgate_rsp_simv_dma")==0 || die "System Interrupt";
      }
    chdir ("$WORKDIR");
    system("make rcpgate_rsp_simv")==0 || die "VCS compile system call interupt";
    system("mv rcpgate_rsp_simv designc/rcpgate_rsp_simv_dma")==0 || die "System Interrupt";
    }
  else {
    if (-r "designc/rcpgate_rsp_simv"){
      system("rm designc/rcpgate_rsp_simv")==0 || die "System Interrupt";
      }
    chdir ("$WORKDIR");
    system("make rcpgate_rsp_simv")==0 || die "VCS compile system call interupt";
    system("mv rcpgate_rsp_simv designc/rcpgate_rsp_simv")==0 || die "System Interrupt";
    }
}

$HW_TYPE = "on HW2";
if ($hw2==0) {
  $HW_TYPE = "on HW";
  }

if ($OPTION_VCSRUN) {
  chdir ("$WORKDIR");
    print "\n\n Running (RCPGATE_LEVEL RSP REGRESSION, $HW_TYPE) Simulation \n\n";
    print "plusargs passed to vcs are: @PlusArgs \n";

    print "\nRunning Gate level version \n";
    if ($OPTION_DMA) {
      system("/bin/csh -c 'setenv LD_LIBRARY_PATH $VCSDIR/lib; ".
      "time designc/rcpgate_rsp_simv_dma -q @PlusArgs ' > ,out")==0
               || die("Interrupt occured, cannot run regression");
      }
    else {
      system("/bin/csh -c 'setenv LD_LIBRARY_PATH $VCSDIR/lib; ".
      "time designc/rcpgate_rsp_simv -q @PlusArgs ' > ,out")==0
               || die("Interrupt occured, cannot run regression");
      }

    print "SImulation Complete\n";
}