delta.c
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/*
* Copyright (C) 1998 by the Board of Trustees
* of Leland Stanford Junior University.
* Copyright (C) 1998 Digital Equipment Corporation
*
* This file is part of the SimOS distribution.
* See LICENSE file for terms of the license.
*
*/
/* ******************************************************
* delta.c
* ******************************************************/
#include <stdio.h>
#include <malloc.h>
#include <setjmp.h>
#include <alpha/inst.h>
#include <sys/signal.h>
#include "simtypes.h"
#include "sim_error.h"
#include "tcl_init.h"
#include "machine_params.h"
#include "arch_specifics.h"
#include "params.h"
#include "annotations.h"
#include "gdb_interface.h"
#include "tc.h"
#include "tc_coherence.h"
#include "userflush.h"
#include "alpha.h"
#include "ev5.h"
#include "ev5_ipr.h"
#include "alpha_gdb.h"
#include "gamma.h"
#include "stats.h"
#include "qc.h"
#include "tb.h"
#include "delta.h"
#include "translator.h"
#include "emit.h"
void **constantsPtr;
void **currentConstant;
union alpha_instruction illegalInstr;
struct DeltaState delta;
#define DELTA_NUM_CACHES 1
static int deltaSigfpeUseLongjmp = 0;
static void DeltaEvents(void);
static void DeltaCPUVectorInit(void);
static char *DeltaStats(void);
extern jmp_buf jmpEnv;
static void DeltaDoneRunning(void)
{
CPUWarning("Exiting the Delta simulator \n");
AnnExec(AnnFind("simos", "exit"));
}
/* ******************************************************
* main entry point
* ******************************************************/
void ExecuteDelta(void)
{
AlphaState *dummy = (AlphaState *) malloc(sizeof(AlphaState));
bzero((char*)dummy,sizeof(AlphaState));
/*
* ssetup original arguments
*/
GammaInitTables();
GammaCPUVectorInit(); /* default functions */
DeltaCPUVectorInit(); /* override some of them */
if (!alphaLateInitDone) {
/*
* Stuff that needs late initalization.
* XXX should use a register mechanism
*/
AnnCommonSetup();
AnnFMInit(128);
InstallPoller(); /* devices */
alphaLateInitDone = 1;
}
/*
* simos enter annotation
*/
{
int cpu;
for (cpu=0;cpu<TOTAL_CPUS;cpu++) {
curPE = PE[cpu];
AnnExec(AnnFind("simos","enter"));
}
curPE = PE[0];
}
/*
* Configure DELTA
*/
delta.useDQC = 1;
delta.useIQC = 1;
delta.chainKnownBranches = 1;
delta.chainBranches = 1;
delta.chainSpec = 1;
delta.inlineIQC = 1;
delta.inlineDQC = 1;
delta.registerAllocate = 1;
delta.mergeBranches = 1;
delta.saveRegOpt = 1;
delta.bypassICheck = 1;
/*
* Initalize the translation cache
*/
{
int size[1] = {4*1024*1024}; /* THIS IS THE MAX 'cause branches */
int pcSize[1] = {1024 * 128};
int annSize[1] = {16*1024};
illegalInstr.word = 0;
illegalInstr.common.opcode = 0; /* callpal */;
illegalInstr.word |= 0x3d; /* retsys, privileged opcode */
usercacheinit();
TC_init(DELTA_NUM_CACHES,size,pcSize,annSize,illegalInstr.word);
TCcoherence_init(alphaMemoryPtr);
}
/*
* link PE 0 and the dummy. Other PE are still in the PROM
* loop.
*/
PE[0]->cpuState = cpu_running;
PE[0]->timeQuantum = delta.timeQuantum;
PE[0]->cycleCountDown = delta.timeQuantum;
PE[0]->cycleCount = 0;
PE[0]->nextCPU = dummy;
dummy->nextCPU = PE[0];
dummy->myNum = -1;
ASSERT(delta.timeQuantum > 0);
CPUWarning("DELTA: P->PC entry = 0x%lx \n",PE[0]->PC);
DeltaClearTranslationCache(TCFLUSH_ALL,DELTAFLUSH_INIT);
{
void * (*f)() = GetEmitFunction(0,CALLOUT_INITSP);
delta.stackPtr = f();
}
curPE = dummy;
InitSimulatorStats(32*1024*1024, DeltaStats);
DeltaFPInit(); /* installs SIGFPE handler */
delta.debugCycle = 28491190;
delta.debugCycle = 0;
{
int toCPUType = NO_CPU;
if ((toCPUType = setjmp(jmpEnv)) != 0) {
DeltaDoneRunning();
simosCPUType = toCPUType;
} else {
if (getenv("DELTA_SIGFPE_USE_LONGJMP") != NULL)
deltaSigfpeUseLongjmp = atoi(getenv("DELTA_SIGFPE_USE_LONGJMP"));
DeltaRun();
}
}
}
#if 1
#define DELTA_CHECK(_x)
#else
#define DELTA_CHECK(_x) DeltaCheck(_x)
#endif
TCA checkTCA;
void DeltaCheck(char *string)
{
SimTime time = CPUVec.CycleCount(0);
if (time >= 19327695) {
CPUPrint("XXX DELTA_CHECK at %lld PC=0x%lx tca=%lx %s \n",
(uint64)time,curPE->PC,checkTCA,string);
}
}
/* **********************************************************
* NextTCA: find the next TCA at all cost,
* possibly raising an ITLB exception, calling
* the translator or even flusing the TC
* **********************************************************/
static inline TCA NextTCA(void)
{
AlphaState *P = curPE;
PA pAddr=0;
MA mAddr, checkMA;
MMUStatus status=MMU_SUCCESS;
ASSERT(P->myNum>=0);
checkMA = QCLookup(P->curIQC,P->PC,0);
if ( delta.useIQC) {
mAddr = checkMA;
pAddr = MEMADDR_TO_PHYS(M_FROM_CPU(P->myNum),mAddr);
} else {
mAddr = 0;
}
if (!mAddr) {
status = EV5_ITranslateVirtual(P,&pAddr, 1);
mAddr = PHYS_TO_MEMADDR(M_FROM_CPU(P->myNum),pAddr);
ASSERT( !checkMA || checkMA==mAddr);
}
if (status==MMU_SUCCESS) {
int tcCache = 0;
TCA tca = TC_PCLookup(tcCache,P->PC,mAddr);
if (!tca) {
int flushCount = tcGenNumber;
/* QCAnalCheck(P,P->curDQC,TB_DATA); */
tca = Translate(P->myNum,P->PC,pAddr,mAddr,P->curIQC);
if (flushCount !=tcGenNumber) return 0;
}
return tca;
} else {
ASSERT(!checkMA);
ASSERT(status==MMU_EXCEPTION);
return 0;
}
}
/* ********************************************************
* DeltaRun: main loop
* ********************************************************/
static void DeltaEnterTC(TCA tca)
{
AlphaState *P = curPE;
checkTCA = tca;
DELTA_CHECK("EnterTC");
ASSERT(!IS_PAL(P));
if (delta.debugCycle &&
delta.debugCycle < CPUVec.CycleCount(0)) {
CPUPrint("%ld Entering TC for PC=0x%lx tca=0x%lx\n",
CPUVec.CycleCount(curPE->myNum),curPE->PC,tca);
}
delta.EnterTC(P,tca,delta.stackPtr,constantsPtr);
NOTREACHED();
}
static jmp_buf deltaJmpEnv;
void DeltaRun()
{
if (deltaSigfpeUseLongjmp)
setjmp(deltaJmpEnv);
while(1) {
if (curPE->myNum<0) {
DeltaEvents();
ASSERT( curPE->myNum>=0);
} else if (IS_PAL(curPE)){
if (delta.debugCycle && delta.debugCycle < CPUVec.CycleCount(0)) {
CPUPrint("%ld Entering DeltaGammaPalCode for PC=0x%lx\n",
CPUVec.CycleCount(curPE->myNum),
curPE->PC);
}
DeltaGammaRun(curPE);
if (curPE->cycleCountDown < 0) {
curPE = curPE->nextCPU;
}
} else {
TCA tca = NextTCA();
if (tca) {
DeltaEnterTC(tca);
/* notreached */
NOTREACHED();
} else {
/*
* either we got an exception, of
* the TC got flushed. In any case, we
* continue with the same processor
*/
}
}
}
}
static void DeltaEvents(void)
{
AlphaState *t=curPE->nextCPU;
SimTime max = 0;
ASSERT(curPE->myNum==-1);
while (t !=curPE) {
SimTime time = t->cycleCount +t->timeQuantum - t->cycleCountDown;
while( t->cycleCountDown < 0) {
t->cycleCountDown += t->timeQuantum;
t->cycleCount += t->timeQuantum;
}
if (time > max) max = time;
t = t->nextCPU;
}
curPE = curPE->nextCPU;
ASSERT(curPE->myNum == 0);
EventProcess(-1,max);
}
void CalloutEvents(void)
{
ASSERT(curPE->myNum==-1);
DeltaEvents();
DeltaRun();
NOTREACHED();
}
/*
* Chaining for branches
*/
TCA CalloutChain(TCA chainAddr, VA prevPC)
{
TCA tca;
ASSERT (curPE->myNum>=0);
ASSERT(!IS_PAL(curPE));
tca= NextTCA();
if (delta.debugCycle &&
CPUVec.CycleCount(0) > delta.debugCycle ) {
CPUPrint("%ld CalloutChain pc=0x%lx ra=0x%lx tca=0x%lx \n",
CPUVec.CycleCount(curPE->myNum),curPE->PC,curPE->reg[REG_RA],tca);
}
if (tca) {
return PatchBranch(prevPC,curPE->PC,chainAddr,tca);
} else {
DeltaRun();
/* notreached */
NOTREACHED();
return 0;
}
}
/*
* Chaining for register indirect calls
*/
TCA CalloutChainSpeculative(TCA chainAddr)
{
TCA tca;
ASSERT(curPE->myNum >=0);
ASSERT(!IS_PAL(curPE));
tca= NextTCA();
if (delta.debugCycle &&
CPUVec.CycleCount(0) > delta.debugCycle ) {
CPUPrint("%ld CalloutChain pc=0x%lx ra=0x%lx tca=0x%lx \n",
CPUVec.CycleCount(curPE->myNum),curPE->PC,curPE->reg[REG_RA],tca);
}
if (tca) {
if (chainAddr) {
return PatchSpeculative(chainAddr,tca);
} else {
return tca;
}
} else {
DeltaRun();
/* notreached */
NOTREACHED();
return 0;
}
}
TCA CalloutChainCtxt(void)
{
TCA tca;
if (curPE->myNum < 0) {
CalloutEvents();
NOTREACHED();
}
if (IS_PAL(curPE)) {
DeltaRun();
NOTREACHED();
}
tca= NextTCA();
if (delta.debugCycle &&
CPUVec.CycleCount(0) > delta.debugCycle ) {
CPUPrint("%ld CalloutChain pc=0x%lx ra=0x%lx tca=0x%lx \n",
CPUVec.CycleCount(curPE->myNum),curPE->PC,curPE->reg[REG_RA],tca);
}
if (tca) {
return tca;
} else {
DeltaRun();
/* notreached */
NOTREACHED();
return 0;
}
}
/*
* Be very careful of side-effects on prePC and postPC
* annotations. e.g. don't perform register preloading on
* those basic blocks.
* Also should make sure that the annotation only
* fires once if we reenter the TC
*/
void CalloutPostPCAnn(void)
{
VA pc = curPE->PC;
int x = delta.sideEffectPC;
int y = delta.sideEffectMem;
AnnPtr aptr = AnnFMLookup(curPE->PC,ANNFM_PC_TYPE);
ASSERT(aptr);
DELTA_CHECK("PostPCAnn");
ASSERT(CPUVec.CycleCount(0)!= 28198929);
AnnExec(aptr);
ASSERT( x==delta.sideEffectPC);
if (y!=delta.sideEffectMem) {
/*
* if this is a problem, we should go into
* some kind of emulation mode to figure out the
* next PC.
* Could also have this done by passing the next PC
* as an argument, computed in the TC
*/
CPUWarning("TC flushed on Post-PC annotation. BAD \n");
}
ASSERT( y==delta.sideEffectMem);
ASSERT( pc==curPE->PC) ;
return;
}
void CalloutPrePCAnn(void)
{
int x = delta.sideEffectPC;
int y = delta.sideEffectMem;
AnnPtr aptr = AnnFMLookup(curPE->PC,ANNFM_PRE_PC_TYPE);
ASSERT(aptr);
DELTA_CHECK("PrePCAnn");
AnnExec(aptr);
if (x!= delta.sideEffectPC ||
y!= delta.sideEffectMem) {
DeltaRun();
NOTREACHED();
}
return;
}
void CalloutNever(TCA tca)
{
CPUError("Reached CalloutNever at tca=0x%lx PC=0x%lx \n",
tca,curPE->PC);
}
void CalloutCallPal(union alpha_instruction instr)
{
DeltaGammaRun(curPE);
DeltaRun();
NOTREACHED();
}
void CalloutMisc(void)
{
DeltaGammaRun(curPE);
DeltaRun();
NOTREACHED();
}
void CalloutFEN(void)
{
EV5_Trap(curPE,TRAP_FEN);
DeltaGammaRun(curPE);
DeltaRun();
NOTREACHED();
}
void CalloutITB(void)
{
MA mAddr=0;
PA pAddr=0;
MMUStatus status;
AlphaState *P = curPE;
DELTA_CHECK("ITB");
/*
* should be moved to assembly
*/
if (!delta.inlineIQC) {
mAddr = QCLookup(P->curIQC,P->PC,0);
ASSERT( mAddr == delta.QCLookupRead(P->curIQC,P->PC));
if (mAddr && delta.useIQC) return;
} else {
#if 0
mAddr = QCLookup(P->curIQC,P->PC,0);
ASSERT(!mAddr);
#endif
}
status = EV5_ITranslateVirtual(P,&pAddr, 1);
if (status==MMU_SUCCESS) {
ASSERT(!mAddr || (mAddr=PHYS_TO_MEMADDR(0,pAddr)));
return;
} else {
ASSERT(!mAddr);
ASSERT( status==MMU_EXCEPTION);
DeltaRun();
}
NOTREACHED();
}
/*
* XXX this is real slow, but the
* XXX P->instr is needed in case of a
* XXX trap
*/
MA CalloutDTBLoad(VA vAddr)
{
AlphaState *P = curPE;
PA pAddr=0;
MA mAddr;
MA qcMA=0;
MMUStatus status;
DELTA_CHECK("DTBLoad");
/* ASSERT( CPUVec.CycleCount(0)!=19450462); */
#ifdef DEBUG_DELTA_MMSTAT
status = EV5_ITranslateVirtual(P,&pAddr,1);
ASSERT( status==MMU_SUCCESS);
mAddr = PHYS_TO_MEMADDR(M_FROM_CPU(P->myNum),pAddr);
P->instr = *(TCA) mAddr;
#endif
if (!delta.inlineDQC) {
qcMA = QCLookup(P->curDQC,vAddr,0);
ASSERT( qcMA == delta.QCLookupRead(P->curDQC,vAddr));
if (qcMA && delta.useDQC) {
return qcMA;
}
} else {
#if 0
qcMA =QCLookup(P->curDQC,vAddr,0);
ASSERT(!qcMA);
#endif
}
status = EV5_DTranslateVirtual(P,vAddr,0,1,&pAddr);
if (status==MMU_SUCCESS) {
mAddr = PHYS_TO_MEMADDR(M_FROM_CPU(P->myNum),pAddr);
ASSERT(!qcMA || (qcMA==mAddr));
return mAddr;
} else if (status==MMU_EXCEPTION) {
ASSERT(!qcMA);
DeltaRun();
NOTREACHED();
return 0;
} else {
ASSERT(!qcMA);
ASSERT( status==MMU_UNCACHED);
DeltaGammaRun(P);
DeltaRun();
NOTREACHED();
return 0;
}
}
MA CalloutDTBStore(VA vAddr)
{
AlphaState *P = curPE;
PA pAddr=0;
MMUStatus status;
MA mAddr;
MA qcMA=0;
DELTA_CHECK("DTBStore");
#ifdef DEBUG_DELTA_MMSTAT
status = EV5_ITranslateVirtual(P,&pAddr,1);
ASSERT( status==MMU_SUCCESS);
mAddr = PHYS_TO_MEMADDR(M_FROM_CPU(P->myNum),pAddr);
P->instr = *(TCA) mAddr;
#endif
if (!delta.inlineDQC) {
qcMA = QCLookup(P->curDQC,vAddr,1);
ASSERT( qcMA == delta.QCLookupWrite(P->curDQC,vAddr));
if (qcMA && delta.useDQC) {
return qcMA;
}
} else {
#if 0
qcMA = QCLookup(P->curDQC,vAddr,1);
ASSERT(!qcMA);
#endif
}
status = EV5_DTranslateVirtual(P,vAddr,1,1,&pAddr);
if (status==MMU_SUCCESS) {
mAddr = PHYS_TO_MEMADDR(M_FROM_CPU(P->myNum),pAddr);
ASSERT( !qcMA || (qcMA==mAddr));
if (TCcoherence_is_code(mAddr)) {
DeltaGammaRun(P); /* required for forward progress */
DeltaClearTranslationCache(TCFLUSH_ALL,DELTAFLUSH_COHERENCE);
DeltaRun();
NOTREACHED();
return 0;
} else {
return mAddr;
}
} else if (status==MMU_EXCEPTION) {
ASSERT( !qcMA);
DeltaRun();
NOTREACHED();
return 0;
} else {
ASSERT(!qcMA);
ASSERT( status==MMU_UNCACHED);
DeltaGammaRun(P);
DeltaRun();
NOTREACHED();
return 0;
}
}
/* ********************************************************
* CPUVector functions. The gamma functions are installed
* by default, but some of them need to be overridden
* ********************************************************/
SimTime
DeltaCycleCount(int cpuNum)
{
AlphaState *P = PE[cpuNum];
if (!P) {
return 0;
} else {
return P->cycleCount + P->timeQuantum - P->cycleCountDown;
}
}
/*
* This algorithm incidentally also works for
* GAMMA, in case we eliminate P->instr
*/
Inst DeltaCurrentInstruction(int cpuNum)
{
Inst inst;
AlphaState *P = PE[cpuNum];
VA oldPC = P->PC;
MA mAddr = QCLookup(P->curIQC,P->PC,0);
ASSERT(P->myNum==cpuNum && cpuNum>=0);
/* QCConsistencyCheck(P,P->curIQC,TB_INSTR); */
if (!mAddr) {
PA pAddr =0;
MMUStatus status;
if (!IS_PAL(P)) {
CPUWarning("DeltaCurrentInstruction oldPC=%lx \n",oldPC);
ASSERT(0);
}
status = EV5_ITranslateVirtual(P,&pAddr,0);
ASSERT( status==MMU_SUCCESS);
mAddr = PHYS_TO_MEMADDR(M_FROM_CPU(P->myNum),pAddr);
}
inst = *(Inst*) mAddr;
#ifdef DEBUG_DELTA_MMSTAT
ASSERT( inst == P->instr.word); /* debug */
CPUWarning("DEBUG_DELTA_MMSTAT clear \n");
#endif
return inst;
}
Result DeltaPutReg(int cpu, int regnum, Reg val)
{
Result res = GammaPutReg(cpu,regnum,val);
if (regnum == PC_REGNUM) {
delta.sideEffectPC++;
}
return res;
}
Result DeltaPutMem(int cpuNum, VA vAddr, uint nbytes, char *buf)
{
int i;
PA pA=0;
if (0)
CPUWarning("Put mem size %d addr 0x%lx buf 0x%x \n",nbytes,vAddr,*(uint32*)buf);
for (i=0;i<nbytes;i++) {
if (EV5_DTranslateVirtual(PE[cpuNum],vAddr+i,0,0,&pA)==MMU_SUCCESS) {
MA mAddr = PHYS_TO_MEMADDR(M_FROM_CPU(cpuNum),pA);
*(char*)mAddr = buf[i];
if (TCcoherence_is_code(mAddr)) {
DeltaClearTranslationCache(TCFLUSH_ALL,DELTAFLUSH_PUTMEM);
delta.sideEffectMem++;
}
} else {
return FAILURE;
}
}
return SUCCESS;
}
void DeltaDebug( int cpuNum , int sigUsr)
{
if (cpuNum < 0 ) {
ASSERT( curPE->myNum >=0);
Simdebug_run(SIGUSR2, curPE->myNum);
} else {
Simdebug_run(SIGUSR2, cpuNum);
}
return;
}
void DeltaDMAInval(int machine, PA *list)
{
int cpuNum;
PA *paPtr;
for (paPtr = list; *paPtr; paPtr++) {
ASSERT (*paPtr < MEM_SIZE(0));
if (TCcoherence_check(PHYS_TO_MEMADDR(machine,*paPtr),
PHYS_TO_MEMADDR(machine,*paPtr+PAGE_SIZE))) {
CPUWarning("DeltaDMAInval: conflict for pAddr=0x%lx \n",
*paPtr);
DeltaClearTranslationCache(TCFLUSH_ALL,DELTAFLUSH_DMAINVAL);
}
}
}
/* **************************************************
* DeltaLaunchSlaveCPU
* NEVE RETURNS
*/
void DeltaLaunchSlaveCPU(int cpu)
{
int i;
CPUWarning("DELTA launch slave cpu %d \n",cpu);
PE[cpu]->cpuState = cpu_running;
PE[cpu]->timeQuantum = PE[0]->timeQuantum;
PE[cpu]->cycleCountDown = PE[0]->cycleCountDown;
PE[cpu]->cycleCount = PE[0]->cycleCount;
for(i=cpu-1;i>=0;i--) {
if (PE[i]->cpuState == cpu_running) {
PE[cpu]->nextCPU = PE[i]->nextCPU;
PE[i]->nextCPU = PE[cpu];
return;
}
}
ASSERT(0);
}
static void DeltaCPUVectorInit(void)
{
CPUVec.CycleCount = DeltaCycleCount;
CPUVec.InstrCount = DeltaCycleCount;
CPUVec.CurrentInstruction = DeltaCurrentInstruction;
CPUVec.PutRegister = DeltaPutReg;
CPUVec.PutMemory = DeltaPutMem;
CPUVec.Handle_Debug_Signal = DeltaDebug;
CPUVec.DMAInval = DeltaDMAInval;
CPUVec.LaunchSlaveCPU = DeltaLaunchSlaveCPU;
}
/* *******************************************************
* DeltaParameters
* *******************************************************/
void DeltaTclInit(Tcl_Interp *interp)
{
ParamRegister("PARAM(CPU.Delta.TimeQuantum)", (char *)&delta.timeQuantum, PARAM_INT);
}
void DeltaClearTranslationCache(int code, DeltaFlushCause cause)
{
char *reason;
switch (cause) {
case DELTAFLUSH_INIT:
reason = " Init";
break;
case DELTAFLUSH_COHERENCE:
reason = "TCcoherence violation";
break;
case DELTAFLUSH_TC:
reason = "TC overflow";
break;
case DELTAFLUSH_CONSTANTS:
reason = "Constants overflow\n";
break;
case DELTAFLUSH_DMAINVAL:
reason = "DMA conflict";
break;
case DELTAFLUSH_PUTMEM:
reason = "PutMem conflict";
break;
default: NOTREACHED(); reason = "none";
}
if (cause!=DELTAFLUSH_COHERENCE) {
CPUWarning("DeltaClearTranslationCache of cache=%d for %s \n",
code,reason);
} else {
delta.stats.coherenceFlushes++;
}
if (code==TCFLUSH_ALL || DELTA_NUM_CACHES==1) {
TCcoherence_flush();
DeltaInitConstants();
}
TC_flush(code);
if (code==TCFLUSH_ALL) {
int i;
for (i=0;i<DELTA_NUM_CACHES;i++) {
EmitFunctions(i);
}
} else {
EmitFunctions(code);
}
delta.EnterTC = ( void (*)()) GetEmitFunction(0,CALLOUT_ENTERTC);
delta.QCLookupRead = ( MA (*)()) GetEmitFunction(0,CALLOUT_QCLOOKUP_READ);
delta.QCLookupWrite = ( MA (*)()) GetEmitFunction(0,CALLOUT_QCLOOKUP_WRITE);
}
/* ***************************************************************
* Constants management
* ***************************************************************/
void DeltaInitConstants(void)
{
if (!constantsPtr) {
constantsPtr = malloc(MAX_CONSTANTS*sizeof(void *));
}
bzero((char*)constantsPtr,MAX_CONSTANTS*sizeof(void *));
constantsPtr[CALLOUT_CALLPAL] = CalloutCallPal;
constantsPtr[CALLOUT_ITB] = CalloutITB;
constantsPtr[CALLOUT_DTB_LOAD] = CalloutDTBLoad;
constantsPtr[CALLOUT_DTB_STORE] = CalloutDTBStore;
constantsPtr[CALLOUT_MISC] = CalloutMisc;
constantsPtr[CALLOUT_FEN] = CalloutFEN;
constantsPtr[CALLOUT_CHAIN] = CalloutChain;
constantsPtr[CALLOUT_CHAIN_SPEC]= CalloutChainSpeculative;
constantsPtr[CALLOUT_CHAIN_CTXT]= CalloutChainCtxt;
constantsPtr[CALLOUT_POSTPC_ANN]= CalloutPostPCAnn;
constantsPtr[CALLOUT_PREPC_ANN] = CalloutPrePCAnn;
constantsPtr[CALLOUT_NEVER] = CalloutNever;
/* .... other constants follow */
currentConstant = constantsPtr+MAX_CALLOUTS;
}
int DeltaAllocateConstant(void *value)
{
int64 offset;
*currentConstant = value;
offset = (char*)currentConstant - (char*)constantsPtr;
currentConstant++;
ASSERT (offset < MAX_CONSTANTS*sizeof(void *));
return (int)offset;
}
int DeltaRemainingConstants()
{
return MAX_CONSTANTS - (currentConstant - constantsPtr);
}
char *DeltaStats()
{
static char buf[256];
sprintf(buf,"TCcoh %5d ",delta.stats.coherenceFlushes);
delta.stats.coherenceFlushes = 0;
return buf;
}
/*
* signal
*/
void DeltaFPInit()
{
struct sigaction action;
struct sigaction oaction;
static void DeltaSIGFPEHandler(int signal, siginfo_t *psiginfo, void *pcontext);
action.sa_handler = (void(*)(int))DeltaSIGFPEHandler;
action.sa_mask = 0;
action.sa_flags = SA_SIGINFO;
sigaction(SIGFPE, &action, &oaction);
}
void DeltaSIGFPEHandler(int signal, siginfo_t *psiginfo, struct sigcontext *ctxt)
{
long code = psiginfo->si_code;
Reg fpcr = gammaReadFPCR();
Reg ofpcr = 0;
Reg pc = (curPE != NULL ? curPE->PC : -1L);
int instr = (curPE != NULL ? DeltaCurrentInstruction(curPE->myNum) : 0);
if (curPE != NULL) {
ofpcr = curPE->fpcr;
}
CPUWarning("@@@@ DeltaSIGFPEHandler: pc=%lx instr=%x ofpcr=%lx actual fpcr=%lx code=%lx\n",
pc, instr, ofpcr, fpcr, code);
/*
* XXX should check that this is indeed a AXPTYPE_CANTRAP instruction
* XXX with its trap barrier
*/
curPE->PC = ctxt->sc_regs[DELTAREG_CALLOUT_PC];
/* set FPCR and raise the EV5_Trap */
EV5_Trap(curPE, TRAP_ARITH);
if (deltaSigfpeUseLongjmp) {
longjmp(deltaJmpEnv, 0);
} else {
/* reinstall the handler */
DeltaFPInit();
/* call DeltaRun -- @@@@ grows the stack? */
DeltaRun();
}
NOTREACHED();
}