/*
 * Copyright (C) 1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * Copyright (C) 1998 Digital Equipment Corporation
 *
 * This file is part of the SimOS distribution.
 * See LICENSE file for terms of the license.
 *
 */



#include <malloc.h>
#include <strings.h>

/* from common */
#include "simtypes.h"
#include "sim_error.h"
#include "tc.h"
#include "tc_coherence.h"
#include "arch_specifics.h"

/* cpus-alpha/alpha_shared */
#include "alpha.h"
#include "alpha_regs.h"
#include "qc.c"
#include "userflush.h"

/* gamma */
#include "gamma.h"

/* delta */
#include "assym.h"
#include "emit.h"
#include "delta.h"
#include "decoder.h"
#include "translator.h"

 
#define INST_SIZE sizeof(union alpha_instruction)

#define LOAD_PV_OFFSET 4

/* ***************************************************************
 * Configuration
 * ***************************************************************/


typedef int HRegIdx; /* Host/Hardware register */
typedef int SRegIdx; /* Simulated register */

static struct {
   QCTable *iQC;
   HRegIdx *allTempRegs;
   int nextFree;
   int fpFree;
   union alpha_instruction *memptr;
   int endsWithBranch;
   int tcCache;
   int printBB;
   TCA startSpeculative;
   int regAlloc;
   int fpChecked;
}  conf;


static BasicBlock bb;
static HRegIdx shadowRegs[] = DELTA_SHADOW_REGS;
static HRegIdx tempRegs[]   = {REG_T7,REG_T8,REG_T9,REG_T10,REG_T11,REG_ZERO};
static HRegIdx *allRegs;
static uint callerSavedMask=0;

   


static void TranslatorStart(int tcCache) {
   if (!allRegs) { 
      int i,base=0;
      allRegs = (HRegIdx*) malloc(32*sizeof(HRegIdx));
      bzero((char*)allRegs,32*sizeof(HRegIdx));
      for(i=1; shadowRegs[i] != REG_ZERO;i++) {
	 allRegs[base++] = shadowRegs[i];
         callerSavedMask |= (1<<shadowRegs[i]);
      }
      for(i=0;tempRegs[i]!=REG_ZERO;i++) {
	 allRegs[base++] = tempRegs[i];
      }
      allRegs[base] = REG_ZERO;
   }

   conf.nextFree = 0;
   conf.fpFree = 0;
   conf.endsWithBranch = 0;
   conf.tcCache = tcCache;
   conf.printBB = 0;
   conf.fpChecked = 0;
}




/* *********************************************************
 * Code generation macros
 * *********************************************************/

#if 0
#define EMIT_U(_instrWord) {ASSERT(conf.memptr->word==illegalInstr.word); \
                             (conf.memptr++)->word = _instrWord;} 

#define EMIT_INSTR(_instr) { ASSERT(conf.memptr->word==illegalInstr.word); \
                             *conf.memptr++ = _instr;} 
#endif

#define EMIT_U(_instrWord) { (conf.memptr++)->word = _instrWord;} 
#define EMIT_INSTR(_instr) {  *conf.memptr++ = _instr;} 


#define PATCH_INSTR(_ptr,_newInstr) { *_ptr = _newInstr;}



/* **********************************************************
 * Load/StoreRegister. 
 * For now, no register allocation (preload)
 * Save always.
 * **********************************************************/



static void PreloadRegs(void) 
{
   conf.regAlloc = delta.registerAllocate && (!bb.hasPCAnn) && (!bb.hasSC);
   if (conf.regAlloc) { 
      int i;
      for (i=1;i<bb.regAlloc.numRegsAlloc;i++) {
         int idx = bb.regAlloc.preload[i];
         ASSERT( bb.regAlloc.reg[idx] ==i);
         
         EMIT_LOAD(shadowRegs[i],DELTAREG_BASE,REG_OFF+idx*sizeof(Reg));
      }
      conf.allTempRegs = tempRegs;
   } else {
      conf.allTempRegs = allRegs;
   }
}

static inline HRegIdx LoadRegister(SRegIdx idx)
{
   HRegIdx loc;
   if (idx==REG_ZERO) return REG_ZERO;
   
   if (conf.regAlloc && bb.regAlloc.reg[idx]) {  
      return shadowRegs[(int)bb.regAlloc.reg[idx]];
   }
  
   if (conf.regAlloc && bb.regAlloc.numRegsAlloc < NUM_SHADOW_REGS) { 
      bb.regAlloc.reg[idx] = bb.regAlloc.numRegsAlloc++;
      loc = shadowRegs[(int)bb.regAlloc.reg[idx]];
   } else { 
      loc = conf.allTempRegs[conf.nextFree++];
   }
   
   ASSERT(loc!=REG_ZERO);
   EMIT_LOAD(loc,DELTAREG_BASE,REG_OFF+idx*sizeof(Reg));
   return loc;
}

static inline  HRegIdx TargetRegister(SRegIdx idx) 
{
  HRegIdx loc;
  if (idx==REG_ZERO) { 
     return REG_ZERO;
  } 
  if (conf.regAlloc && bb.regAlloc.reg[idx]) {
     return shadowRegs[(int)bb.regAlloc.reg[idx]];
  } 
  if (conf.regAlloc && bb.regAlloc.numRegsAlloc< NUM_SHADOW_REGS) {
     bb.regAlloc.reg[idx] = bb.regAlloc.numRegsAlloc++;
     loc = shadowRegs[(int)bb.regAlloc.reg[idx]];
  } else {
     loc = conf.allTempRegs[conf.nextFree++];
  }
  ASSERT(loc!=REG_ZERO);
  return loc;
}


static inline HRegIdx TempRegister(void) 
{
   HRegIdx loc;
   loc = conf.allTempRegs[conf.nextFree++];
   ASSERT(loc!=REG_ZERO);
   return loc;
}

static inline void StoreRegister(HRegIdx hwR ,SRegIdx simR, uint saveReg)
{
   ASSERT(simR != REG_ZERO);
   if (saveReg&SAVE_REG_OPT) {
      if ( (1<<hwR)&callerSavedMask) {
#if 0
         EMIT_NOP(); /* debug */
#endif
         return;
      }
   }
   EMIT_STORE(hwR,DELTAREG_BASE,REG_OFF+simR*sizeof(Reg));  
}




   
HRegIdx LoadFPRegister(SRegIdx idx, int flags)
{
   register union alpha_instruction t; 
   HRegIdx loc = conf.fpFree++;
   ASSERT(loc!=REG_ZERO);
   t.common.opcode = op_ldt;
   t.m_format.ra = loc;  
   t.m_format.rb = DELTAREG_BASE;  
   t.m_format.memory_displacement = FPREG_OFF+idx*sizeof(Reg);  
   EMIT_INSTR(t); 
   return loc;
}


HRegIdx TargetFPRegister(SRegIdx idx) 
{
   if (idx==REG_ZERO) { 
      return REG_ZERO;
   } else { 
      HRegIdx loc = conf.fpFree++;
      return loc;
   }
}
HRegIdx TempFPRegister(void) 
{
   HRegIdx loc = conf.fpFree++;
   ASSERT(loc!=REG_ZERO);
   return loc;
}

void StoreFPRegister(HRegIdx hwR ,SRegIdx simR, int flags)
{
   register union alpha_instruction t; 
   ASSERT(simR != REG_ZERO);
   t.common.opcode = op_stt; 
   t.m_format.ra = hwR;  
   t.m_format.rb = DELTAREG_BASE;  
   t.m_format.memory_displacement = FPREG_OFF+simR*sizeof(Reg);  
   EMIT_INSTR(t); 
      
}

HRegIdx LoadFPCRRegister(void)
{
   register union alpha_instruction t;
   HRegIdx loc = conf.fpFree++;
   ASSERT(loc!=REG_ZERO);
   t.common.opcode = op_ldt;
   t.m_format.ra = loc;
   t.m_format.rb = DELTAREG_BASE;
   t.m_format.memory_displacement = FPCR_OFF;
   EMIT_INSTR(t);

   t.common.opcode = op_fltl;
   t.f_format.function = fltl_mt_fpcr;
   t.f_format.fa = loc;
   t.f_format.fb = loc;
   t.f_format.fc = loc;
   EMIT_INSTR(t);
   return loc;
}
 
void StoreFPCRRegister(HRegIdx hwR) 
{
   register union alpha_instruction t;


   t.common.opcode = op_fltl;
   t.f_format.function = fltl_mf_fpcr;
   t.f_format.fa = hwR;
   t.f_format.fb = hwR;
   t.f_format.fc = hwR;
   EMIT_INSTR(t);
   t.common.opcode = op_stt;
   t.m_format.ra = hwR;
   t.m_format.rb = DELTAREG_BASE;
   t.m_format.memory_displacement = FPCR_OFF;
   EMIT_INSTR(t);  
}





/* **************************************************************
 * General Callout Mechanism
 * **************************************************************/
#define LENGTH_EMIT_CALLOUT (6+LENGTH_EMIT_RELOAD)

void Callout(BasicBlockInstr *i, int callout)
{
   HRegIdx pc = TempRegister();
   HRegIdx cc = TempRegister();
   union alpha_instruction inst;
   TCA savedTCA = conf.memptr;

   ASSERT (callout>=0 && callout < MAX_CALLOUTS);

   EMIT_LOAD(REG_PV,DELTAREG_CONSTANTS,callout*sizeof(Reg));

   EMIT_LDA(pc,DELTAREG_PC,i->offset);
   EMIT_STORE(pc,DELTAREG_BASE,PC_OFF);
   EMIT_ADDI(DELTAREG_COUNTDOWN,bb.numCycles-i->cycles,cc);
   EMIT_STORE(cc,DELTAREG_BASE,COUNTDOWN_OFF);
   
   inst.common.opcode = op_jsr;
   inst.j_format.ra = REG_RA;
   inst.j_format.rb = REG_PV;
   inst.j_format.function = jsr_jsr; /* XXX bogus XXX */
   EMIT_INSTR(inst);
   EMIT_RELOAD();
   ASSERT( savedTCA + LENGTH_EMIT_CALLOUT == conf.memptr);
}


/* ***********************************************************
 * EmitBranchToCode
 * XXX These callouts must be within direct reach!!!
 * ***********************************************************/

static void inline EmitBranchToCode(int branch_opcode,HRegIdx ra,int callout)
{
   void *target = GetEmitFunction(conf.tcCache, callout);
   union alpha_instruction inst;  
   int64 diff;

   diff = ((int64)target - (int64)conf.memptr) /(int)INST_SIZE;
   diff = diff-1;
  
   ASSERT(target);
   ASSERT( diff > (-1*(1<<20)) && diff < (1<<20));
     
   inst.common.opcode = branch_opcode;
   inst.b_format.ra = ra;
   inst.b_format.branch_displacement = diff;
   EMIT_INSTR(inst);

}

   
static inline void EmitAdd(HRegIdx src, int64 diff , HRegIdx dst)
{
   if (diff >= -32768 && diff < 32768) { 
      EMIT_LDA(dst,src,diff);
      return;
   }
   {
      /*
       * emit lDA_H, LDA sequence. 
       * Careful to add one if low is negative
       */

      int64 hi = diff >>16;
      int64 lo = diff & BITMASK(16);
      if (lo & (1<<15)) {
	 hi++;
      }
      if (hi >= -32768 && hi < 32768) { 
	 EMIT_M(op_ldah,dst,src,hi);
	 EMIT_M(op_lda,dst,dst,lo);
	 return;
      }
   }
	 
   { 
      /*
       * slow and uses constants, but uncommon. leave it for now
       */
      HRegIdx tmp = TempRegister();
      int constant = DeltaAllocateConstant((void*)diff);
      EMIT_LOAD(tmp,DELTAREG_CONSTANTS,constant);
      EMIT_OP(op_inta,inta_addq,src,tmp,dst);
   }
}

static inline void  EmitReference(BasicBlockInstr *i,int  callout)
{
   union alpha_instruction orig = i->instr;
   HRegIdx reg = LoadRegister(orig.m_format.rb);

   /*
    * compute effective address into REG_A0
    * Saved updated PC and updated CCD into P
    */

   EMIT_LDA(DELTAREG_CALLOUT_PC,DELTAREG_PC,i->offset);
   EMIT_LDA(DELTAREG_CALLOUT_CCD,DELTAREG_COUNTDOWN,bb.numCycles-i->cycles);
   EMIT_LDA(REG_A0,reg,orig.m_format.memory_displacement);
   
   EmitBranchToCode(op_bsr,REG_RA,callout );
}


void CheckFPEnabled(BasicBlockInstr *i)
{
   ASSERT(bb.usesFP);
   if (conf.fpChecked) return;
   conf.fpChecked  = 1;
   EMIT_LDA(DELTAREG_CALLOUT_PC,DELTAREG_PC,i->offset);
   EMIT_LDA(DELTAREG_CALLOUT_CCD,DELTAREG_COUNTDOWN,bb.numCycles-i->cycles);
   EmitBranchToCode(op_bsr,REG_RA,CALLOUT_FEN );

}


#define BYPASS_SPECULATION 3
#define BYPASS_ICHECK      1


static void Prelude(BasicBlock *bb)
{
   VA vPC = bb->vPC;
     
   HRegIdx checkPC = tempRegs[0];
   
   /*
    * check PC (speculative only) (bypass possible)
    * If you branch to CALLOUT_CHAIN, this never returns
    * Make sure not to modify REG_RA before calling
    * CALLOUT_CHAIN, as this will be need to patch the
    * chaining logic. 
    *
    * The prelude is entered through an indirect
    * jump off 0(REG_PV). -8(REG_PV) contains the
    * PC to check for.   
    */
   
   while ((intPtrSize)conf.memptr & 0x7) {
      /* Align */
      (conf.memptr++)->word = 0;
   }  
   * (VA*)conf.memptr = vPC;
   conf.memptr += sizeof(VA)/INST_SIZE;
   
   conf.startSpeculative = conf.memptr;
   EMIT_LOAD(checkPC,REG_PV,-8);
   EMIT_OP(op_intl,intl_xor,checkPC,DELTAREG_PC,checkPC);
   EmitBranchToCode(op_bne,checkPC,CALLOUT_CHAIN_SPEC);

   ASSERT( conf.memptr - conf.startSpeculative == BYPASS_SPECULATION);


   /*
    * ITB check (bypass possible)
    */
   
   EmitBranchToCode(op_bsr,REG_RA,CALLOUT_ITB);
   
   ASSERT( conf.memptr - conf.startSpeculative ==BYPASS_SPECULATION+BYPASS_ICHECK);
   /*
    * Cycle check
    */

   EmitBranchToCode(op_blt,DELTAREG_COUNTDOWN,CALLOUT_CTXT);

   /*
    * Decrement the cycle countdown 
    */
   EMIT_LDA(DELTAREG_COUNTDOWN,DELTAREG_COUNTDOWN, -1*bb->numCycles);
   
}


static TCA FindTCA(VA nextPC)
{
   MA mAddr = QCLookup(conf.iQC,nextPC,0);
   /* ASSERT(nextPC != 0x3ff8001af70); */
   if (mAddr) { 
      TCA tca = TC_PCLookup(conf.tcCache,nextPC,mAddr);
      if (tca) {
         if (delta.bypassICheck && 
	     VADDR2VPN(bb.vPC)==VADDR2VPN(nextPC)) {
            return tca + BYPASS_SPECULATION + BYPASS_ICHECK;
         } else {
            return tca + BYPASS_SPECULATION;
         }
      }
   }
   return 0;
}

/* ***********************************************************
 * UpdatePC
 * 
 * First, save the PC into P->PC. 
 * Coundown is already take care of at start of BB
 * Emit the code to jump to the emmitted chaining code
 * This target will be overridden by chaining
 * You never return from here
 * *************************************************************/

void UpdatePC(int64 diff)
{
   VA nextPC = bb.vPC + diff;
  
   union alpha_instruction inst;
      

   /*
    * If the next BB is already translated and in the IQC
    * directly emit a branch to it which bypassed the speculative
    * entry point
    */

   if (delta.chainKnownBranches) { 
      TCA tca = FindTCA(nextPC);
      if (tca) {
         int offset;
  
         /* 
          * update pc
          */
         EmitAdd(DELTAREG_PC,diff,DELTAREG_PC);

	 offset = (tca - conf.memptr)-1;
         inst.common.opcode = op_br;
         inst.b_format.ra = REG_ZERO;
         inst.b_format.branch_displacement = offset;
         ASSERT( offset==inst.b_format.branch_displacement);
         EMIT_INSTR(inst);
         return;           
      }
   }


   /*
    * Emit a pc-relative branch to the chaining
    * code, later to be overridden with a 
    * op_bsr directly to the TC
    */
   
      
   EMIT_MOVE(DELTAREG_PC,DELTAREG_PREV_PC);
   EmitAdd(DELTAREG_PC,diff,DELTAREG_PC);
   /*
    * xxx in Emit_Callout
    * EMIT_STORE(DELTAREG_COUNTDOWN,DELTAREG_BASE,COUNTDOWN_OFF);
    * EMIT_STORE(DELTAREG_PC,DELTAREG_BASE,PC_OFF);
    */
   EmitBranchToCode(op_bsr,REG_RA,CALLOUT_CHAIN );
   return;


#if dead_code
   /*
    * prev_pc <- pc, update pc 
    */
   ASSERT(0);
   EMIT_MOVE(DELTAREG_PC,DELTAREG_PREV_PC);
   EMIT_STORE(DELTAREG_COUNTDOWN,DELTAREG_BASE,COUNTDOWN_OFF);
   EmitAdd(DELTAREG_PC,diff,DELTAREG_PC);
   EMIT_STORE(DELTAREG_PC,DELTAREG_BASE,PC_OFF);


   /*
    * Dead code from here on
    *
    * slower path. Register indirect jump for now
    * to callout, to be patched to the target block
    */   
   
   target = GetEmitFunction(conf.tcCache, CALLOUT_CHAIN_SPEC);
   constantOffset = DeltaAllocateConstant(target);
   EMIT_LOAD(REG_PV,DELTAREG_CONSTANTS,constantOffset);
   
   
   /*
    * jump to emitted CHAIN, or to chained block
    * to the chained block.
    * In any case, You never return from that jump
    */
   
   inst.common.opcode = op_jsr;
   inst.j_format.ra = REG_RA;
   inst.j_format.rb = REG_PV;
   inst.j_format.function = jsr_jsr; 
   EMIT_INSTR(inst);
#endif

}


TCA PatchBranch(VA prevPC, VA pc, TCA chainAddr,TCA tca)
{
   int tcCache = 0;
   int64 diff;
   ASSERT(chainAddr);
   ASSERT(chainAddr->common.opcode == op_bsr);
   ASSERT(TC_InTC(tcCache,chainAddr));

   if (delta.chainBranches) { 
      
      if (delta.bypassICheck && 
	  VADDR2VPN(prevPC)==VADDR2VPN(pc)) {
         tca += BYPASS_SPECULATION + BYPASS_ICHECK;
      } else {
         tca += BYPASS_SPECULATION;
      }
      
      diff = ((int64)tca - (int64)chainAddr) /(int)INST_SIZE;
      diff = diff-1;
      chainAddr->b_format.branch_displacement = diff;
      ASSERT( chainAddr->b_format.branch_displacement == diff);
      FlushOneLine(tca); 
      
#if 0
      CPUWarning("Patching Branch chain prevPC=0x%lx pc=0x%lx chainAddr=0x%lx tca=0x%lx\n",
                 prevPC,pc,chainAddr,tca);
#endif
   }
   return tca;  
}
   
TCA PatchSpeculative(TCA chainAddr, TCA targetAddr)
{
   int tcCache = 0;

   chainAddr -= LOAD_PV_OFFSET;

   if (delta.chainSpec && chainAddr) { 
      int offset = chainAddr->m_format.memory_displacement;
      TCA *location = (TCA*) ((char*)constantsPtr + offset); 
      ASSERT(chainAddr->common.opcode == op_ldq);
      ASSERT(chainAddr->m_format.ra =REG_PV);
      ASSERT(chainAddr->m_format.rb =DELTAREG_CONSTANTS);
      ASSERT( TC_InTC(tcCache,*location));
      *location = targetAddr;
   }
   return targetAddr;
}

      

/* ***********************************************************
 * TranslateOne 
 * ***********************************************************/
static void inline TranslateOne(BasicBlockInstr *i)
{
 
   union alpha_instruction orig = i->instr;
   union alpha_instruction new = orig;
   int opcode = orig.common.opcode;
   
   int pcOffset = i->offset;

   

   switch(opcode) { 
      
   case op_call_pal:
   {
      if (!orig.word) { 
         CPUError("Reached callpal halt instruction\n");
      }
      
      Callout(i,CALLOUT_CALLPAL);    
      break;
   }
   case op_lda: 
   case op_ldah: 
      new.m_format.rb = LoadRegister(orig.m_format.rb);
      new.m_format.ra = TargetRegister(orig.m_format.ra);
      EMIT_INSTR(new);
      StoreRegister(new.m_format.ra,orig.m_format.ra,i->saveReg);
      break;
      
   case op_ldq_u:
   case op_ldl:
   case op_ldq:
   case op_ldl_l:
   case op_ldq_l:
   {
      EmitReference(i,CALLOUT_DTB_LOAD);

      new.m_format.ra = TargetRegister(orig.m_format.ra);
      new.m_format.rb = REG_V0;
      new.m_format.memory_displacement = 0;


      EMIT_INSTR(new);
      if (orig.m_format.ra!=REG_ZERO) {
	 StoreRegister(new.m_format.ra, orig.m_format.ra,i->saveReg);
      }

      if (opcode==op_ldl_l || opcode==op_ldq_l) { 
	 EMIT_STORE(REG_V0,DELTAREG_BASE,LLADDR_OFF);
	 EMIT_STORE(new.m_format.ra,DELTAREG_BASE,LLVALUE_OFF);
      }
      break;
   }

   case op_ldf:
   case op_ldg:
   case op_lds:
   case op_ldt:
   {
      CheckFPEnabled(i);
      EmitReference(i,CALLOUT_DTB_LOAD);

      new.m_format.ra = TargetFPRegister(orig.m_format.ra);
      new.m_format.rb = REG_V0;
      new.m_format.memory_displacement = 0;


      EMIT_INSTR(new);
      if (orig.m_format.ra!=REG_ZERO) {
	 StoreFPRegister(new.m_format.ra, orig.m_format.ra,0);
      }

      break;
   }

   case op_stq_u:
   case op_stl:
   case op_stq:
   {
      EmitReference(i,CALLOUT_DTB_STORE);

      new.m_format.memory_displacement = 0;
      new.m_format.ra = LoadRegister(orig.m_format.ra);
      new.m_format.rb = REG_V0;

      EMIT_INSTR(new);
      break;
   }

   case op_stf:
   case op_stg:
   case op_sts:
   case op_stt:
   {
      CheckFPEnabled(i);
      EmitReference(i,CALLOUT_DTB_STORE);

      new.m_format.memory_displacement = 0;
      new.m_format.ra = LoadFPRegister(orig.m_format.ra,0);
      new.m_format.rb = REG_V0;


      EMIT_INSTR(new);
      break;
   }
      
   case op_stl_c:
   case op_stq_c:
   {
      /*
       * REG_A0: effective address 
       * REG_V0: physical address
       */
      HRegIdx tmp = TempRegister();  
      HRegIdx tmp2 = TempRegister();
      HRegIdx tmp3 = TempRegister();
      HRegIdx ra   = LoadRegister(orig.m_format.ra);
      TCA instr;

      ASSERT (orig.m_format.ra != REG_ZERO);
#if 0
      CPUWarning("Translating LL/SC at pc=0x%lx \n",bb.vPC);
      /* conf.printBB = 1; */
#endif
#if 0
      /* debug user-level ll/sc */
      if ((int64)bb.vPC > 0) { conf.printBB=1;}
#endif
      EmitReference(i,CALLOUT_DTB_STORE);

      /*
       * compare value and address 
       */
      EMIT_LOAD(tmp,DELTAREG_BASE,LLADDR_OFF);
      EMIT_OP(op_intl,intl_xor,tmp,REG_V0,tmp);
      
      EMIT_LOAD(tmp2,DELTAREG_BASE,LLVALUE_OFF);

      if (opcode==op_stl_c) { 
	 EMIT_M(op_ldl,tmp3,REG_V0,0);
      } else {
	 EMIT_LOAD(tmp3,REG_V0,0);  
      }

      EMIT_OP(op_intl,intl_xor,tmp2,tmp3,tmp2);
      EMIT_OP(op_intl,intl_bis,tmp,tmp2,tmp);

      StoreRegister(REG_ZERO,orig.m_format.ra,i->saveReg);
      
      {
	 new.common.opcode = op_bne;
	 new.b_format.ra = tmp;
	 new.b_format.branch_displacement = 3; /* 3 instr */
	 EMIT_INSTR(new);
      }
      
      instr = conf.memptr;
      if (opcode==op_stl_c) { 
	 EMIT_M(op_stl,ra,REG_V0,0);
      } else {
	 EMIT_STORE(ra,REG_V0,0);
      }
  
      EMIT_LDA(tmp,REG_ZERO,1);
      StoreRegister(tmp,orig.m_format.ra,i->saveReg);

      break;
   }   
 

   case op_br:
   case op_bsr:
      if (orig.b_format.ra != REG_ZERO) {
         HRegIdx reg = TargetRegister(orig.b_format.ra);
	 EmitAdd(DELTAREG_PC,pcOffset+4,reg);
         StoreRegister(reg,orig.b_format.ra,i->saveReg);
      }
      if (!i->mergedBranch) { 
         UpdatePC((orig.b_format.branch_displacement<<2)+ pcOffset + 4);
         conf.endsWithBranch = 1;
      }

      break;

   case op_blbc:
   case op_beq:
   case op_blt:
   case op_ble:
   case op_blbs:
   case op_bne:
   case op_bge:
   case op_bgt:
      
   { 
      union alpha_instruction *savedInstr;
      new.b_format.ra = LoadRegister(orig.b_format.ra);    
      
      savedInstr = conf.memptr;
      EMIT_INSTR(new);    /* bogus branch */
      UpdatePC(pcOffset+4);
      
      new.b_format.branch_displacement = (conf.memptr-savedInstr)-1;
      PATCH_INSTR(savedInstr,new);
      
      UpdatePC(pcOffset+(orig.b_format.branch_displacement<<2)+4);
      conf.endsWithBranch =1;
      break;
   }
      
   case op_fbeq:
   case op_fblt:
   case op_fble:
   case op_fbne:
   case op_fbge:
   case op_fbgt:
   { 
      union alpha_instruction *savedInstr;
      HRegIdx fpcr;
      CheckFPEnabled(i);
      fpcr = LoadFPCRRegister();

      new.b_format.ra = LoadFPRegister(orig.b_format.ra,0);    
      
      savedInstr = conf.memptr;
      EMIT_INSTR(new);    /* bogus branch */
      StoreFPCRRegister(fpcr);
      UpdatePC(pcOffset+4);
      
      new.b_format.branch_displacement = (conf.memptr-savedInstr)-1;
      PATCH_INSTR(savedInstr,new);
      
      StoreFPCRRegister(fpcr);
      UpdatePC(pcOffset+(orig.b_format.branch_displacement<<2)+4);
      conf.endsWithBranch =1;
      break;
   }
      
   case op_inta:
   case op_intl:
   case op_ints:
   case op_intm:
      if (orig.o_format.rc != REG_ZERO) {
	 int flags = gammaOperateFlags[opcode*(1<<7)+orig.o_format.function];
	 ASSERT(flags&AXPTYPE_INT);
	 
         /*
          * Some operations are only implemented in Gamma, such as amask
          */
         if (flags&AXPTYPE_GAMMA)
            goto callout_misc;

	 /*
	  * Support for PRECISE exceptions. Save the PC away
	  * Ideally, should also save DELTAREG_CALLOUT_CCD but that
	  * is really not worth it
	  */

	 if (flags&AXPTYPE_CANTRAP) {
	    EMIT_LDA(DELTAREG_CALLOUT_PC,DELTAREG_PC,i->offset);
	 }

	 new.o_format.ra = LoadRegister(orig.o_format.ra);
	 if (!orig.o_format.form) {
	    new.o_format.rb = LoadRegister(orig.o_format.rb);
	 }
	 
	 if (flags&AXPTYPE_INT_CONDITIONAL) {
	    new.o_format.rc = LoadRegister(orig.o_format.rc);
	 } else {
	    new.o_format.rc = TargetRegister(orig.o_format.rc);
	 }
	 EMIT_INSTR(new);
         if (flags&AXPTYPE_CANTRAP) {
            union alpha_instruction trapb;
            trapb.common.opcode = op_misc;
            trapb.m_format.memory_displacement = misc_trapb;
            EMIT_INSTR(trapb);
         }
	 StoreRegister(new.o_format.rc,orig.o_format.rc,i->saveReg); 
      }
      break;

   callout_misc:
   case op_opc14:
      /* These opcodes not supported by current Alpha, so let Gamma handle them */
      Callout(i,CALLOUT_MISC);
      break;
   case op_fltv:
   case op_flti:
   case op_fltl:
   {
      HRegIdx fpcr;
      CheckFPEnabled(i);
      fpcr = LoadFPCRRegister();
      
      if (orig.f_format.fc != REG_ZERO) {
	 int flags = gammaFPFlags[opcode*(1<<11)+orig.f_format.function];
	 ASSERT(flags&AXPTYPE_FP);

	 new.f_format.fa = LoadFPRegister(orig.f_format.fa,flags);
	 new.f_format.fb = LoadFPRegister(orig.f_format.fb,flags);
	 
	 if (flags&AXPTYPE_FP_CONDITIONAL) {
	    new.f_format.fc = LoadFPRegister(orig.f_format.fc,flags);
	 } else {
	    new.f_format.fc = TargetFPRegister(orig.f_format.fc);
	 }
	 EMIT_INSTR(new);
	 StoreFPRegister(new.f_format.fc,orig.f_format.fc,flags); 
      }
      StoreFPCRRegister(fpcr);
      break;
   }
   case op_jsr:
   { 
      /*
       * XXX be really careful of case when ra==rb
       * XXX AXP manual page 4-21
       */
      void *target = GetEmitFunction(conf.tcCache, CALLOUT_CHAIN_SPEC);
      int constantOffset = DeltaAllocateConstant(target);   
      HRegIdx reg; 
      union alpha_instruction inst;
      TCA savedAddr;

      reg = LoadRegister(orig.j_format.rb);
      if (orig.j_format.ra  ==REG_ZERO) {
	 /* nothing */
      } else if (orig.j_format.ra == orig.j_format.rb) {
	 HRegIdx tmp = TempRegister();
	 EmitAdd(DELTAREG_PC,pcOffset+4,tmp);
         StoreRegister(tmp,orig.j_format.ra,i->saveReg);
      } else {
	 HRegIdx tmp = TargetRegister(orig.j_format.ra);
	 EmitAdd(DELTAREG_PC,pcOffset+4,tmp);
         StoreRegister(tmp,orig.j_format.ra,i->saveReg);
      }
      
      /*
       * Store new PC and COUNTDOWN
       * jump to emitted CHAIN, or to chained block
       * to the chained block.
       * In any case, You never return from that jump
       */
      
      EMIT_LOAD(REG_PV,DELTAREG_CONSTANTS,constantOffset);
      savedAddr = conf.memptr;
      EMIT_STORE(DELTAREG_COUNTDOWN,DELTAREG_BASE,COUNTDOWN_OFF);
      EMIT_MOVE(reg,DELTAREG_PC);
      EMIT_STORE(reg,DELTAREG_BASE,PC_OFF);
      
      inst.common.opcode = op_jsr;
      inst.j_format.ra = REG_RA;
      inst.j_format.rb = REG_PV;
      inst.j_format.function = jsr_jsr; 
      EMIT_INSTR(inst);

      ASSERT( savedAddr + LOAD_PV_OFFSET == conf.memptr);

      conf.endsWithBranch=1;
      break;
   }
   case op_misc:
      Callout(i,CALLOUT_MISC);
      break;

   case PRIV_OP_MTPR: 
   case PRIV_OP_MFPR: 
   case PRIV_OP_HW_LD:
   case PRIV_OP_HW_ST: 
   case PRIV_OP_REI: 
      CPUError("Executing privileged instructions\n");
      break;

   default:
      ASSERT (0);
   } /* switch(opcode) */
}

   
VA debugPC = 0x120009eb5;
TCA Translate(int cpuNum, VA vPC, PA pPC, MA mAddr, QCTable *iQC)
{
   
   int estTransLen;
   TCA tcStart;
   int tcCache = 0;
   int i;


   ASSERT( vPC != debugPC);
  
   TranslatorStart(tcCache);
   Decode(vPC,mAddr,&bb);
   conf.iQC = iQC;

   if (vPC == debugPC) {
      conf.printBB = 1;
   }

   /*
    * black magic. Upper bound checked a posteriori 
    */
   estTransLen = (12*bb.numInstructions + 20); 
   if (!TC_Is_Room(INST_SIZE*estTransLen,tcCache)) {
      DeltaClearTranslationCache(tcCache,DELTAFLUSH_TC);
   }

   if (DeltaRemainingConstants() < 4) { 
      DeltaClearTranslationCache(TCFLUSH_ALL, DELTAFLUSH_CONSTANTS);
   }

   tcStart = conf.memptr = TC_GetTCPtr(tcCache);
   if (delta.debugCycle && 
       CPUVec.CycleCount(0) > delta.debugCycle) { 
      CPUPrint("Translating pc=0x%lx mAddr=0x%lx tca=0x%lx \n",
	       vPC,mAddr,tcStart);
   }
   Prelude(&bb);
   /*
    * FEN check
    */
   if (0)
     if (bb.usesFP) /* @@@@ needs fixing, for now we use Gamma for all FP */
       Callout(&bb.instr[0],CALLOUT_FEN);
   PreloadRegs();
      
   for(i=0;i<bb.numInstructions;i++) {
      conf.nextFree = 0; /* reuse temp registers */
      conf.fpFree = 0;
      if (bb.instr[i].prePCAnn) { 
         Callout(&bb.instr[i],CALLOUT_PREPC_ANN);
	 TC_IncrementSize(tcCache,LENGTH_EMIT_CALLOUT);
	 conf.nextFree = 0;
      }
      if (bb.instr[i].isBranch &&  bb.instr[i].postPCAnn) { 
         Callout(&bb.instr[i],CALLOUT_POSTPC_ANN);
	 TC_IncrementSize(tcCache,LENGTH_EMIT_CALLOUT);
	 conf.nextFree = 0;
      }
      TranslateOne(&bb.instr[i]);
      if (!bb.instr[i].isBranch && bb.instr[i].postPCAnn) { 
         Callout(&bb.instr[i],CALLOUT_POSTPC_ANN);
	 TC_IncrementSize(tcCache,LENGTH_EMIT_CALLOUT);
	 conf.nextFree = 0;
      }
   }
   if (!conf.endsWithBranch) {
      int64 diff = (int64)bb.nextPC-(int64)vPC;
      ASSERT(bb.nextPC);
      UpdatePC(diff);
   }     
   
   /*
    * Cache coherency: although this is not *exactly* correct,
    * the following strategy should catch all Tc coherency
    * problems in practice:
    * If we emit, we mark the pAddr to be text and
    * downgrade the vAddr and the corresponding KSEG addr
    * --> if there is another vAddr that points to the 
    * --> page and writes to it, then we are in tough luck.
    */

   /* mark the entire page. */
   {
      MA end = (MA) (((uint64)mAddr+PAGE_SIZE)&~(PAGE_SIZE-1));
      TCcoherence_mark_code(mAddr,end);
   }
   QCDowngrade(cpuNum,VADDR2TAG(vPC));
   QCDowngrade(cpuNum,VADDR2TAG(pPC|KSEG));
   QCDowngrade(cpuNum,VADDR2TAG(pPC|KSEG_32));

   TC_PCInsert(tcCache,conf.startSpeculative,vPC,mAddr);
   TC_SetTCNext(tcCache,tcStart,conf.memptr);
   ASSERT(conf.memptr-tcStart < estTransLen);

   if (conf.printBB) { 
      PrintBasicBlock(&bb,tcStart);
   }
   return conf.startSpeculative;
}

extern void disasm();

void PrintBasicBlock( BasicBlock *bb, TCA tcaStart)
{
   int i;
   TCA tca;
   long piG1=0, piG2=0, piG3=0;
   
   CPUPrint("\n");
   for (i=0;i<bb->numInstructions;i++) {
      char buf[200];
      disasm(buf,
             bb->vPC + bb->instr[i].offset,
             bb->instr[i].instr.word,
             &piG1, &piG2, &piG3);
      CPUPrint("  BB     %s\n",buf);
   }
   CPUPrint("\n");
   for (tca=tcaStart; tca->word != illegalInstr.word; tca++) {
      char buf[200];
      disasm(buf,tca,tca->word, &piG1, &piG2, &piG3);
      CPUPrint("  BB_TC  %s\n", buf);
   }
}