/*
 * Copyright (C) 1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * Copyright (C) 1998 Digital Equipment Corporation
 *
 * This file is part of the SimOS distribution.
 * See LICENSE file for terms of the license.
 *
 */



/* ******************************************************
 * gamma.c
 *
 * main fetch/decode/execute loop for the gamma instruction
 * set interpreter. To be integrated into SimOS. 
 * ******************************************************/

#include <setjmp.h>
#include <math.h>
#include <signal.h>
#include <alpha/inst.h>
#include <alpha/fpu.h>
#include <siginfo.h>

#include "simtypes.h"
#include "sim_error.h"
#include "registry.h"
#include "machine_params.h"
#include "params.h"

#include "gamma.h"
#include "ev5.h"
#include "ev5_ipr.h"
#include "disassembler.h"
#include "alpha_regs.h"
#include "alpha_params.h"
#include "memref.h"
#include "alpha_memref.h"
#include "ipr_decode.h"
#include "alpha_trace.h"

#include "tcl_init.h"
#include "print_insts.h"
#include "cpu_stats.h"
#include "cpu_interface.h"
#include "stats.h"
#include "qc.h"

#include "external_trace.h"

typedef int (*MagicFunction)(int   cpuNum, /* CPU making this access */
			     VA   va,     /* accessed virtual address */
			     int   type,   /* access type */
			     void* buff);  /* buff width acc to type */


#define CACHE_LINE_SIZE 64 /* elsewhere XXX */

/* ********************************************
 * globals
 * ********************************************/
/* The instruction formats corresponding to the opcodes of instructions */



int Pindex;
AlphaState *curPE;
int numCPUs;
int64 gammaCurrentTime[SIM_MAXCPUS];
jmp_buf     jmpEnv;                    /* Used to exit the main loop */
int numLLActive;

GammaParams gammaParams;

uint gdbInstr;
uint gdbInstrCommon;
static int prePCAnnsExist;

static void GammaCPURun(void);
static void DoneRunning(void);
char * GammaStats(void);

int gamma_debug_mode = 0;
int gamma_break_nexti = 0;
int gamma_sigusr = 0;
int gammaArithTrap = 0;


/*****************************************************************
 * ANNOTATION SUPPORT!
 *****************************************************************/
#define CHECK_LD_ANN(_vAddr, _pAddr) \
{  if (annLoads) {        \
      AnnPtr ptr = AnnFMLookup(_vAddr, ANNFM_LD_TYPE);\
      if (ptr)         \
         AnnExec(ptr); \
      ptr = AnnFMLookup(_pAddr, ANNFM_LD_TYPE);\
      if (ptr)         \
         AnnExec(ptr); \
   }                         \
}

#define CHECK_ST_ANN(_vAddr,_pAddr) \
{ if (annStores) {         \
      AnnPtr ptr = AnnFMLookup(_vAddr, ANNFM_ST_TYPE);\
      if (ptr)         \
         AnnExec(ptr); \
      ptr = AnnFMLookup(_pAddr, ANNFM_ST_TYPE);\
      if (ptr)         \
         AnnExec(ptr); \
 }                         \
}



/* ************************************************
 * main entry point
 * ************************************************/

void ExecuteGamma(void)
{
  int i;

  /*
   * setup original arguments
   */
  GammaInitTables();
  GammaCPUVectorInit();

  if (!alphaLateInitDone) {
     /*
      * Stuff that needs late initalization.
      * XXX should use a register mechanism
      */

     AnnCommonSetup();
     AnnFMInit(128);
     InstallPoller();  /* devices */
     prePCAnnsExist = AnnFMTypesExist(ANNFM_PRE_PC_TYPE);
     InitSimulatorStats(4*1024*1024, GammaStats);
     HWEventsLateInit();
     alphaLateInitDone = 1;


     /*
      * simos enter annotation
      */
     {
        int cpu;
        for (cpu=0;cpu<TOTAL_CPUS;cpu++) {
           curPE = PE[cpu];
           AnnExec(AnnFind("simos","enter"));
        }
        curPE = PE[0];
     }

     for (i=0; i < SIM_MAXCPUS; i++)
        gammaCurrentTime[i] = -1;
  }

  curPE = PE[0];
  Pindex = 0;
  curPE->cpuState = cpu_running;
  numCPUs = NUM_CPUS(0);
  EXTERNAL_TRACE_PE(curPE);

  CPUWarning("P->PC entry = 0x%lx \n",curPE->PC);

  GammaFPInit(); /* installs SIGFPE handler */

  {
     int toCPUType = NO_CPU;
     if ((toCPUType = setjmp(jmpEnv)) != 0) {
        if (gammaArithTrap) {
           gammaArithTrap = 0;
           GammaCPURun();
        } else { 
           DoneRunning();
           simosCPUType = toCPUType;
        }
     } else {
        GammaCPURun();
     }
  }
}


Result GammaUncachedOperation(VA  vAddr, int type, void *data)
{
   AlphaState *P = curPE;
   void *func;
   int flag;
   Result result;

   if (!RegistryIsInRange(vAddr, &func, &flag)) {
      CPUError("UNCACHED OPERATION at vAddr=0x%lx pc=0x%lx val=0x%lx \n",
	       vAddr,P->PC,P->reg[REG_RA]);
   }
   if (!(flag & REG_FUNC)) { 
      CPUError("GammUncached op at va 0x%lx pc 0x%lx val=0x%lx\n",
	       vAddr,P->PC,P->reg[REG_RA]);
   }
   ASSERT(flag & REG_FUNC);
   result = (Result)((MagicFunction)func)(P->myNum, vAddr, type, data); 
   if (gammaParams.debugLoadStore || vAddr == alphaDebugParams.debugVATranslation)
     CPUWarning("GammaUncachedOperation: func=%p va=%lx type=%d data=%lx\n", func, vAddr, type, *(long*)data);
   switch (type) {
   case BDOOR_LOAD_BYTE:
   case BDOOR_LOAD_HALF:
   case BDOOR_LOAD_WORD:
   case BDOOR_LOAD_DOUBLE:
     CHECK_LD_ANN(vAddr, vAddr);
     break;
   case BDOOR_STORE_BYTE:
   case BDOOR_STORE_HALF:
   case BDOOR_STORE_WORD:
   case BDOOR_STORE_DOUBLE:
     CHECK_ST_ANN(vAddr, vAddr);
     break;
   default:
     CPUWarning("@@@ GammaUncachedOperation: type=%d\n", type);
   }
   return result;
}


int GammaMemoryReadOpcode(int opcode,Reg *raPtr, Reg vAddr)
{
   AlphaState *P = curPE;
   MA mAddr=0;
   PA pAddr=0;
   MMUStatus status;
   RefSize refSize = alphaRefSizeMap[opcode];
   mAddr = QCLookup(curPE->curDQC,vAddr,0);
   if (mAddr) {
      status = MMU_SUCCESS;
      pAddr=MEMADDR_TO_PHYS(M_FROM_CPU(curPE->myNum),mAddr);
   } else {
      status =EV5_DTranslateVirtual(curPE,vAddr,0,1,&pAddr);
      mAddr = PHYS_TO_MEMADDR(0,pAddr);
   }
   if ((int)vAddr == (int)alphaDebugParams.debugVATranslation) {
     CPUWarning("GammaMemoryReadOpcode: DVAT pc=%lx status=%d va=%lx pa=%lx ma=%lx\n",
		P->PC, status, vAddr, pAddr, mAddr);
   }
   if (status == MMU_SUCCESS) {
      if (pAddr >= MEM_SIZE(0)) {
	 CPUError("GammaMemoryReadOpcode vA=0x%lx pA=0x%lx pc=0x%lx val=0x%lx\n",
		  vAddr,pAddr,P->PC, P->reg[REG_RA]);
      }
      ASSERT( pAddr < MEM_SIZE(0));
      if (!gammaMemoryTable[opcode]) {
	 CPUError("MemoryRead: opcode %d unknown \n");
      }
      CHECK_LD_ANN(vAddr,pAddr);
      STATS_INC(P->myNum, dReads, 1);
      TRACE_ENTRY(TRACE_LOAD,curPE->myNum,vAddr);
      gammaMemoryTable[opcode](raPtr, NULL,(Reg*)mAddr,pAddr,vAddr);
      if (gammaParams.debugLoadStore || vAddr == alphaDebugParams.debugVATranslation)
	CPUWarning("GammaMemoryReadOpcode: pc=%lx val=%016lx vaddr=%lx paddr=%lx maddr=%lx, status=%d cycle=%ld\n",
		   P->PC, *raPtr, vAddr, pAddr, mAddr, status, gammaCurrentTime[P->myNum]);
      return 0;
   } else if (status == MMU_EXCEPTION) { 
      return 1;
   } else {
      int bdoortype = (refSize == WORD_SZ ? BDOOR_LOAD_WORD : BDOOR_LOAD_DOUBLE);
      bdoortype = BDOOR_LOAD_WORD;
      ASSERT( status==MMU_UNCACHED);
      status = GammaUncachedOperation(vAddr,bdoortype,raPtr);
      if (gammaParams.debugLoadStore || vAddr == alphaDebugParams.debugVATranslation)
	CPUWarning("GammaMemoryReadOpcodeUncached: pc=%lx val=%016lx vaddr=%lx paddr=%lx maddr=%lx status=%d cycle=%ld\n",
		   P->PC, *raPtr, vAddr, pAddr, mAddr, status, gammaCurrentTime[P->myNum]);

      if (status==MMU_SUCCESS) return 0;
      if (status==MMU_EXCEPTION) return 1;
      ASSERT(0);
      return 0;
   }
}


int GammaMemoryWriteOpcode(int opcode, Reg *rdestp, const Reg *raPtr, Reg vAddr) 
{
   AlphaState *P = curPE;
   MA mAddr=0;
   PA pAddr=0;
   MMUStatus status;
   RefSize refSize = alphaRefSizeMap[opcode];
   mAddr = QCLookup(curPE->curDQC,vAddr,1);
   if (mAddr) {
      status = MMU_SUCCESS;
      pAddr=MEMADDR_TO_PHYS(M_FROM_CPU(curPE->myNum),mAddr);
   } else {
      status =EV5_DTranslateVirtual(curPE,vAddr,1,1,&pAddr);
      mAddr = PHYS_TO_MEMADDR(0,pAddr);
   }
   if ((int)vAddr == (int)alphaDebugParams.debugVATranslation) {
     CPUWarning("GammaMemoryWriteOpcode: DVAT pc=%lx status=%d va=%lx pa=%lx ma=%lx\n",
		P->PC, status, vAddr, pAddr, mAddr);
   }

   ASSERT( vAddr != 0xfffffc000023faf0);
   if (status==MMU_SUCCESS) { 
      if (pAddr >= MEM_SIZE(0)) {
	 CPUError("GammaMemoryWriteOpcode vA=0x%lx pA=0x%lx pc=0x%lx val=0x%lx\n",
		  vAddr,pAddr,P->PC, P->reg[REG_RA]);
      } 
      ASSERT (mAddr);
      if (!gammaMemoryTable[opcode]) {
	 CPUError("MemorWrite: opcode %d unknown \n");
      }

      CHECK_ST_ANN(vAddr,pAddr);
      STATS_INC(P->myNum, dWrites, 1);
      TRACE_ENTRY(TRACE_STORE,curPE->myNum,vAddr);
      gammaMemoryTable[opcode](rdestp, raPtr,(Reg*)mAddr,pAddr,vAddr);
      if (gammaParams.debugLoadStore || vAddr == alphaDebugParams.debugVATranslation)
	CPUWarning("GammaMemoryWriteOpcode: pc=%lx val=%016lx vaddr=%lx paddr, maddr=%lx, status=%d cycle=%ld\n",
		   P->PC, *raPtr, vAddr, pAddr, mAddr, status, gammaCurrentTime[P->myNum]);
      if (numLLActive) {
	 VA align = (VA)pAddr & ~(VA)(CACHE_LINE_SIZE-1);
	 int i;
	 for (i=0;i<numCPUs;i++) {
	    if (Pindex==i) continue;
	    if (PE[i]->lock_flag && PE[i]->locked_addr == align) { 
	       PE[i]->locked_addr = 0;
	       PE[i]->lock_flag = 0;
	       numLLActive--;
	       ASSERT(numLLActive>=0);
	    }
	 }
	 if (curPE->lock_flag) {
	    curPE->lock_flag = 0;
	    numLLActive--;
	    ASSERT(numLLActive>=0);
	 }
      }
      return 0;
   } else if (status==MMU_EXCEPTION) {
      return 1;
   } else  {
      int bdoortype = ((refSize == WORD_SZ) ? BDOOR_STORE_WORD : BDOOR_STORE_DOUBLE);
      bdoortype = BDOOR_STORE_WORD;
      ASSERT( status==MMU_UNCACHED);
      status = GammaUncachedOperation(vAddr, bdoortype, (void *)raPtr);
      if (gammaParams.debugLoadStore || vAddr == alphaDebugParams.debugVATranslation)
	CPUWarning("GammaMemoryWriteOpcodeUncached: pc=%lx val=%016lx vaddr=%lx paddr=%lx maddr=%lx status=%d cycle=%ld\n",
		   P->PC, *raPtr, vAddr, pAddr, mAddr, status, gammaCurrentTime[P->myNum]);
      if (status==MMU_SUCCESS) return 0;
      if (status==MMU_EXCEPTION) return 1;
      NOTREACHED();
      return 0;
   }
      
}

/* **********************************************
 * LL/SC support
 * **********************************************/

void ldl_l_ff(Reg *a, const Reg *b, Reg *mAddr, PA pAddr, VA vAddr)
{
   VA align = pAddr & ~(VA)(CACHE_LINE_SIZE-1);
   *a = *(unsigned*)mAddr;
   curPE->lock_flag = 1;
   curPE->locked_addr = align;
   numLLActive++;
}
void ldq_l_ff(Reg *a, const Reg *b, Reg *mAddr, PA pAddr, VA vAddr)
{
   VA align = pAddr & ~(VA)(CACHE_LINE_SIZE-1);
   *a = *(long*)mAddr;
   curPE->lock_flag = 1;
   curPE->locked_addr = align;
   numLLActive++;
}


void stl_c_ff(Reg *rdestp,  const Reg *a, Reg *mAddr, PA pAddr, VA vAddr)
{
   VA align = pAddr & ~(VA)(CACHE_LINE_SIZE-1);
   if (curPE->lock_flag && curPE->locked_addr==align) { 
      *(unsigned *)mAddr = (unsigned)(*a) ;
      *rdestp = 1;
   } else {
      *rdestp = 0;
   }
}

void stq_c_ff(Reg *rdestp,  const Reg *a, Reg *mAddr, PA pAddr, VA vAddr)
{
   VA align = pAddr & ~(VA)(CACHE_LINE_SIZE-1);
   if (curPE->lock_flag && curPE->locked_addr==align) { 
      *(long *)mAddr = (long)(*a) ;
      *rdestp = 1;
   } else {
      *rdestp = 0;
   }
}

/* **********************************************
 * SQRT support
 * **********************************************/

void sqrtt_ff(const double *a, const double* b, const double *c, double *rdest, Reg *fpcr)
{
  *rdest = sqrt(*b);
}

void sqrts_ff(const double *a, const double* b, const double *c, float *rdest, Reg *fpcr)
{
  *rdest = sqrt(*b);
}

/* **********************************************
 * FTOI/ITOF support
 * **********************************************/

void itofs_ff(const double *a, const double* b, const double *c, double *rdest, Reg *fpcr)
{
  *(float*)rdest = *a;
}

void itoff_ff(const double *a, const double* b, const double *c, double *rdest, Reg *fpcr)
{
  NOTREACHED();
}

void itoft_ff(const double *a, const double* b, const double *c, double *rdest, Reg *fpcr)
{
  *rdest = *a;
}

void ftois_ff(const double *a, const double* b, const double *c, double *rdest, Reg *fpcr)
{
  *(float*)rdest = *a;
}

void ftoit_ff(const double *a, const double* b, const double *c, double *rdest, Reg *fpcr)
{
  *rdest = *a;
}


/* **********************************************
 * AMASK (architecture mask) support
 * **********************************************/
void amask_ff(Reg a, Reg b, Reg *c, Reg *rdestp)
{
#ifdef op_ldbu
   /* byte/word load/store supported */
   *rdestp = (~(long)AMASK_BIT0_BWLS)&b;
#else
   *rdestp = 0;
#endif
}

void implver_ff(Reg a, Reg b, Reg *c, Reg *rdestp)
{
   *rdestp = IMPLVER_EV5_FAMILY;
}


/* **********************************************
 * FPCR support
 * **********************************************/

void mf_fpcr_ff(const double *a, const double* b, const double *c, double *rdest, Reg *fpcr)
{
  *(long *)rdest = *fpcr;
}

void mt_fpcr_ff(const double *a, const double* b, const double *c, double *rdest, Reg *fpcr)
{
  *fpcr = *(long *)a;
}



void GammaFPInit()
{
  struct sigaction action;
  struct sigaction oaction;
  static void gammaSigfpeHandler(int signal, siginfo_t *psiginfo, void *pcontext);

  action.sa_handler = (void(*)(int))gammaSigfpeHandler;
  action.sa_mask = 0;
  action.sa_flags = SA_SIGINFO;
  sigaction(SIGFPE, &action, &oaction);
}

int GammaFPCRIndicatesTrap(AlphaState *P) 
{
  Reg fpcr = P->fpcr;
  int res = 0;
  if ((P->PC & 1) == 0) {
    res = gammaArithTrap;
  }
  gammaArithTrap = 0;

  if (0 && (P->PC & 1) == 0) {
    if ((fpcr & FPCR_INV) && !(fpcr & FPCR_INVD))
      res = 1;
    if ((fpcr & FPCR_DZE) && !(fpcr & FPCR_DZED))
      res = 1;
    if ((fpcr & FPCR_OVF) && !(fpcr & FPCR_OVFD))
      res = 1;
    if ((fpcr & FPCR_UNF) && !(fpcr & FPCR_UNFD))
      res = 1;
    if ((fpcr & FPCR_INE) && !(fpcr & FPCR_INED))
      res = 1;
    if ((fpcr & FPCR_IOV))
      res = 1;
  }
  return res;
}

extern Reg gammaReadFPCR(void);

void gammaSigfpeHandler(int signal, siginfo_t *psiginfo, struct sigcontext *ctxt)
{
   int intTrap = 0;
  long code = psiginfo->si_code;
  Reg fpcr = gammaReadFPCR();
  Reg ofpcr = 0;
  Reg pc = (curPE != NULL ? curPE->PC : -1L);
  union alpha_instruction instr;
  if (curPE != NULL) {
    ofpcr = curPE->fpcr;
  }
  CPUVec.GetMemory(curPE->myNum, pc, 4, (char*)&instr);
  CPUWarning( "@@@@ gammaSigfpeHandler: pc=%lx instr=%x ofpcr=%lx actual fpcr=%lx code=%lx\n", 
	  pc, instr.word, ofpcr, fpcr, code);

  CPUWarning("@@@@ gammaSigfpeHandler: context pc=%lx ra=%lx \n",
             ctxt->sc_pc,ctxt->sc_regs[REG_RA]);
  
  
  
  switch (code) {
    
  case FPE_INTOVF: curPE->fpcr |= FPCR_IOV; intTrap=1; break;
  case FPE_FLTDIV: curPE->fpcr |= FPCR_DZE; intTrap=0; break;
  case FPE_FLTOVF: curPE->fpcr |= FPCR_OVF; intTrap=0; break;
  case FPE_FLTUND: curPE->fpcr |= FPCR_UNF; intTrap=0; break;
  case FPE_FLTRES: curPE->fpcr |= FPCR_INE; intTrap=1; break;
  case FPE_FLTINV: curPE->fpcr |= FPCR_INV; intTrap=1; break;

  case FPE_FLTSUB: 
  case FPE_INTDIV: 
  default: NOTREACHED();
  }

#if 0
  if (intTrap) {
     /*
      * sanity check. 
      */
     int i;
     long bestffptr = 0;
     long besti = -1;
     for (i=0;i<(1<<13);i++) {
        long ffptr = (long)gammaOperateTable[i];
        if (ffptr && ffptr < ctxt->sc_pc && ffptr>bestffptr) {
           bestffptr = ffptr;
           besti = i;
        }
     }
     CPUWarning("@@@@ gammaSigfpeHandler: (opcode,func)==%d ffptr=%lx\n",
                besti,bestffptr);
     ASSERT(i>0 && (gammaOperateFlags[i]&AXPTYPE_CANTRAP));
  } else { 
     int i;
     long bestffptr = 0;
     long besti = -1;
     for (i=0;i<(1<<17);i++) {
        long ffptr = (long)gammaFPTable[i];
        if (ffptr && ffptr < ctxt->sc_pc && ffptr>bestffptr) {
           bestffptr = ffptr;
           besti = i;
        }
     }
     CPUWarning("@@@@ gammaSigfpeHandler: (opcode,func)==%d ffptr=%lx\n",
                besti,bestffptr);
     ASSERT(i>0 && (gammaFPFlags[i]&AXPTYPE_CANTRAP));
  }
#endif
  if (GammaFPCRIndicatesTrap(curPE)) { 
     EV5_Trap(curPE,TRAP_ARITH);
  } else {
     CPUError("In GammaSigfpehandler. No trap \n");
  }
  gammaArithTrap = 1;
  longjmp(jmpEnv,1);
  NOTREACHED();
}




/* **********************************************
 *  Instruction Execution
 * **********************************************/

int GammaBranchOpcode( AlphaState *P, int opcode, Reg *pra, Reg_s r, double f)
{
#if 0
   CPUWarning("GammaBranchOpcode: pc=%lx r=%lx cycle=%ld\n",
              P->PC, r, gammaCurrentTime[P->myNum]);
#endif
  switch (opcode) {
  case op_br:  
  case op_bsr:
    *pra = (P->PC+4) & ~3;
    return 1;
  case op_blbc: return !(r&1);
  case op_beq: return (r==0);
  case op_blt: return (r<0);
  case op_ble: return (r<=0);
  case op_blbs: return (r&1);
  case op_bne: return (r!=0);
  case op_bge: return (r>=0);
  case op_bgt: return (r>0);
  case op_fbeq: return (f==0);
  case op_fblt: return (f<0);
  case op_fble: return (f<=0);
  case op_fbne: return (f!=0);
  case op_fbge: return (f>=0);
  case op_fbgt: return (f>0);
  default: 
     CPUError("unknown branch opcode: 0x%x \n",opcode);
  }
  NOTREACHED();
  return -1;
}
  

int GammaOperateOpcode(AlphaState *P,int code_func, Reg ra, Reg rb, const Reg * rcPtr, Reg * rdestPtr)
{ 
   /* xxx? Reg oldfpcr = gammaExchangeFPCR(P->fpcr); */
  
  if (!gammaOperateTable[code_func]) {
      CPUWarning("\nOperateOpcode, not def pc=%x code_func=%#x \n",
		 P->PC, code_func);
      *rdestPtr = *rcPtr;
    } else { 
      gammaOperateTable[code_func](ra,rb,rcPtr,rdestPtr);
    }
  
  /* gammaExchangeFPCR(oldfpcr); */

  return SUCCESS; 
};

int GammaFloatingOpcode(AlphaState *P,int opcode,int func, 
			const double *rap, const double *rbp, const double *rcp, double *rdestp)
{ 
   /* Reg oldfpcr = gammaExchangeFPCR(P->fpcr); */
  int ind = (opcode <<11) + func;

  if (!gammaFPTable[ind]) {
     CPUError("FPOpcode, not def pc=%lx opcode=%x func=%x \n",
              P->PC, opcode,func);
  } else { 
     gammaFPTable[ind](rap,rbp,rcp,rdestp,&P->fpcr);
  }
 
  /* gammaExchangeFPCR(oldfpcr); */
  return SUCCESS;
};

int GammaMiscOpcode(AlphaState *P, uint instr, Reg *rdestp)
{
   uint func = instr & 0xffff;
#if 0
CPUWarning("GammaMiscOpcode: pc=%lx cycle=%ld\n",
	   P->PC, gammaCurrentTime[P->myNum]);
#endif
   switch(func) {
   case misc_trapb:
   case misc_excb:
   case misc_mb: 
   case misc_wmb: 
   case misc_fetch: 
   case misc_fetch_m: 
#ifdef misc_wh64
   case misc_wh64: 
#endif
      return SUCCESS;
#ifndef SOLO
   case misc_rc:
   case misc_rs:
      EV5_MiscReadClearSet(P,rdestp,func==misc_rs);
      return SUCCESS;
#endif
   case misc_rpcc: 
   {
      *rdestp = CPUVec.CycleCount(P->myNum);
      break;
   }
   default:
   CPUWarning("Misc opcode at pc=0x%lx func=%x \n",P->PC,func);
   NOTREACHED();
   }
   return 0;
}


static inline int FetchInstruction(AlphaState *P,union alpha_instruction *inst)
{
   MA instrMAddr;
   PA pAddr;
   MMUStatus status;

   /*
    * PALCode: fetched from physical memory
    */

   if (IS_PAL(P)) {
      pAddr =  P->PC & ~0x3;
      instrMAddr = PHYS_TO_MEMADDR(P->myNum,pAddr);
      P->instr = *inst = *(union alpha_instruction *)instrMAddr;
      STATS_INC(P->myNum, iReads, 1);
      return 1;
   } 

   /*
    * Fast access
    */
   instrMAddr = QCLookup(P->curIQC,P->PC,0);
   if (instrMAddr) { 
      P->instr = *inst = *(union alpha_instruction *)instrMAddr;
      STATS_INC(P->myNum, iReads, 1);
      return 1;
   }

   /*
    * Fall-back case 
    */

   pAddr = 0;
   status = EV5_ITranslateVirtual(P,&pAddr,1);
   if (status==MMU_SUCCESS) { 
      instrMAddr = PHYS_TO_MEMADDR(P->myNum,pAddr);     
      P->instr = *inst = *(union alpha_instruction *)instrMAddr;
      STATS_INC(P->myNum, iReads, 1);
      return 1;
   }
   ASSERT( status == MMU_EXCEPTION);
   return 0;
}


static  void DecodeExecuteCommitCycle(AlphaState *P, union alpha_instruction instr) 
{

   Reg rav,rbv;
   Reg *raPtr,*rcPtr;
   int ra,rb;
   int opcode,ret;
   int  disp;
   MMUStatus mmuStatus = MMU_SUCCESS;
   Reg oldPC = P->PC;

   opcode = instr.common.opcode;
   switch (opcode) {
   case op_call_pal:
      ASSERT( instr.pal_format.function); /* no halt */
      EV5_PALOpcode(P,instr.pal_format.function);
      break;
   case op_lda: 
   case op_ldah: 
      rbv = P->reg[instr.m_format.rb];
      disp = instr.m_format.memory_displacement;
      raPtr = &P->reg[instr.m_format.ra];
      if (opcode == op_lda) { 
         *raPtr = rbv + disp;
      } else {
         *raPtr = rbv + (disp<<16);
      }
      P->PC += 4;
      break;

   case op_ldq_u:
#ifdef op_ldbu
   case op_ldbu:
   case op_ldwu:
#endif
   case op_ldl:
   case op_ldq:
   case op_ldl_l:
   case op_ldq_l:
      rbv = P->reg[instr.m_format.rb];
      disp = instr.m_format.memory_displacement;
      raPtr = &P->reg[ZERO_REDIRECT(instr.m_format.ra)];
      EXTERNAL_TRACE_SET_VEA(P, rbv+disp);
      ret = GammaMemoryReadOpcode(opcode,raPtr,rbv+disp);
      if (!ret) { 
         P->PC += 4;
      } else {
	mmuStatus = MMU_EXCEPTION;
      }
      break;
   case op_ldf:
   case op_ldg:
   case op_lds:
   case op_ldt:
     EXTERNAL_TRACE_SET_VEA(P, P->reg[instr.m_format.rb] + instr.m_format.memory_displacement);
     if (!FPENABLED(P)) {
        EV5_Trap(P, TRAP_FEN);
        mmuStatus = MMU_EXCEPTION;
     } else {
        rbv = P->reg[instr.m_format.rb];
        disp = instr.m_format.memory_displacement;
        raPtr = (Reg*)&P->fp[ZERO_REDIRECT(instr.m_format.ra)];
       ret = GammaMemoryReadOpcode(opcode,raPtr,rbv+disp);
       if (!ret) { 
          P->PC += 4;
       } else {
          mmuStatus = MMU_EXCEPTION;
       }
     } break;
   case op_stq_u:
#ifdef op_stb
   case op_stb:
   case op_stw:
#endif
   case op_stl:
   case op_stq:
   case op_stl_c:
   case op_stq_c:
      rbv = P->reg[instr.m_format.rb];
      disp = instr.m_format.memory_displacement;
      raPtr = &P->reg[instr.m_format.ra];
      EXTERNAL_TRACE_SET_VEA(P, rbv+disp);
      ret = GammaMemoryWriteOpcode(opcode, &P->reg[ZERO_REDIRECT(instr.m_format.ra)], raPtr,rbv+disp);
      if (!ret) { 
	P->PC += 4; 
      } else {
	mmuStatus = MMU_EXCEPTION;
      }
      break;
   case op_stf:
   case op_stg:
   case op_sts:
   case op_stt:
     EXTERNAL_TRACE_SET_VEA(P, P->reg[instr.m_format.rb] + instr.m_format.memory_displacement);
     if (!FPENABLED(P)) {
        EV5_Trap(P, TRAP_FEN);
        mmuStatus = MMU_EXCEPTION;
     } else {
        rbv = P->reg[instr.m_format.rb];
        disp = instr.m_format.memory_displacement;
        raPtr = (Reg*)&P->fp[instr.m_format.ra];
        ret = GammaMemoryWriteOpcode(opcode, (Reg*)&P->fp[ZERO_REDIRECT(instr.m_format.ra)], raPtr,rbv+disp);
        if (!ret) { 
           P->PC += 4; 
       } else {
          mmuStatus = MMU_EXCEPTION;
       }
     } break;
   case op_fbeq:
   case op_fblt:
   case op_fble:
   case op_fbne:
   case op_fbge:
   case op_fbgt:
     if (!FPENABLED(P)) {
        EV5_Trap(P, TRAP_FEN);
        mmuStatus = MMU_EXCEPTION;
     } else {
        goto cbr;
     } break;
   case op_br:
   case op_bsr:
   case op_blbc:
   case op_beq:
   case op_blt:
   case op_ble:
   case op_blbs:
   case op_bne:
   case op_bge:
   case op_bgt:
   cbr: {
     ra = instr.b_format.ra;
     rav = P->reg[ra];
     if (GammaBranchOpcode(P,opcode,&P->reg[ZERO_REDIRECT(ra)],rav,P->fp[ra])) {
       TRACE_ENTRY(TRACE_BR_TAKEN,P->myNum,P->PC);
       disp = instr.b_format.branch_displacement;
       P->PC += (disp <<2)+4;
       TRACE_ENTRY(TRACE_BB,P->myNum,P->PC);
     } else {
       TRACE_ENTRY(TRACE_BR_NOTTAKEN,P->myNum,P->PC);
       P->PC = P->PC + 4;
     }	 	   
   } break;
   case op_inta:
   case op_intl:
   case op_ints:
   case op_intm:
      rav = P->reg[instr.o_format.ra];
      if (instr.o_format.form) {
         /* literal */
         rbv = instr.l_format.literal;
      } else {
         rbv = P->reg[instr.o_format.rb];
      }
      rcPtr = &P->reg[ZERO_REDIRECT(instr.o_format.rc)];
      ret = GammaOperateOpcode(P, 
			       opcode*(1<<7)+instr.o_format.function,
			       rav,rbv,rcPtr,&P->reg[ZERO_REDIRECT(instr.o_format.rc)]);
      P->PC +=4;
      break;
   case op_opc14:
   case op_fltv:
   case op_flti:
   case op_fltl:
      if (!FPENABLED(P)) {
         EV5_Trap(P, TRAP_FEN);
         mmuStatus = MMU_EXCEPTION;
      } else {
         double *pra = 
            (opcode == op_opc14)
            ? (double*)&P->reg[instr.f_format.fa]
            : &P->fp[instr.f_format.fa];
	GammaFloatingOpcode(P,opcode,instr.f_format.function,
			    pra,
			    &P->fp[instr.f_format.fb],
			    &P->fp[instr.f_format.fc],
			    &P->fp[ZERO_REDIRECT(instr.f_format.fc)]);
        
        P->PC +=4;
      } break;
      
   case op_jsr:
   { 
      /*
       * XXX be really careful of case when ra==rb
       * XXX AXP manual page 4-21
       */
      VA savedPC = P->PC+4;
      ra = instr.j_format.ra;
      rb = instr.j_format.rb;
      ASSERT (((P->reg[rb]&3)==0) || IS_PAL(P));
      TRACE_ENTRY(TRACE_JSR,P->myNum,P->PC);
      if IS_PAL(P) {
         P->PC = (P->reg[rb] & ~0x3) | 0x1;
      } else {
         P->PC = (P->reg[rb] & ~0x3);
      }
      P->reg[ZERO_REDIRECT(ra)] = savedPC;
      TRACE_ENTRY(TRACE_BB,P->myNum,P->PC);
      break;
   }
   case op_misc:
      GammaMiscOpcode(P,instr.word,&P->reg[ZERO_REDIRECT(instr.m_format.ra)]);
      P->PC +=4;
      break;

   case PRIV_OP_MTPR:
   {
      int priv = instr.m_format.memory_displacement;
      ra = instr.m_format.ra;
      EV5_MoveToPriv(P,priv,P->reg[ra]);
      P->PC +=4;
      break;
   }
   case PRIV_OP_MFPR:
   {
      int priv = instr.m_format.memory_displacement;
      ra = instr.m_format.ra;
      P->reg[ZERO_REDIRECT(ra)] = EV5_MoveFromPriv(P,priv);
      P->PC +=4;
      break;
   }
   case PRIV_OP_HW_LD: 
   {
      PA pAddr = 0;
      VA align;
      int size=0;
      MA mA;
      ev5_hwldst_format hwldst = ( ev5_hwldst_format)instr.word;
      Reg *regPtr = &P->reg[ZERO_REDIRECT(instr.m_format.ra)];
      int rb = instr.m_format.rb;
      rbv = P->reg[rb];
      mmuStatus = EV5_HW_Load(P,instr.word, rbv, &pAddr,&size);
      mA = PHYS_TO_MEMADDR(0,pAddr);
      ASSERT( size==4 || size == 8);
      switch (mmuStatus) { 
      case MMU_SUCCESS:
         ASSERT (pAddr < MEM_SIZE(0));
	 /* @@@@ maybe I should remove this later, but it seems handy */
         if        (size==4) { *regPtr = *(int32*)mA;  
         } else if (size==8) { *regPtr = *(int64*)mA;
         } 
	 CHECK_LD_ANN(rbv+hwldst.hwmem_format.disp, pAddr);
         P->PC +=4;
         break;
      case MMU_LL:
         ASSERT (pAddr < MEM_SIZE(0));
         align = pAddr & ~(VA)(CACHE_LINE_SIZE-1);
	 /* @@@@ maybe I should remove this later, but it seems handy */
         if        (size==4) { *regPtr = *(int32*)mA;  
         } else if (size==8) { *regPtr = *(int64*)mA;
         } 
	 CHECK_LD_ANN(rbv+hwldst.hwmem_format.disp, pAddr);
         P->PC +=4;
         curPE->lock_flag = 1;
         curPE->locked_addr = align;
#if 0
         CPUWarning("HWLD(LL) called: pAddr 0x%x\n", pAddr);
#endif
         numLLActive++;
         break;
      case MMU_UNCACHED:
         if (size==4) {  
            mmuStatus = GammaUncachedOperation((pAddr&PA_MASK)|K1BASE,BDOOR_LOAD_WORD,regPtr);
         } else {
            mmuStatus = GammaUncachedOperation((pAddr&PA_MASK)|K1BASE,BDOOR_LOAD_DOUBLE,regPtr);
         }
         if (mmuStatus==MMU_SUCCESS) { P->PC += 4; 
         } else {
            ASSERT (mmuStatus==MMU_EXCEPTION);
         }
         break;
      case MMU_EXCEPTION:
         break;
      default: NOTREACHED();
      }
      if (gammaParams.debugLoadStore || (rbv + hwldst.hwmem_format.disp == alphaDebugParams.debugVATranslation))
	CPUWarning("PRIV_OP_HW_LD: pc=%lx val=%lx r%d=%lx vaddr=%lx paddr=%lx maddr=%lx status=%d cycle=%ld\n",
		   P->PC, *regPtr, rb, rbv, rbv + hwldst.hwmem_format.disp, pAddr, mA, mmuStatus, gammaCurrentTime[P->myNum]);
      break;
   }
   case PRIV_OP_HW_ST: 
   {
      PA pAddr=0;
      int size=0;
      VA align;
      MA mA;
      ev5_hwldst_format hwldst = ( ev5_hwldst_format)instr.word;
      Reg *regPtr = &P->reg[instr.m_format.ra]; /* source operand, so no ZERO_REDIRECT */
      Reg *targetRegPtr = &P->reg[ZERO_REDIRECT(instr.m_format.ra)];
      rbv = P->reg[instr.m_format.rb];
      mmuStatus = EV5_HW_Store(P,instr.word,rbv,&pAddr,&size);
      mA = PHYS_TO_MEMADDR(0,pAddr);
      ASSERT( size==4 || size == 8);
      if (gammaParams.debugLoadStore || (rbv + hwldst.hwmem_format.disp == alphaDebugParams.debugVATranslation))
	CPUWarning("PRIV_OP_HW_ST: pc=%lx val=%lx vaddr=%lx paddr=%lx maddr=%lx status=%d cycle=%ld\n",
		   P->PC, *regPtr, rbv + hwldst.hwmem_format.disp, pAddr, mA, mmuStatus, gammaCurrentTime[P->myNum]);
      switch (mmuStatus) { 
      case MMU_SUCCESS:
         if (pAddr>MEM_SIZE(0)) { 
            CPUError("hw_st: pAddr=0x%lx memory ref too large \n",pAddr);
         }
         if        (size==4) { *(int32*)mA = *regPtr;
         } else if (size==8) { *(int64*)mA = *regPtr;
         } 
	 /* @@@@ maybe I should remove this later, but it seems handy */
	 CHECK_ST_ANN(rbv+hwldst.hwmem_format.disp, pAddr);
         P->PC +=4;
         break;
      case MMU_SC:
         if (pAddr>MEM_SIZE(0)) { 
            CPUError("hw_st: pAddr=0x%lx memory ref too large \n",pAddr);
         }
         align = pAddr & ~(VA)(CACHE_LINE_SIZE-1);
         if (curPE->lock_flag && curPE->locked_addr==align) { 
            if        (size==4) { *(int32*)mA = *regPtr;
            } else if (size==8) { *(int64*)mA = *regPtr;
            } 
            *targetRegPtr = 1;
#if 0
            CPUWarning("HWST(SC) succeeded: pAddr 0x%x\n", pAddr);
#endif
            /* @@@@ maybe I should remove this later, but it seems handy */
            CHECK_ST_ANN(rbv+hwldst.hwmem_format.disp, pAddr);
         } else {
            *targetRegPtr = 0;
#if 0
            CPUWarning("HWST(SC) failed: pAddr 0x%x\n", pAddr);
#endif
         }
         P->PC +=4;
         break;
      case MMU_UNCACHED:
         if (size==4) {  
            mmuStatus = GammaUncachedOperation((pAddr&PA_MASK)|K1BASE,BDOOR_STORE_WORD,regPtr);
         } else {
            mmuStatus = GammaUncachedOperation((pAddr&PA_MASK)|K1BASE,BDOOR_STORE_DOUBLE,regPtr);
         }
         if (mmuStatus==MMU_SUCCESS) { 
            P->PC += 4; 
         } else {
            ASSERT (mmuStatus==MMU_EXCEPTION);
         }
         break;
      case MMU_EXCEPTION:
         break;
      default: NOTREACHED();
      }

      if (numLLActive) {
         int i;
         align = (VA)pAddr & ~(VA)(CACHE_LINE_SIZE-1);
         for (i=0;i<numCPUs;i++) {
            if (Pindex==i) continue;
            if (PE[i]->lock_flag && PE[i]->locked_addr == align) { 
               PE[i]->locked_addr = 0;
               PE[i]->lock_flag = 0;
               numLLActive--;
               ASSERT(numLLActive>=0);
            }
         }
         if (curPE->lock_flag) {
            curPE->lock_flag = 0;
            numLLActive--;
            ASSERT(numLLActive>=0);
         }
      }
      break;
   }
     
   case PRIV_OP_REI:
      EV5_HwRei(P);
      break;

   default:
      ASSERT (0);
   } /* switch(opcode) */
   if (mmuStatus == MMU_SUCCESS) {
#if defined(GAMMA_PRINT_INSTRUCTIONS) && !defined(PRINT_INSTRUCTION_ON_FETCH)
     { 
       Reg pc = P->PC;
       curPE->PC = oldPC;
       PRINT_INSTRUCTION(curPE,instr.word);
       curPE->PC = pc;
     }
#endif

     STATS_INC(P->myNum, numInstructions, 1);
     EXTERNAL_TRACE_INSTRUCTION(P, oldPC, instr.word);
#ifdef WAY_TOO_EXPENSIVE
     AlphaCommitAnnExec();
#endif
   }
}


/* **************************************************************
 * Main loop for Gamma
 * **************************************************************/
   
static void GammaCPURun(void)
{
   union alpha_instruction instr;
   uint i;

   ASSERT(MP_SIM_CYCLE_GRAIN > 0);

   while(1) {
     
    /*
     * Bookkeeping, event handling
     */
    Pindex++;
    curPE = PE[Pindex];
    if (!curPE) {
        Pindex = 0;
        curPE = PE[0];
    }

    for (i=0; i < MP_SIM_CYCLE_GRAIN; i++) {

      gammaCurrentTime[Pindex]++;
      EventPollSingleQueue(gammaCurrentTime[Pindex]);

      if (curPE->cpuState != cpu_running) {
          break;
      }
      EXTERNAL_TRACE_PE(curPE);

      /*
       * Single-stepping debugger
       */
      if (gamma_debug_mode) {
         if ((curPE->myNum == gamma_break_nexti) 
             || (gamma_break_nexti == GAMMA_BREAKANYCPU)) {
            /* GammaDebug returns nonzero if the PC has changed */
            /* or the contents of it have been overwritten, so it */
            /* needs to be reloaded. */
            GammaDebug(curPE->myNum, 1);
         } else if (gamma_sigusr) {
            gamma_debug_mode = 0;
            gamma_sigusr = 0;
            AnnExec(AnnFind("simos", "sigusr"));
         }
      }

      /*
       * Fetch-Decode-Execute
       */
      if (FetchInstruction(curPE,&instr)) {
         VA oldPC = curPE->PC;
#ifdef PRINT_INSTRUCTION_ON_FETCH
         PRINT_INSTRUCTION(curPE,instr.word);
#endif
         DecodeExecuteCommitCycle(curPE,instr);
         RUN_PC_ANNOTATIONS(oldPC,curPE->PC);       
      }
    } /* for (i=0..MP_SIM_CYCLE_GRAIN) */
   } /* while (1) */
}

/* *********************************************************************
 * DeltaLoop for PALcode execution
 * *********************************************************************/

void DeltaGammaRun(AlphaState *P) 
{
   union alpha_instruction inst;
   
   /*
    * The first instruction does NOT have to be PALcode, 
    * but can generate an ITB exception
    */
   if (!FetchInstruction(P,&inst)) {
      inst = *(union alpha_instruction *)PHYS_TO_MEMADDR(M_FROM_CPU(P->myNum),(P->PC & ~0x3));
   }
   
   while(1) { 
      VA oldPC = P->PC;
      DecodeExecuteCommitCycle(P,inst);

      RUN_PC_ANNOTATIONS(oldPC,P->PC);       


      P->cycleCountDown--;
      if (!IS_PAL(P)) break;
      /*
       * We are in PALcode. Loading the PC is easy
       */
      inst = *(union alpha_instruction *)PHYS_TO_MEMADDR(M_FROM_CPU(P->myNum),(P->PC & ~0x3));
      
   };
}

static void DoneRunning(void)
{
  CPUWarning("Exiting the simulator \n");
  AnnExec(AnnFind("simos", "exit"));
}
 

SimTime
GammaCycleCount(int cpuNum) 
{
   return gammaCurrentTime[cpuNum];
}



void GammaStall(AlphaState *P, CPUStatus state)
{
   ASSERT( state != cpu_running);
   P->cpuState = state;
   if (0) CPUWarning("GAMMA: stalling %d for %d \n",Pindex,state);
}

void GammaUnstall(int cpuNum)
{
   AlphaState *P = PE[cpuNum];
   P->cpuState = cpu_running;
   if (0) CPUWarning("GAMMA: unstalling %d\n",Pindex);
}


static char *LLAddrAccess(ClientData clientData, Tcl_Interp *interp,
			  char *name1, char *name2, int flags)
{
  int cpunum;
  Tcl_GetInt(interp, name2, &cpunum);
  if (flags & TCL_TRACE_READS) {
    char buf[32];
    if (0)
    fprintf(stderr, "LLAddrAccess: cpunum=%s(%d) flag=%d addr=%lx\n",
	    name2, cpunum, PE[cpunum]->lock_flag, PE[cpunum]->locked_addr);
    if (PE[cpunum]->lock_flag)
      sprintf(buf, "%lx", PE[cpunum]->locked_addr);
    else
      sprintf(buf, "0");
    Tcl_SetVar2(interp, name1, name2, buf, 0);
  } else {
    Tcl_SetVar2(interp, name1, name2, "0", 0);
  }
  return NULL;
}

void GammaTclInit(Tcl_Interp *interp)
{
   ParamRegister("PARAM(CPU.Gamma.Debug.LoadStore)", (char *)&gammaParams.debugLoadStore, PARAM_INT);
   ParamRegister("PARAM(CPU.Gamma.RecognizePrefetches)", (char *)&gammaParams.recognizePrefetches, PARAM_INT);
   Tcl_TraceVar(interp, "LLAddr", TCL_TRACE_READS|TCL_TRACE_WRITES|TCL_GLOBAL_ONLY, 
		LLAddrAccess,
		(ClientData)NULL);
#if 0
   Tcl_CreateCommand(interp, "verboseDebug", InterpretVerboseDebug,
                     (char *)NULL, (Tcl_CmdDeleteProc*)NULL);
#endif
}

SimTime
GammaInstructionCount(int cpuNum)
{
  return STATS_VALUE(cpuNum, numInstructions);
}

char *GammaStats(void)
{
   return "";
}

void GammaExitSimulator( CPUType toSim )
{
  longjmp(jmpEnv, toSim);
}

int GammaCheckFPEnabled(AlphaState *P)
{
   return FPENABLED(P);
}