/*
 * Copyright (C) 1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * Copyright (C) 1998 Digital Equipment Corporation
 *
 * This file is part of the SimOS distribution.
 * See LICENSE file for terms of the license.
 *
 */



/* ******************************************************
 * cached-gamma.c
 *
 * main fetch/decode/execute loop for the gamma instruction
 * set interpreter. To be integrated into SimOS. 
 * ******************************************************/

#include <setjmp.h>
#include <alpha/inst.h>

#include "simtypes.h"
#include "sim_error.h"
#include "registry.h"
#include "machine_params.h"
#include "params.h"

#include "gamma.h"
#include "kappa.h"
#include "ev5.h"
#include "ev5_ipr.h"
#include "disassembler.h"
#include "alpha_regs.h"
#include "alpha_params.h"
#include "alpha_trace.h"
#include "ipr_decode.h"
#include "memref.h"
#include "alpha_memref.h"
#include "hw_events.h"

#include "tcl_init.h"
#include "print_insts.h"
#include "cpu_stats.h"
#include "cpu_interface.h"
#include "stats.h"
#include "qc.h"

#include "external_trace.h"

typedef int (*MagicFunction)(int   cpuNum, /* CPU making this access */
			     VA   va,     /* accessed virtual address */
			     int   type,   /* access type */
			     void* buff);  /* buff width acc to type */


#define CACHE_LINE_SIZE 64 /* elsewhere XXX */

/* ********************************************
 * globals
 * ********************************************/
/* The instruction formats corresponding to the opcodes of instructions */



extern int Pindex;
extern AlphaState *curPE;
extern int numCPUs;
extern int64 gammaCurrentTime[SIM_MAXCPUS];
extern jmp_buf     jmpEnv;                    /* Used to exit the main loop */
extern int numLLActive;

extern GammaParams gammaParams;

extern uint gdbInstr;
extern uint gdbInstrCommon;
static int prePCAnnsExist;

static void KappaCPURun(void);
static void KappaDoneRunning(void);
extern char * GammaStats(void);

extern int gamma_debug_mode;
extern int gamma_break_nexti;
extern int gamma_sigusr;


/*****************************************************************
 * ANNOTATION SUPPORT!
 *****************************************************************/
#define CHECK_LD_ANN(_vAddr, _pAddr) \
{  if (annLoads) {        \
      AnnPtr ptr = AnnFMLookup(_vAddr, ANNFM_LD_TYPE);\
      if (ptr)         \
         AnnExec(ptr); \
      ptr = AnnFMLookup(_pAddr, ANNFM_LD_TYPE);\
      if (ptr)         \
         AnnExec(ptr); \
   }                         \
}

#define CHECK_ST_ANN(_vAddr,_pAddr) \
{ if (annStores) {         \
      AnnPtr ptr = AnnFMLookup(_vAddr, ANNFM_ST_TYPE);\
      if (ptr)         \
         AnnExec(ptr); \
      ptr = AnnFMLookup(_pAddr, ANNFM_ST_TYPE);\
      if (ptr)         \
         AnnExec(ptr); \
 }                         \
}


/* ************************************************
 * main entry point
 * ************************************************/

void ExecuteKappa(void)
{
  int i;

  /*
   * setup original arguments
   */
  GammaInitTables();
  GammaCPUVectorInit();
  KappaCPUVectorInit();

  /*
   * KAPPA currently broken for direct-mapped L2 caches with
   * inclusion on I-$
   */

  ASSERT( SCACHE_ASSOC > 1  || !ICACHE_INCLUSION);


  if (!alphaLateInitDone) {
     /*
      * Stuff that needs late initalization.
      * XXX should use a register mechanism
      */

     GammaInitStats();
     AnnCommonSetup();
     AnnFMInit(128);
     InstallPoller();  /* devices */
     prePCAnnsExist = AnnFMTypesExist(ANNFM_PRE_PC_TYPE);
     InitSimulatorStats(4*1024*1024, GammaStats);
     HWEventsLateInit();
     /*
      * simos enter annotation
      */
     {
        int cpu;
        for (cpu=0;cpu<TOTAL_CPUS;cpu++) {
           curPE = PE[cpu];
           AnnExec(AnnFind("simos","enter"));
        }
        curPE = PE[0];
     }

     for (i=0; i < SIM_MAXCPUS; i++)
        gammaCurrentTime[i] = -1;
     alphaLateInitDone = 1;
  }

  curPE = PE[0];
  Pindex = 0;
  curPE->cpuState = cpu_running;
  numCPUs = NUM_CPUS(0);
  EXTERNAL_TRACE_PE(curPE);

  CPUWarning("P->PC entry = 0x%lx \n",curPE->PC);

  GammaFPInit(); /* installs SIGFPE handler */

  {
     int toCPUType = NO_CPU;
     if ((toCPUType = setjmp(jmpEnv)) != 0) {
        if (gammaArithTrap) {
           gammaArithTrap = 0;
           KappaCPURun();
        } else {
           KappaDoneRunning();
           simosCPUType = toCPUType;
        }
     } else {
        KappaCPURun();
     } 
  }
  GammaDumpAllStats();

}


Result KappaUncachedOperation(VA  vAddr, int type, void *data)
{
   AlphaState *P = curPE;
   void *func;
   int flag;
   Result result;

   if (!RegistryIsInRange(vAddr, &func, &flag)) {
      CPUError("UNCACHED OPERATION at vAddr=0x%lx pc=0x%lx val=0x%lx \n",
	       vAddr,P->PC,P->reg[REG_RA]);
   }
   if (!(flag & REG_FUNC)) { 
      CPUError("GammUncached op at va 0x%lx pc 0x%lx val=0x%lx\n",
	       vAddr,P->PC,P->reg[REG_RA]);
   }
   ASSERT(flag & REG_FUNC);
   result = (Result)((MagicFunction)func)(P->myNum, vAddr, type, data); 
   if (gammaParams.debugLoadStore || vAddr == alphaDebugParams.debugVATranslation)
     CPUWarning("KappaUncachedOperation: func=%p va=%lx type=%d data=%lx\n", func, vAddr, type, *(long*)data);
   switch (type) {
   case BDOOR_LOAD_BYTE:
   case BDOOR_LOAD_HALF:
   case BDOOR_LOAD_WORD:
   case BDOOR_LOAD_DOUBLE:
     CHECK_LD_ANN(vAddr, vAddr);
     break;
   case BDOOR_STORE_BYTE:
   case BDOOR_STORE_HALF:
   case BDOOR_STORE_WORD:
   case BDOOR_STORE_DOUBLE:
     CHECK_ST_ANN(vAddr, vAddr);
     break;
   default:
     CPUWarning("@@@ KappaUncachedOperation: type=%d\n", type);
   }
   return result;
}


static int poison = 0;
int KappaMemoryReadOpcode(int opcode,Reg *raPtr, Reg vAddr)
{
   AlphaState *P = curPE;
   MA mAddr=0;
   PA pAddr=0;
   RefSize refSize = alphaRefSizeMap[opcode];
   RefFlavor refFlavor = alphaRefFlavorMap[opcode];
   Reg data = 0;
   MMUStatus status;
   mAddr = QCLookup(curPE->curDQC,vAddr,0);
   if (mAddr) {
      status = MMU_SUCCESS;
      pAddr=MEMADDR_TO_PHYS(M_FROM_CPU(curPE->myNum),mAddr);
      if ((int)vAddr == (int)alphaDebugParams.debugVATranslation) {
	CPUWarning("KappaMemoryReadOpcode: -QCLookup- va=%lx pa=%lx\n",
		   vAddr, pAddr);
      }
   } else {
      status =EV5_DTranslateVirtual(curPE,vAddr,0,1,&pAddr);
      mAddr = PHYS_TO_MEMADDR(0,pAddr);
   }
   if (status == MMU_SUCCESS) {
      if (pAddr >= MEM_SIZE(0)) {
	 CPUError("KappaMemoryReadOpcode vA=0x%lx pA=0x%lx pc=0x%lx val=0x%lx\n",
		  vAddr,pAddr,P->PC, P->reg[REG_RA]);
      }
      ASSERT( pAddr < MEM_SIZE(0));
      {
	int ret;
	VA vAddr1 = vAddr;
	PA pAddr1 = pAddr;

	if (opcode == op_ldq_u) {
	  vAddr1 &= ~7L;
	  pAddr1 &= ~7L;
	}
	if (opcode == op_ldl_l || opcode == op_ldq_l) {
	   ASSERT(alphaRefFlavorMap[opcode] == LL_FLAVOR);
	}

	ret = MemRefReadData(P->myNum, vAddr1, pAddr1, &data, refSize, refFlavor);
	if (ret != SUCCESS) { 
	  if ((ret == STALL) || (ret == FAILURE) || (ret == SCFAILURE)) {
	    poison = 1;
	    P->cpuState = cpu_stalled;
	    return ret;
	  } else if (ret == BUSERROR) {
	    NOTREACHED();
	    return ret;
	  } else {
	    CPUWarning("Bad return value (%d) from MemRefReadData\n", ret);
	  }
	} else {
	  /* We hit in the DCACHE */
	  /* so we're done */
	  
	}
      }
      CHECK_LD_ANN(vAddr,pAddr);
      STATS_INC(P->myNum, dReads, 1);
      TRACE_ENTRY(TRACE_LOAD,curPE->myNum,vAddr);

      gammaMemoryTable[opcode](raPtr, NULL,(Reg*)mAddr, pAddr, vAddr);

      if (gammaParams.debugLoadStore || vAddr == alphaDebugParams.debugVATranslation)
         CPUWarning("KappaMemoryReadOpcode: pc=%lx val=%016lx vaddr=%lx paddr=%lx maddr=%lx, status=%d cycle=%ld\n",
                    P->PC, *raPtr, vAddr, pAddr, mAddr, status, gammaCurrentTime[P->myNum]);
      return 0;
   } else if (status == MMU_EXCEPTION) { 
      DTLB_MISS_EVENT(gammaCurrentTime[P->myNum], P->myNum, P->PC, vAddr);
      return 1;
   } else {
      ASSERT( status==MMU_UNCACHED);
      status = KappaUncachedOperation(vAddr,BDOOR_LOAD_WORD,raPtr);
      if (gammaParams.debugLoadStore || vAddr == alphaDebugParams.debugVATranslation)
	CPUWarning("KappaMemoryReadOpcodeUncached: pc=%lx val=%016lx vaddr=%lx paddr=%lx maddr=%lx status=%d cycle=%ld\n",
		   P->PC, *raPtr, vAddr, pAddr, mAddr, status, gammaCurrentTime[P->myNum]);

      if (status==MMU_SUCCESS) return 0;
      if (status==MMU_EXCEPTION) return 1;
      NOTREACHED();
      return 0;
   }
}


int KappaMemoryWriteOpcode(int opcode, Reg *rdestp, const Reg *raPtr, Reg vAddr) 
{
  AlphaState *P = curPE;
  int cpu = P->myNum;
  MA mAddr=0;
  PA pAddr=0;
  RefSize refSize = alphaRefSizeMap[opcode];
  RefFlavor refFlavor = alphaRefFlavorMap[opcode];
  Reg data = 0;
  MMUStatus status;
  mAddr = QCLookup(curPE->curDQC,vAddr,1);

  if (mAddr) {
    status = MMU_SUCCESS;
    pAddr=MEMADDR_TO_PHYS(M_FROM_CPU(curPE->myNum),mAddr);
    if ((int)vAddr == (int)alphaDebugParams.debugVATranslation) {
      CPUWarning("KappaMemoryWriteOpcode: -QCLookup- va=%lx pa=%lx\n",
		 vAddr, pAddr);
    }
  } else {
    status =EV5_DTranslateVirtual(curPE,vAddr,1,1,&pAddr);
    mAddr = PHYS_TO_MEMADDR(0,pAddr);
  }

  if (status==MMU_SUCCESS) { 
    Reg tdest;
    if (pAddr >= MEM_SIZE(0)) {
      CPUError("KappaMemoryWriteOpcode vA=0x%lx pA=0x%lx pc=0x%lx val=0x%lx\n",
	       vAddr,pAddr,P->PC, P->reg[REG_RA]);
    } 
    ASSERT (mAddr);

    if (refFlavor == SC_FLAVOR) {
       if (!P->lock_flag || (P->locked_addr != ((VA)pAddr & ~(VA)(CACHE_LINE_SIZE-1)))) {
          *rdestp = 0;
          return SUCCESS; /* SCFAILURE not visible to CPU */
       }
    }

    {
      int ret;

      if (opcode == op_stq_u) {
	vAddr &= ~7L;
	pAddr &= ~7L;
      }
      ret = MemRefWriteData(P->myNum, vAddr, pAddr, data, refSize, refFlavor);
      switch(ret) {
      case SUCCESS:
         gammaMemoryTable[opcode](&tdest, raPtr,(Reg*)mAddr,pAddr,vAddr);
         CHECK_ST_ANN(vAddr,pAddr);
         STATS_INC(P->myNum, dWrites, 1);
         if (opcode == op_stq_c || opcode == op_stl_c) {
            ASSERT(tdest == curPE->lock_flag);
            ASSERT(tdest == 1);
            ASSERT(alphaRefFlavorMap[opcode] == SC_FLAVOR);
            *rdestp = 1;
         }
         if (numLLActive) {
            VA align = (VA)pAddr & ~(VA)(CACHE_LINE_SIZE-1);
            int i;
            for (i=0;i<numCPUs;i++) {
               if (cpu==i) continue;
               if (PE[i]->lock_flag && PE[i]->locked_addr == align) { 
                  CPUPrint("cpu %d shot down lock that memref missed for paddr=%lx cpu=%d lockaddr=%lx\n",
                           cpu, pAddr, i, PE[i]->locked_addr);
                  PE[i]->locked_addr = 0;
                  PE[i]->lock_flag = 0;
                  numLLActive--;
                  ASSERT(numLLActive>=0);
               }
            }
            if (P->lock_flag) {
               P->lock_flag = 0;
               numLLActive--;
               ASSERT(numLLActive>=0);
            }
         }
         return SUCCESS;

      case SCFAILURE:
         *rdestp =0;
         return SUCCESS; /*SC failure does not stall the processor */
         return ret;

      case STALL: 
      case FAILURE:
         P->cpuState = cpu_stalled;
         return ret;
         
      default: NOTREACHED();

      }
     
    } 
    NOTREACHED();
    return 0;
  } else if (status==MMU_EXCEPTION) {
     DTLB_MISS_EVENT(gammaCurrentTime[P->myNum], P->myNum, P->PC, vAddr);
     return 1;
  } else  {
     ASSERT( status==MMU_UNCACHED);
     /*
      * XXX bugnion 
      * should be either _WORD or _DOUBLE !!!!
      */
     status = KappaUncachedOperation(vAddr,BDOOR_STORE_WORD,(void *)raPtr);
     if (gammaParams.debugLoadStore || vAddr == alphaDebugParams.debugVATranslation)
        CPUWarning("KappaMemoryWriteOpcodeUncached: pc=%lx val=%016lx vaddr=%lx paddr=%lx maddr=%lx status=%d cycle=%ld\n",
                   P->PC, *raPtr, vAddr, pAddr, mAddr, status, gammaCurrentTime[P->myNum]);
     if (status==MMU_SUCCESS) return 0;
     if (status==MMU_EXCEPTION) return 1;
     NOTREACHED();
    return 0;
  }
  
}

int KappaMiscOpcode(AlphaState *P, uint instr, Reg *rdestp)
{
   uint func = instr & 0xffff;
#if 0
CPUWarning("KappaMiscOpcode: pc=%lx cycle=%ld\n",
	   P->PC, gammaCurrentTime[P->myNum]);
#endif
   switch(func) {
   case misc_trapb:
   case misc_excb:
   case misc_mb: 
   case misc_wmb: 
   case misc_fetch: 
   case misc_fetch_m: 
#ifdef misc_wh64
   case misc_wh64: 
#endif
      return SUCCESS;
#ifndef SOLO
   case misc_rc:
   case misc_rs:
      EV5_MiscReadClearSet(P,rdestp,func==misc_rs);
      return SUCCESS;
#endif
   case misc_rpcc: 
   {
      *rdestp = CPUVec.CycleCount(P->myNum);
      break;
   }
   default:
   CPUWarning("Misc opcode at pc=0x%lx func=%x \n",P->PC,func);
   NOTREACHED();
   }
   return 0;
}



/*
 * !!! should go to memref in all cases, as soon as
 * we have a phys
 */


static inline int FetchInstruction(AlphaState *P,union alpha_instruction *inst)
{
  int cpu = P->myNum;
  MA instrMAddr = 0;
  VA vAddr = P->PC;
  PA pAddr = 0;

  ASSERT(P->PC); /* not strickly necesssar. */

  /*
   * PALCode: fetched from physical memory
   */

  if (IS_PAL(P)) {
    pAddr =  P->PC & ~0x3;
    instrMAddr = PHYS_TO_MEMADDR(cpu,pAddr);
  } else if ((instrMAddr = QCLookup(P->curIQC,P->PC,0)) != NULL) {
    /*
     * Fast access
     */
    pAddr = MEMADDR_TO_PHYS(M_FROM_CPU(curPE->myNum), instrMAddr);
  } else {
    /*
     * Fall-back case 
     */

    MMUStatus status = EV5_ITranslateVirtual(P,&pAddr,1);
    if (status==MMU_SUCCESS) { 
      instrMAddr = PHYS_TO_MEMADDR(P->myNum,pAddr);     
    } else {
      ASSERT( status == MMU_EXCEPTION);
      ITLB_MISS_EVENT(gammaCurrentTime[P->myNum], P->myNum, vAddr);
      return 0;
    }
  }

  if (instrMAddr) { 
    Result result = MemRefReadInst(cpu, vAddr, pAddr, (Inst*)&P->instr);

#if DeadCode
    P->instr = *inst = *(union alpha_instruction *)instrMAddr;
#endif

    switch (result) {
    case SUCCESS: {
      *inst = P->instr;
      STATS_INC(P->myNum, iReads, 1);
      return 1;
    } break;
    case STALL: {
      P->cpuState = cpu_stalled;
      return 0;
    } break;
    case FAILURE: {
      return 0;
    } break;
    case BUSERROR:
      NOTREACHED();
      break;
    default:
      NOTREACHED();
    }
  }
  NOTREACHED();
  return 0;
}



static void DecodeExecuteCommitCycle(AlphaState *P, union alpha_instruction instr) 
{

   Reg rav,rbv;
   Reg *raPtr,*rcPtr;
   int ra,rb;
   int opcode,ret;
   int  disp;
   VA thisPC = P->PC;
   MMUStatus mmuStatus = MMU_SUCCESS;

   opcode = instr.common.opcode;
   switch (opcode) {
   case op_call_pal:
      ASSERT( instr.pal_format.function); /* no halt */
      EV5_PALOpcode(P,instr.pal_format.function);
      break;
   case op_lda: 
   case op_ldah: 
      rbv = P->reg[instr.m_format.rb];
      disp = instr.m_format.memory_displacement;
      raPtr = &P->reg[instr.m_format.ra];
      if (opcode == op_lda) { 
         *raPtr = rbv + disp;
      } else {
         *raPtr = rbv + (disp<<16);
      }
      P->PC += 4;
      break;

   case op_ldq_u:
#ifdef op_ldbu
   case op_ldbu:
   case op_ldwu:
#endif
   case op_ldl:
   case op_ldq:
   case op_ldl_l:
   case op_ldq_l:
      rbv = P->reg[instr.m_format.rb];
      disp = instr.m_format.memory_displacement;
      raPtr = &P->reg[ZERO_REDIRECT(instr.m_format.ra)];
      EXTERNAL_TRACE_SET_VEA(P, rbv+disp);
      ret = KappaMemoryReadOpcode(opcode,raPtr,rbv+disp);
      if (!ret) { 
         P->PC += 4;
      } else {
         mmuStatus = MMU_EXCEPTION;
      }
      break;
   case op_ldf:
   case op_ldg:
   case op_lds:
   case op_ldt:
      EXTERNAL_TRACE_SET_VEA(P, P->reg[instr.m_format.rb] + instr.m_format.memory_displacement);
      if (FPENABLED(P)) { 
	 rbv = P->reg[instr.m_format.rb];
	 disp = instr.m_format.memory_displacement;
	 raPtr = (Reg*)&P->fp[ZERO_REDIRECT(instr.m_format.ra)];
	 ret = KappaMemoryReadOpcode(opcode,raPtr,rbv+disp);
	 if (!ret) { 
	    P->PC += 4;
	 } else {
	    mmuStatus = MMU_EXCEPTION;
	 }
      } else {
	 EV5_Trap(P,TRAP_FEN);
	 mmuStatus = MMU_EXCEPTION;
      }
      break;

   case op_stq_u:
#ifdef op_stb
   case op_stb:
   case op_stw:
#endif
   case op_stl:
   case op_stq:
   case op_stl_c:
   case op_stq_c:
      rbv = P->reg[instr.m_format.rb];
      disp = instr.m_format.memory_displacement;
      raPtr = &P->reg[instr.m_format.ra];
      EXTERNAL_TRACE_SET_VEA(P, rbv+disp);
      ret = KappaMemoryWriteOpcode(opcode, &P->reg[ZERO_REDIRECT(instr.m_format.ra)], raPtr,rbv+disp);
      if (!ret) { 
         P->PC += 4; 
      } else {
         mmuStatus = MMU_EXCEPTION;
      }
      break;
   case op_stf:
   case op_stg:
   case op_sts:
   case op_stt:
      EXTERNAL_TRACE_SET_VEA(P, P->reg[instr.m_format.rb] + instr.m_format.memory_displacement);
      if (FPENABLED(P)) {
	 rbv = P->reg[instr.m_format.rb];
	 disp = instr.m_format.memory_displacement;
	 raPtr = (Reg*)&P->fp[instr.m_format.ra];
	 ret = KappaMemoryWriteOpcode(opcode, (Reg*)&P->fp[ZERO_REDIRECT(instr.m_format.ra)], raPtr,rbv+disp);
	 if (!ret) { 
	    P->PC += 4; 
	 } else {
	    mmuStatus = MMU_EXCEPTION;
	 }
      } else {
	 EV5_Trap(P,TRAP_FEN);
	 mmuStatus = MMU_EXCEPTION;
      }
      break;
   case op_fbeq:
   case op_fblt:
   case op_fble:
   case op_fbne:
   case op_fbge:
   case op_fbgt:
      if (FPENABLED(P)) {
	 goto cbr;
      } else {
	 EV5_Trap(P,TRAP_FEN);
	 mmuStatus = MMU_EXCEPTION;
      }
      break;

   case op_br:
   case op_bsr:
   case op_blbc:
   case op_beq:
   case op_blt:
   case op_ble:
   case op_blbs:
   case op_bne:
   case op_bge:
   case op_bgt:
 cbr: 
   ra = instr.b_format.ra;
   rav = P->reg[ra];
   if (GammaBranchOpcode(P,opcode,&P->reg[ZERO_REDIRECT(ra)],rav,P->fp[ra])) {
      TRACE_ENTRY(TRACE_BR_TAKEN,P->myNum,P->PC);
      disp = instr.b_format.branch_displacement;
      P->PC += (disp <<2)+4;
      TRACE_ENTRY(TRACE_BB,P->myNum,P->PC);
   } else {
      TRACE_ENTRY(TRACE_BR_NOTTAKEN,P->myNum,P->PC);
      P->PC = P->PC + 4;
   }	 	   
   break;
   case op_inta:
   case op_intl:
   case op_ints:
   case op_intm: {
      rav = P->reg[instr.o_format.ra];
      if (instr.o_format.form) {
         /* litteral */
         rbv = instr.l_format.literal;
      } else {
         rbv = P->reg[instr.o_format.rb];
      }
      rcPtr = &P->reg[ZERO_REDIRECT(instr.o_format.rc)];
      ret = GammaOperateOpcode(P, 
                               opcode*(1<<7)+instr.o_format.function,
                               rav,rbv,rcPtr,&P->reg[ZERO_REDIRECT(instr.o_format.rc)]);
      if (GammaFPCRIndicatesTrap(P)) {
         EV5_Trap(P, TRAP_ARITH);
      } else {
         P->PC +=4;
      }
   } break;
   case op_opc14:
   case op_fltv:
   case op_flti:
   case op_fltl:
      if (!FPENABLED(P)) {
         EV5_Trap(P, TRAP_FEN);
         mmuStatus =  MMU_EXCEPTION;
      } else {
         double *pra = 
            (opcode == op_opc14)
            ? (double*)&P->reg[instr.f_format.fa]
            : &P->fp[instr.f_format.fa];
         if (0)
            CPUWarning("FLOAT: op=%x fun=%x a=%lx b=%lx c=%lx\n",
                       opcode, instr.f_format.function,
                       *(long *)pra,
                       *(long *)&P->fp[instr.f_format.fb],
                       *(long*)&P->fp[instr.f_format.fc]);
         GammaFloatingOpcode(P,opcode,instr.f_format.function,
                             pra,
                             &P->fp[instr.f_format.fb],
                             &P->fp[instr.f_format.fc],
                             &P->fp[ZERO_REDIRECT(instr.f_format.fc)]);
         if (GammaFPCRIndicatesTrap(P)) {
            EV5_Trap(P, TRAP_ARITH);
         } else {
            P->PC +=4;
         }
      } break;

   case op_jsr:
   { 
      /*
       * XXX be really careful of case when ra==rb
       * XXX AXP manual page 4-21
       */
      VA savedPC = P->PC+4;
      ra = instr.j_format.ra;
      rb = instr.j_format.rb;
      ASSERT ((P->reg[rb]&3)==0);
      TRACE_ENTRY(TRACE_JSR,P->myNum,P->PC);
      if IS_PAL(P) {
         P->PC = P->reg[rb] | 0x1;
      } else {
         P->PC = P->reg[rb];
      }
      P->reg[ZERO_REDIRECT(ra)] = savedPC;
      TRACE_ENTRY(TRACE_BB,P->myNum,P->PC);
      break;
   }
   case op_misc:
      KappaMiscOpcode(P,instr.word,&P->reg[ZERO_REDIRECT(instr.m_format.ra)]);
      P->PC +=4;
      break;

   case PRIV_OP_MTPR:
   {
      int priv = instr.m_format.memory_displacement;
      ra = instr.m_format.ra;
      EV5_MoveToPriv(P,priv,P->reg[ra]);
      P->PC +=4;
      break;
   }
   case PRIV_OP_MFPR:
   { int priv = instr.m_format.memory_displacement;
   ra = instr.m_format.ra;
   P->reg[ZERO_REDIRECT(ra)] = EV5_MoveFromPriv(P,priv);
   P->PC +=4;
   break;
   }
   case PRIV_OP_HW_LD: 
   {
      PA pAddr = 0;
      int size=0;
      MA mA;
      ev5_hwldst_format hwldst = ( ev5_hwldst_format)instr.word;
      Reg *regPtr = &P->reg[ZERO_REDIRECT(instr.m_format.ra)];
      int rb = instr.m_format.rb;
      rbv = P->reg[rb];
      mmuStatus = EV5_HW_Load(P,instr.word, rbv, &pAddr,&size);
      mA = PHYS_TO_MEMADDR(0,pAddr);
      ASSERT( size==4 || size == 8);
      switch (mmuStatus) { 
         
      case MMU_SUCCESS:
      {
         int status;
         Reg data=0;
         ASSERT (pAddr < MEM_SIZE(0));
         status = MemRefReadData(P->myNum, pAddr & ~0x7L, pAddr & ~0x7L, &data, 
                                 (size==4?WORD_SZ:DOUBLE_SZ), NO_FLAVOR);
         if (status==SUCCESS) {
            /* @@@@ maybe I should remove this later, but it seems handy */
            if        (size==4) { *regPtr = *(int32*)mA;  
            } else if (size==8) { *regPtr = *(int64*)mA;
            } 
            CHECK_LD_ANN(pAddr,pAddr);
            STATS_INC(P->myNum, dReads, 1);
            P->PC +=4;
         } else if (status==STALL || status==FAILURE) {
            P->cpuState = cpu_stalled;
         } else {
            NOTREACHED();
         }                    
         break;
      }
      case MMU_LL:
         NOTREACHED();
         break;
      case MMU_UNCACHED:
         if (size==4) {  
            mmuStatus = KappaUncachedOperation((pAddr&PA_MASK)|K1BASE,BDOOR_LOAD_WORD,regPtr);
         } else {
            mmuStatus = KappaUncachedOperation((pAddr&PA_MASK)|K1BASE,BDOOR_LOAD_DOUBLE,regPtr);
         }
         if (mmuStatus==MMU_SUCCESS) { P->PC += 4; 
         } else {
            ASSERT (mmuStatus==MMU_EXCEPTION);
         }
         break;
      case MMU_EXCEPTION:
         break;
      default: NOTREACHED();
      }
      if (gammaParams.debugLoadStore || (rbv + hwldst.hwmem_format.disp == alphaDebugParams.debugVATranslation))
         CPUWarning("PRIV_OP_HW_LD: pc=%lx val=%lx r%d=%lx vaddr=%lx paddr=%lx maddr=%lx status=%d cycle=%ld\n",
                    P->PC, *regPtr, rb, rbv, rbv + hwldst.hwmem_format.disp, pAddr, mA, mmuStatus, gammaCurrentTime[P->myNum]);
      break;
   }
   case PRIV_OP_HW_ST: 
   {
      PA pAddr=0;
      int size=0;
      MA mA;
      ev5_hwldst_format hwldst = ( ev5_hwldst_format)instr.word;
      Reg *regPtr = &P->reg[instr.m_format.ra]; /* source operand, so no ZERO_REDIRECT */
      rbv = P->reg[instr.m_format.rb];
      mmuStatus = EV5_HW_Store(P,instr.word,rbv,&pAddr,&size);
      mA = PHYS_TO_MEMADDR(0,pAddr);
      ASSERT( size==4 || size == 8);
      if (gammaParams.debugLoadStore || (rbv + hwldst.hwmem_format.disp == alphaDebugParams.debugVATranslation))
         CPUWarning("PRIV_OP_HW_ST: pc=%lx val=%lx vaddr=%lx paddr=%lx maddr=%lx status=%d cycle=%ld\n",
                    P->PC, *regPtr, rbv + hwldst.hwmem_format.disp, pAddr, mA, mmuStatus, gammaCurrentTime[P->myNum]);
      switch (mmuStatus) { 
      case MMU_SUCCESS:
      {
         int status;
         if (pAddr>MEM_SIZE(0)) { 
            CPUError("hw_st: pAddr=0x%lx memory ref too large \n",pAddr);
         }
         status = MemRefWriteData(P->myNum, pAddr&~0x7L, pAddr&~0x7L, *regPtr,
                                  (size==4?WORD_SZ:DOUBLE_SZ), NO_FLAVOR);
         if (status == SUCCESS) {
            if        (size==4) { *(int32*)mA = *regPtr;
            } else if (size==8) { *(int64*)mA = *regPtr;
            } 
            /* @@@@ maybe I should remove this later, but it seems handy */
            CHECK_ST_ANN(rbv+hwldst.hwmem_format.disp, pAddr);
            STATS_INC(P->myNum, dWrites, 1);
            P->PC +=4;
         } else if (status==STALL || status==FAILURE) {
            P->cpuState = cpu_stalled;
         } else {
            NOTREACHED();
         }

         break;
      }
      case MMU_SC:
         NOTREACHED();
         break;
      case MMU_UNCACHED:
         if (size==4) {  
            mmuStatus = KappaUncachedOperation((pAddr&PA_MASK)|K1BASE,BDOOR_STORE_WORD,regPtr);
         } else {
            mmuStatus = KappaUncachedOperation((pAddr&PA_MASK)|K1BASE,BDOOR_STORE_DOUBLE,regPtr);
         }
         if (mmuStatus==MMU_SUCCESS) { 
            P->PC += 4; 
         } else {
            ASSERT (mmuStatus==MMU_EXCEPTION);
         }
         break;
      case MMU_EXCEPTION:
         break;
      default: NOTREACHED();
      }
      break;
   }
     
   case PRIV_OP_REI:
      EV5_HwRei(P);
      break;

   default:
      ASSERT (0);
   } /* switch(opcode) */
   if (mmuStatus == MMU_SUCCESS) {
      EXTERNAL_TRACE_INSTRUCTION(P, thisPC, instr.word);
      STATS_INC(P->myNum, numInstructions, 1);
      if (STATS_VALUE(P->myNum, numInstructions) > 
          STATS_VALUE(P->myNum, nextInstrSample)) { 
         INST_SAMPLE_EVENT(gammaCurrentTime[P->myNum], P->myNum,thisPC); 
         STATS_INC(P->myNum, nextInstrSample, MS_SAMPLE_INSTR_INTERVAL); 
      }
      AlphaCommitAnnExec();
      RUN_PC_ANNOTATIONS(thisPC, P->PC);       
   }
}


/* **************************************************************
 * Main loop for Gamma
 * **************************************************************/
   
static void KappaCPURun(void)
{
   union alpha_instruction instr;
   uint i;

   ASSERT(MP_SIM_CYCLE_GRAIN > 0);

   while(1) {
     
    /*
     * Bookkeeping, event handling
     */
    Pindex++;
    curPE = PE[Pindex];
    if (!curPE) {
        Pindex = 0;
        curPE = PE[0];
    }

    for (i=0; i < MP_SIM_CYCLE_GRAIN; i++) {

      gammaCurrentTime[Pindex]++;
      EventPollSingleQueue(gammaCurrentTime[Pindex]);

      if (curPE->cpuState != cpu_running) {
          break;
      }
      EXTERNAL_TRACE_PE(curPE);

/*
      Pindex++;
      curPE = PE[Pindex];
      if (!curPE) {
         Pindex = 0;
         curPE = PE[0];
         gammaCurrentTime++;
         EventPollSingleQueue(gammaCurrentTime);
         
      } 
      
      if (curPE->cpuState != cpu_running) {
         continue;
      }
      EXTERNAL_TRACE_PE(curPE);
*/
      
      /*
       * Single-stepping debugger
       */
      if (gamma_debug_mode) {
         if ((curPE->myNum == gamma_break_nexti) 
             || (gamma_break_nexti == GAMMA_BREAKANYCPU)) {
            /* GammaDebug returns nonzero if the PC has changed */
            /* or the contents of it have been overwritten, so it */
            /* needs to be reloaded. */
            GammaDebug(curPE->myNum, 1);
         } else if (gamma_sigusr) {
            gamma_debug_mode = 0;
            gamma_sigusr = 0;
            AnnExec(AnnFind("simos", "sigusr"));
         }
      }

      /*
       * Fetch-Decode-Execute
       */
      if (FetchInstruction(curPE,&instr)) {
         PRINT_INSTRUCTION(curPE,instr.word);
         DecodeExecuteCommitCycle(curPE,instr);
         if (curPE->cpuState == cpu_stalled) {
            /*
             * XXX bugnion
             * stall on D-miss. should latch instruction
             */
         }
            
      }
    } /* for (i=0..MP_SIM_CYCLE_GRAIN) */
   } /* while (1) */
}

static void KappaDoneRunning(void)
{
   FalseSharingCleanup();  
   CPUWarning("Exiting the Kappa simulator \n");
   AnnExec(AnnFind("simos", "exit"));
}


void KappaTclInit(Tcl_Interp *interp)
{
  NOTREACHED();
}

Result KappaGetMem(int cpunum, VA vAddr, uint nbytes, char *buf)
{
   int i;
   PA pAddr=0;
   buf[0] = 0;
   for (i=0;i<nbytes;i++) {
      if (EV5_DTranslateVirtual(PE[cpunum],vAddr+i,0,0,&pAddr)==MMU_SUCCESS) {
	 buf[i] = *(char *)PHYS_TO_MEMADDR(0,pAddr);
	 MemRefDebugReadData(cpunum, vAddr, pAddr, &buf[i], 1);
      } else {
	 return FAILURE;
      }
   }
   return SUCCESS;
}

Result KappaPutMem(int cpunum, VA vAddr, uint nbytes, char *buf)
{

   int i;
   PA pAddr=0;
   CPUWarning("Put mem size %d addr 0x%lx buf 0x%x (flush cache) \n",nbytes,vAddr,*(uint32*)buf);
   for (i=0;i<nbytes;i++) {
      if (EV5_DTranslateVirtual(PE[cpunum],vAddr+i,0,0,&pAddr)==MMU_SUCCESS) {
	 MemRefDebugWriteData(cpunum, vAddr, pAddr, &buf[i], 1);
      } else {
	 return FAILURE;
      }
   }
   return SUCCESS;
}

void KappaDMAInval(int machine, PA* k0list)
{
   ;
}

/*****************************************************************
 * CPUVectorInit
 *****************************************************************/

void 
KappaCPUVectorInit(void)
{
#if 0 /* use GammaGetMem, etc. until we turn on data handling in MemRef */
   CPUVec.GetMemory            = KappaGetMem;
   CPUVec.PutMemory            = KappaPutMem;
#endif
   CPUVec.DMAInval             = KappaDMAInval;
   CPUVec.useMemRef            = TRUE;
   CPUVec.singleEventQueue     = TRUE;
}