ms_cache.h
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/*
* Copyright (C) 1996-1998 by the Board of Trustees
* of Leland Stanford Junior University.
*
* This file is part of the SimOS distribution.
* See LICENSE file for terms of the license.
*
*/
/*
* ms_cache.h - Header file for load/store buffer and MXS
* cache simulator.
*
* Jim Bennett
* 1993, 1994, 1995
*/
#ifndef _SYS_TYPES_H
typedef unsigned int uint;
typedef unsigned short ushort;
typedef unsigned char uchar;
#endif
/* Define the load/store buffer */
struct s_ldst_buffer {
struct s_ldst_buffer *next;
struct s_ldst_buffer *prev;
struct s_lsq *ls;
char *dataPtr;
void *missTag;
int cacheStallReason;
int paddr;
int size;
int invalidated;
struct s_ldst_buffer *loadhit;
char data[8];
char validBytes[8];
};
struct s_lsq
{
int status; /* Status bits and lstypes defined below */
int lstype;
int addr;
int paddr;
int reg;
int reg2; /* Source reg for LWL/LWR, dst reg for SC */
int inum; /* Inum causing reference */
struct s_ldst_buffer *ldst_ent; /* Entry in ldst_buffer */
};
/* Load/store status bits */
#define LS_ST_PEND 0x0001 /* Waiting for data to be ready */
#define LS_ST_UNCACHED 0x0002 /* If is an uncached operation */
#define LS_ST_CACHED 0x0004 /* If already sent to cache */
#define LS_ST_CONFLICT 0x0008 /* If conflicts with earlier entry */
#define LS_ST_DONE 0x0010 /* Operation has been completed */
#define LS_ST_FAILED 0x0020 /* Cache rejected operation */
#define LS_ST_STALL 0x0040 /* Cache will call back */
#define LS_ST_PC_DLY 0x0080 /* Primary cache delay (on hit) */
/* Load/store types */
#define LD_DELETED -1 /* Invalid entry */
#define LD_UNSIGNED_B 0 /* Unsigned byte */
#define LD_UNSIGNED_H 1 /* Unsigned half word */
#define LD_UNSIGNED_L 2 /* Unsigned left word */
#define LD_UNSIGNED_R 3 /* Unsigned right word */
#define LD_INTEGER_B 4 /* Integer byte */
#define LD_INTEGER_H 5 /* Integer half word */
#define LD_INTEGER_W 6 /* Integer word */
#define LD_FLOAT 7 /* Floating point */
#define LD_DOUBLE 8 /* Double word (FP) */
#define LD_INTEGER_LL 9 /* Integer load linked */
#define ST_INTEGER_B 10 /* Store byte */
#define ST_INTEGER_H 11 /* Store half word */
#define ST_INTEGER_W 12 /* Store word */
#define ST_INTEGER_L 13 /* Store word left */
#define ST_INTEGER_R 14 /* Store word right */
#define ST_FLOAT 15 /* Store floating point */
#define ST_DOUBLE 16 /* Store double (FP) */
#define ST_INTEGER_SC 17 /* Store conditional word */
#define PREFETCH 18
#define IsStore(t) ((t)>=ST_INTEGER_B && (t)<PREFETCH)
#define IsPrefetch(t) ((t)==PREFETCH)
#define IsLoad(t) ((t)<ST_INTEGER_B)
#define IsDouble(t) (((t) == LD_DOUBLE) || ((t) == ST_DOUBLE))
#define IsSC(t) ((t) == ST_INTEGER_SC)
#ifdef TRACE
/* The memory (load/store) trace record format */
struct s_trace
{
int addr;
int lstype;
union {
int ireg;
uint ureg;
float freg;
double dreg;
} u;
};
#endif
#ifdef MXS_CACHE
/* Define the cache line busy queue */
/* and the bus queue structures */
struct s_lbsy
{
int active; /* State of queue entry */
uint addr;
int set; /* Cache location we are */
int line; /* waiting on */
int rw;
};
struct s_dbus
{
struct s_dbus *next; /* Linked list of transactions */
int ticks;
struct s_lbsy *misstag; /* If this request came from */
/* the line busy queue, keep */
/* track of which entry */
uint addr;
int set; /* Cache location we are */
int line; /* waiting on */
int rw;
int store; /* If write to memory */
int prefetch; /* If stream buffer prefetch */
};
/* Macros for handling cache accesses, and converting */
/* addresses in the simulator to addresses in virtual memory */
#define LOG2_PC_INDEX (LOG2_PC_CACHE_SIZE-LOG2_PC_SET_SIZE)
#define PC_TAG_BITS (-1<<LOG2_PC_INDEX)
#define PC_NLINES (PC_CACHE_SIZE/(PC_LINE_SIZE*PC_SET_SIZE))
#define LOG2_PC_NLINES (LOG2_PC_CACHE_SIZE- \
(LOG2_PC_LINE_SIZE+LOG2_PC_SET_SIZE))
#define LineNo(a) (((a)>>LOG2_PC_LINE_SIZE) & (~(-1<<LOG2_PC_NLINES)))
#define ILineNo(a,i) (((a)>>LOG2_PC_LINE_SIZE) & \
(~(-1<<(LOG2_PC_NLINES+(i)))))
#define Index(a) ((a) & (~(-1<<LOG2_PC_INDEX)))
/* Per cache line status bits */
#define LINE_DIRTY 0x01
#define LINE_BUSY 0x02
/* Definitions for the load/store buffer code */
#define DCACHE_INDEXOF(x) (LineNo(x))
#define DCACHE_TAG(x) ((x)&PC_TAG_BITS)
#define SCACHE_INDEXOF(x) (LineNo(x))
#endif