m32r.c
12.5 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
/* m32r simulator support code
Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define WANT_CPU m32rbf
#define WANT_CPU_M32RBF
#include "sim-main.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
/* Decode gdb ctrl register number. */
int
m32r_decode_gdb_ctrl_regnum (int gdb_regnum)
{
switch (gdb_regnum)
{
case PSW_REGNUM : return H_CR_PSW;
case CBR_REGNUM : return H_CR_CBR;
case SPI_REGNUM : return H_CR_SPI;
case SPU_REGNUM : return H_CR_SPU;
case BPC_REGNUM : return H_CR_BPC;
case BBPSW_REGNUM : return H_CR_BBPSW;
case BBPC_REGNUM : return H_CR_BBPC;
}
abort ();
}
/* The contents of BUF are in target byte order. */
int
m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
{
int mach = MACH_NUM (CPU_MACH (current_cpu));
if (rn < 16)
SETTWI (buf, a_m32r_h_gr_get (current_cpu, rn));
else
switch (rn)
{
case PSW_REGNUM :
case CBR_REGNUM :
case SPI_REGNUM :
case SPU_REGNUM :
case BPC_REGNUM :
case BBPSW_REGNUM :
case BBPC_REGNUM :
SETTWI (buf, a_m32r_h_cr_get (current_cpu,
m32r_decode_gdb_ctrl_regnum (rn)));
break;
case PC_REGNUM :
if (mach == MACH_M32R)
SETTWI (buf, m32rbf_h_pc_get (current_cpu));
else
SETTWI (buf, m32rxf_h_pc_get (current_cpu));
break;
case ACCL_REGNUM :
if (mach == MACH_M32R)
SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu)));
else
SETTWI (buf, GETLODI (m32rxf_h_accum_get (current_cpu)));
break;
case ACCH_REGNUM :
if (mach == MACH_M32R)
SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu)));
else
SETTWI (buf, GETHIDI (m32rxf_h_accum_get (current_cpu)));
break;
default :
return 0;
}
return -1; /*FIXME*/
}
/* The contents of BUF are in target byte order. */
int
m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
{
int mach = MACH_NUM (CPU_MACH (current_cpu));
if (rn < 16)
a_m32r_h_gr_set (current_cpu, rn, GETTWI (buf));
else
switch (rn)
{
case PSW_REGNUM :
case CBR_REGNUM :
case SPI_REGNUM :
case SPU_REGNUM :
case BPC_REGNUM :
case BBPSW_REGNUM :
case BBPC_REGNUM :
a_m32r_h_cr_set (current_cpu,
m32r_decode_gdb_ctrl_regnum (rn),
GETTWI (buf));
break;
case PC_REGNUM :
if (mach == MACH_M32R)
m32rbf_h_pc_set (current_cpu, GETTWI (buf));
else
m32rxf_h_pc_set (current_cpu, GETTWI (buf));
break;
case ACCL_REGNUM :
{
DI val;
if (mach == MACH_M32R)
val = m32rbf_h_accum_get (current_cpu);
else
val = m32rxf_h_accum_get (current_cpu);
SETLODI (val, GETTWI (buf));
if (mach == MACH_M32R)
m32rbf_h_accum_set (current_cpu, val);
else
m32rxf_h_accum_set (current_cpu, val);
break;
}
case ACCH_REGNUM :
{
DI val;
if (mach == MACH_M32R)
val = m32rbf_h_accum_get (current_cpu);
else
val = m32rxf_h_accum_get (current_cpu);
SETHIDI (val, GETTWI (buf));
if (mach == MACH_M32R)
m32rbf_h_accum_set (current_cpu, val);
else
m32rxf_h_accum_set (current_cpu, val);
break;
}
default :
return 0;
}
return -1; /*FIXME*/
}
/* Cover fns for mach independent register accesses. */
SI
a_m32r_h_gr_get (SIM_CPU *current_cpu, UINT regno)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_M32RBF
case MACH_M32R :
return m32rbf_h_gr_get (current_cpu, regno);
#endif
#ifdef HAVE_CPU_M32RXF
case MACH_M32RX :
return m32rxf_h_gr_get (current_cpu, regno);
#endif
default :
abort ();
}
}
void
a_m32r_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_M32RBF
case MACH_M32R :
m32rbf_h_gr_set (current_cpu, regno, newval);
break;
#endif
#ifdef HAVE_CPU_M32RXF
case MACH_M32RX :
m32rxf_h_gr_set (current_cpu, regno, newval);
break;
#endif
default :
abort ();
}
}
USI
a_m32r_h_cr_get (SIM_CPU *current_cpu, UINT regno)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_M32RBF
case MACH_M32R :
return m32rbf_h_cr_get (current_cpu, regno);
#endif
#ifdef HAVE_CPU_M32RXF
case MACH_M32RX :
return m32rxf_h_cr_get (current_cpu, regno);
#endif
default :
abort ();
}
}
void
a_m32r_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_M32RBF
case MACH_M32R :
m32rbf_h_cr_set (current_cpu, regno, newval);
break;
#endif
#ifdef HAVE_CPU_M32RXF
case MACH_M32RX :
m32rxf_h_cr_set (current_cpu, regno, newval);
break;
#endif
default :
abort ();
}
}
USI
m32rbf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
{
switch (cr)
{
case H_CR_PSW : /* psw */
return (((CPU (h_bpsw) & 0xc1) << 8)
| ((CPU (h_psw) & 0xc0) << 0)
| GET_H_COND ());
case H_CR_BBPSW : /* backup backup psw */
return CPU (h_bbpsw) & 0xc1;
case H_CR_CBR : /* condition bit */
return GET_H_COND ();
case H_CR_SPI : /* interrupt stack pointer */
if (! GET_H_SM ())
return CPU (h_gr[H_GR_SP]);
else
return CPU (h_cr[H_CR_SPI]);
case H_CR_SPU : /* user stack pointer */
if (GET_H_SM ())
return CPU (h_gr[H_GR_SP]);
else
return CPU (h_cr[H_CR_SPU]);
case H_CR_BPC : /* backup pc */
return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
case H_CR_BBPC : /* backup backup pc */
return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
case 4 : /* ??? unspecified, but apparently available */
case 5 : /* ??? unspecified, but apparently available */
return CPU (h_cr[cr]);
default :
return 0;
}
}
void
m32rbf_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
{
switch (cr)
{
case H_CR_PSW : /* psw */
{
int old_sm = (CPU (h_psw) & 0x80) != 0;
int new_sm = (newval & 0x80) != 0;
CPU (h_bpsw) = (newval >> 8) & 0xff;
CPU (h_psw) = newval & 0xff;
SET_H_COND (newval & 1);
/* When switching stack modes, update the registers. */
if (old_sm != new_sm)
{
if (old_sm)
{
/* Switching user -> system. */
CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
}
else
{
/* Switching system -> user. */
CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
}
}
break;
}
case H_CR_BBPSW : /* backup backup psw */
CPU (h_bbpsw) = newval & 0xff;
break;
case H_CR_CBR : /* condition bit */
SET_H_COND (newval & 1);
break;
case H_CR_SPI : /* interrupt stack pointer */
if (! GET_H_SM ())
CPU (h_gr[H_GR_SP]) = newval;
else
CPU (h_cr[H_CR_SPI]) = newval;
break;
case H_CR_SPU : /* user stack pointer */
if (GET_H_SM ())
CPU (h_gr[H_GR_SP]) = newval;
else
CPU (h_cr[H_CR_SPU]) = newval;
break;
case H_CR_BPC : /* backup pc */
CPU (h_cr[H_CR_BPC]) = newval;
break;
case H_CR_BBPC : /* backup backup pc */
CPU (h_cr[H_CR_BBPC]) = newval;
break;
case 4 : /* ??? unspecified, but apparently available */
case 5 : /* ??? unspecified, but apparently available */
CPU (h_cr[cr]) = newval;
break;
default :
/* ignore */
break;
}
}
/* Cover fns to access h-psw. */
UQI
m32rbf_h_psw_get_handler (SIM_CPU *current_cpu)
{
return (CPU (h_psw) & 0xfe) | (CPU (h_cond) & 1);
}
void
m32rbf_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
{
CPU (h_psw) = newval;
CPU (h_cond) = newval & 1;
}
/* Cover fns to access h-accum. */
DI
m32rbf_h_accum_get_handler (SIM_CPU *current_cpu)
{
/* Sign extend the top 8 bits. */
DI r;
#if 1
r = ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff));
r = XORDI (r, MAKEDI (0x800000, 0));
r = SUBDI (r, MAKEDI (0x800000, 0));
#else
SI hi,lo;
r = CPU (h_accum);
hi = GETHIDI (r);
lo = GETLODI (r);
hi = ((hi & 0xffffff) ^ 0x800000) - 0x800000;
r = MAKEDI (hi, lo);
#endif
return r;
}
void
m32rbf_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
{
CPU (h_accum) = newval;
}
#if WITH_PROFILE_MODEL_P
/* FIXME: Some of these should be inline or macros. Later. */
/* Initialize cycle counting for an insn.
FIRST_P is non-zero if this is the first insn in a set of parallel
insns. */
void
m32rbf_model_insn_before (SIM_CPU *cpu, int first_p)
{
M32R_MISC_PROFILE *mp = CPU_M32R_MISC_PROFILE (cpu);
mp->cti_stall = 0;
mp->load_stall = 0;
if (first_p)
{
mp->load_regs_pending = 0;
mp->biggest_cycles = 0;
}
}
/* Record the cycles computed for an insn.
LAST_P is non-zero if this is the last insn in a set of parallel insns,
and we update the total cycle count.
CYCLES is the cycle count of the insn. */
void
m32rbf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
{
PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
M32R_MISC_PROFILE *mp = CPU_M32R_MISC_PROFILE (cpu);
unsigned long total = cycles + mp->cti_stall + mp->load_stall;
if (last_p)
{
unsigned long biggest = total > mp->biggest_cycles ? total : mp->biggest_cycles;
PROFILE_MODEL_TOTAL_CYCLES (p) += biggest;
PROFILE_MODEL_CUR_INSN_CYCLES (p) = total;
}
else
{
/* Here we take advantage of the fact that !last_p -> first_p. */
mp->biggest_cycles = total;
PROFILE_MODEL_CUR_INSN_CYCLES (p) = total;
}
/* Branch and load stall counts are recorded independently of the
total cycle count. */
PROFILE_MODEL_CTI_STALL_CYCLES (p) += mp->cti_stall;
PROFILE_MODEL_LOAD_STALL_CYCLES (p) += mp->load_stall;
mp->load_regs = mp->load_regs_pending;
}
static INLINE void
check_load_stall (SIM_CPU *cpu, int regno)
{
UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
if (regno != -1
&& (h_gr & (1 << regno)) != 0)
{
CPU_M32R_MISC_PROFILE (cpu)->load_stall += 2;
if (TRACE_INSN_P (cpu))
cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
}
}
int
m32rbf_model_m32r_d_u_exec (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT sr, INT sr2, INT dr)
{
check_load_stall (cpu, sr);
check_load_stall (cpu, sr2);
return idesc->timing->units[unit_num].done;
}
int
m32rbf_model_m32r_d_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT src1, INT src2)
{
check_load_stall (cpu, src1);
check_load_stall (cpu, src2);
return idesc->timing->units[unit_num].done;
}
int
m32rbf_model_m32r_d_u_mac (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT src1, INT src2)
{
check_load_stall (cpu, src1);
check_load_stall (cpu, src2);
return idesc->timing->units[unit_num].done;
}
int
m32rbf_model_m32r_d_u_cti (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT sr)
{
PROFILE_DATA *profile = CPU_PROFILE_DATA (cpu);
int taken_p = (referenced & (1 << 1)) != 0;
check_load_stall (cpu, sr);
if (taken_p)
{
CPU_M32R_MISC_PROFILE (cpu)->cti_stall += 2;
PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
}
else
PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
return idesc->timing->units[unit_num].done;
}
int
m32rbf_model_m32r_d_u_load (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT sr, INT dr)
{
CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending |= (1 << dr);
check_load_stall (cpu, sr);
return idesc->timing->units[unit_num].done;
}
int
m32rbf_model_m32r_d_u_store (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT src1, INT src2)
{
check_load_stall (cpu, src1);
check_load_stall (cpu, src2);
return idesc->timing->units[unit_num].done;
}
int
m32rbf_model_test_u_exec (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced)
{
return idesc->timing->units[unit_num].done;
}
#endif /* WITH_PROFILE_MODEL_P */