/*
 * pifmon.s
 */
#include "sys/regdef.h"
#include "sys/asm.h"
#include "tinymon.h"

        .text
        .set noat			# allows us to use register $1 ($at)
        .set noreorder	

LEAF (Boot)                       	# Address = 0xbfc00000.

 #
 # Rom entry point; on reset, the R4300 fetches instructions starting at 
 # address 0xbfc00000; we tell the R4300 to immediately jump to cartridge
 # rom address 0xb0000400 (0x400 bytes into the cartridge rom).
 #
	lui	s0, 0xb000
	addiu	s0, s0, 0x400
	j	s0

 #
 # Cartridge ramrom read/write access routines.  We provide them here, so that
 # ramrom resident programs may jump briefly into the pif rom to send or fetch 
 # data to/from ramrom without running into memory arbitration problems caused
 # by accessing the ramrom while the cpu is fetching instructions from ramrom.
 #
 # NOTE:	these routines assume that the caller has already read the
 #		PI_STATUS_REG to guarantee that neither busy bits
 #		(PI_STATUS_IO_BUSY or PI_STATUS_DMA_BUSY) are set. 
 #

 #
 # Read from cartridge ramrom co-routine.  Register usage:
 #
 #	t0	cartridge ramrom address to read from
 #	t1	read return value
 #	ra	return address to jr to
 #
#ifdef BROKEN_PIF_ROUTINES
rdCart:	lw	t1, 0x0(t0)
	nop
	jr	ra
	nop

 #
 # Write to cartridge ramrom co-routine.  Register usage:
 #
 #	t0	cartridge ramrom address to write to
 #	t1	data value to write into cartridge ramrom
 #	ra	return address to jr to
 #
wrCart:	sw	t1, 0x0(t0)
	jr	ra
	nop
#else
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
#endif
 #
 # Write to cartridge ramrom co-routine.  Register usage:
 #
 #	t0	cartridge ramrom address to write to
 #	t1	data value to write into cartridge ramrom
 #	ra	return address to jr to
 #
wrCart:	sw	t1, 0x0(t0)
	lui	t7, PI_BASE_REG_UPPER

waitForIdle:

	lw	t6, PI_STATUS_REG_OFFSET(t7)
	nop
	andi	t6, t6, (PI_STATUS_DMA_BUSY | PI_STATUS_IO_BUSY)
	bne	t6, zero, waitForIdle
	nop
	jr	ra
	nop

 #
 # Now prepare a default interrupt exception vector table.  There are three 
 # types of exceptions in all, user tlb miss, extended address tlb miss,
 # and all others.  The condition codes in the CAUSE register will be set.
 #
 # Each exception will simply spin forever, jumping back to its entry point
 # (making it easy to capture which exception was triggered by looking at the
 # memory bus address on a logic analyzer).
 #

        .align      9                   # Align to start of the vector table.
	                                # Address = 0xbfc00200.
#ifdef OLD_VECTOR_ROUTINES
	lui	s0, 0xbfc0
	addiu	s0, s0, 0x200		# Spin forever at 0xbfc00200
	j	s0			# utlbmiss boot exception vector
#else
	nop				# overwrite old instructions
	nop				# overwrite old instructions
	nop				# overwrite old instructions
	nop				# overwrite old instructions
        lui     s0, RAMROM_BASE_UPPER
	addiu	s0, s0, 0x780		# utlbmiss boot exception vector 
	j	s0			# jump to 0xb0000780 (0x780 into ramrom)
	nop

#endif
        .align      7                   # Align to next exception vector
					# Address = 0xbfc00280.
#ifdef OLD_VECTOR_ROUTINES
	lui	s0, 0xbfc0
	addiu	s0, s0, 0x280		# Spin forever at 0xbfc00280
	j	s0			# xutlbmiss boot exception vector
#else
	nop				# overwrite old instructions
	nop				# overwrite old instructions
	nop				# overwrite old instructions
	nop				# overwrite old instructions
        lui     s0, RAMROM_BASE_UPPER
	addiu	s0, s0, 0x780		# utlbmiss boot exception vector 
	j	s0			# jump to 0xb0000780 (0x780 into ramrom)
	nop
#endif

        .align      8                   # Align to next exception vector
					# Address = 0xbfc00380.
#ifdef OLD_VECTOR_ROUTINES
	lui	s0, 0xbfc0
	addiu	s0, s0, 0x380		# Spin forever at 0xbfc00380
	j	s0			# "Others" (all other exceptions)
#else
	nop				# overwrite old instructions
	nop				# overwrite old instructions
	nop				# overwrite old instructions
	nop				# overwrite old instructions
        lui     s0, RAMROM_BASE_UPPER
	addiu	s0, s0, 0x780		# utlbmiss boot exception vector 
	j	s0			# jump to 0xb0000780 (0x780 into ramrom)
	nop
#endif

END (Boot)