Command Shuffle Unit Test Plan:
			 Fri Sep  9 11:43:33 PDT 1994


I. Understand the unit. 
   - basic function and algorithms.	(done)
   - C-simulation framework.		(done)
   - some detailed algorithms.		(done)

II. Get the C-simulation framework running.	(done)
    - compiled, running simple cases.   (done)
    - understand inputs/outputs.	(done)

III. Construct first-pass test cases.
     - several commands tested.		(done)
     - odd cases, multi-word commands, things which shuffle, etc. (done)
     - one of each command (done)
     - lots of commands, lots of big commands that clog the FIFO, ... (done)

IV. Run first-pass tests, examine output.
    - everything look okay? yes. (done)

V. Run first-pass tests, compare with Verilog.
    - everything look okay? yes. (done)

VI. Construct exhaustive test cases.
    - exhaustive command examination (mostly done. Need to examine
	output by hand for each command. We did this, but some of
	the commands didn't have all the fields set, see below)
    - walking 1's (to test data path)

VII. Remaining issues.

	- not every example in the "every command" test (rdpall)
	  was sufficiently "interesting". The pipelining, the number
	  of output words, etc. were all verified, but there might
	  be nagging bit-field problems in some of the more obscure
	  data muxing cases. (data mux tables vs. verilog for cs_ew_data)

	- one of the tricky areas are the signals which control the fifo,
	  like xbus_cs_valid, cs_xbus_req, start_prim, attr_valid, etc.
	  These are the keys to the pipeline flow. Need to beat on
	  these cases and carefully examine their behavior.

	- we need the sync release signals implemented in order to
	  test the rdp sync commands.

	- integration with the ew might force some tiny changes.


------------------------------------------------------------------------------------------

Test Cases
----------

0) reset (make sure that all other external inputs have no effect)

1) all possible command types with walking ones to insure proper output muxing.

2) all possible command types with random data to insure proper address shuffling.

during (1) and (2) fill the fifo completely and empty out the fifo completely several times.
also toggle ew_busy to verify shf_state.

3) repeat (2) but interleave each of the 3 syncs before and after each of the commands to insure 
   proper stop and restart.


cs.v
----

verify all relative timing of I/O


csclk.v
-------

observe wr_adrs[5:0] increment based on xbus_valid. 

observe words_fifo[5:0] updates simultaneously with the data being clocked into the register files. 
also verify that it wraps/unwraps correctly. 

observe empty = (words_fifo == 0) (make sure its not off by a clock)

observe cs_xbus_req <= (words_fifo <= 22). insure that the latency of cs_xbus_req cannot cause the fifo
to overflow.

observe that during and after reset, wr_adrs = rd_adrs = words_fifo = 0. and empty = cs_xbus_req = 1. 


csfiforptr.v
------------

confirm that rd_adrs transitions simultaneously with the last word of the primitive or attribute. 
verify that it doesn't update when empty or sync_state.

verify that the rd_adrs is incremented by the correct command size for all commands.


csshuffle.v
-----------

confirm that shf_state = 0, during and after reset. 

confirm that shf_state remains at zero for all non-primitives, and cycles from 0 to 21 for all 
primitives. confirm that shf_state remains at zero if (words_fifo < size_prim) or ew_busy or empty 
or sync_state.

confirm that for all primitives, the off_addr and sel_inv are correct based on shf_state and cmd.

confirm that for all non-primitives, rm_adrs = rl_adrs = base_adrs. 


csdecode.v
----------

verify that start_prim is a one-cycle pulse one clock after new_prim goes high. 

confirm that ew_busy timing from edge walker is correct.

verify that attr_valid goes high with only attributes and is disabled during sync or fifo empty

verify that sync_state goes high one cycle after sync is read out of fifo and goes low one
cycle after rel_sync signal.

fifo_out is registered and fifo_data is muxed. verify fifo_data muxing onto cs_ew_data, 
cs_tc_data, tile_addr, and we's for all commands (both primitives and non-primitives).

confirm texel_size attribute timing wrt the load primitives.

confirm that every necessary register is stalled by syncs: rd_adrs, shf_state, start_prim, attr_valid

verify back to back syncs ? verify all three types of syncs.