dplat0201.vmd
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/**************************************************************/
/* Verilog module of datapath cell dplat0201 */
/* Designed by Chunling Liu Compass Aug. 4, 92 */
/* Designed by Linda J. Xu Compass Sep. 10 92 */
/* Changed by Matt Rohm SGI May 27 94 */
/* (fixed the DELAY assignment, and async behavior) */
/* */
/* The following is the port description */
/* Data ports */
/* D : the input port */
/* Q : the output port */
/* Control ports */
/* INST_CP : the clock signal */
/* INST_INIT : initialization control input */
/* Parameters */
/* WORDSIZE : the word size of the datapath cell */
/* DELAY : the delay time from input to output */
/* initial_value: initialize the output */
/**************************************************************/
module dplat0201(D, Q, INST_CP, INST_INIT);
parameter WORDSIZE = 8, initial_value = 'b00000000, DELAY = 4, BF = 1;
input [WORDSIZE-1:0] D;
output [WORDSIZE-1:0] Q;
input INST_CP, INST_INIT;
reg [WORDSIZE-1:0] Q;
initial Q = {WORDSIZE{1'bx}};
function [WORDSIZE-1:0] alat;
input [WORDSIZE-1:0] d;
begin
case (INST_CP)
'b 0 : alat = Q;
'b 1 : alat = ~(~d);
default alat = {WORDSIZE{1'b x}};
endcase
case (INST_INIT)
'b 0 : alat = initial_value;
'b 1 : ;
default alat = {WORDSIZE{1'b x}};
endcase
end
endfunction
always @ (INST_CP or D or INST_INIT) Q = #DELAY alat(D);
endmodule