ai.ss
4.57 KB
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/*****************************************************************************/
/* custom variables */
/*****************************************************************************/
module = "ai"
wire_load = 256000
standard_load = 0.01
clock = "clock"
clocks = { "clock" "vbus_clock" }
default_input_delay = 1.5
default_output_delay = 13.0
default_pin_delay = 10.0
default_input_load = 20
default_output_load = 20
default_pin_load = 150
default_drive_cell = "dfntnh"
default_drive_pin = "q"
default_period = 16.0
default_max_transition = 1.5
default_uncertainty = 1.0
/*****************************************************************************/
/* set the path and read */
/*****************************************************************************/
search_path = search_path \
+ "../src" \
+ "../../inc" \
+ "../../../lib/verilog/user" \
+ "../../syn"
read -f verilog cbus_driver.v
read -f verilog ai_controller.v
read -f verilog ai_abus.v
read -f verilog ai_dma.v
read -f verilog module + ".v"
/*****************************************************************************/
/* default environment */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top
/*****************************************************************************/
/* clock constraints */
/*****************************************************************************/
create_clock clocks -period default_period -waveform { 0.0 default_period / 2 }
set_clock_skew -propagated -uncertainty default_uncertainty clocks
set_dont_touch_network clocks
/*****************************************************************************/
/* default constraint */
/*****************************************************************************/
set_max_area 0
set_dont_touch { ne35hd130d/nt01d* }
set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null
set_drive 0 { clocks }
set_input_delay 0 { clocks }
set_max_transition default_max_transition current_design
/*****************************************************************************/
/* custom constraints */
/*****************************************************************************/
set_driving_cell -cell ni01d5 { cbus_read_enable cbus_write_enable }
set_driving_cell -cell nt01d5 { cbus_data }
set_load 100 * standard_load { cbus_data }
set_input_delay 10.0 -clock clock { cbus_data }
set_output_delay 10.0 -clock clock { cbus_data }
set_driving_cell -cell ni01d5 { dma_start }
set_load 100 * standard_load { dma_start }
set_max_fanout 2 * standard_load { dma_start }
set_driving_cell -cell ni01d5 { cbus_command cbus_select }
set_load 100 * standard_load { cbus_command cbus_select }
set_max_fanout 2 * standard_load { cbus_command cbus_select }
set_load default_pin_load * standard_load \
{ abus_data abus_word abus_clock }
set_output_delay default_pin_delay -clock clock \
{ abus_data abus_word abus_clock }
set_false_path -fall -from reset_l
set_max_fanout 2 * standard_load reset_l
/*****************************************************************************/
/* check */
/*****************************************************************************/
link
check_design > module + ".lint"
/*****************************************************************************/
/* compile */
/*****************************************************************************/
compile -map_effort high -ungroup_all
/*****************************************************************************/
/* write */
/*****************************************************************************/
include "report.dc"
change_names -rules compass_rules -hierarchy
write -format edif -hierarchy -o module + ".edf" module
write -format db -hierarchy -o module + ".db" module
quit