/*****************************************************************************/
/* custom variables                                                          */
/*****************************************************************************/
module = "at"
wire_load = 256000
standard_load = 0.01
clock = "clk"
clocks = { "clk" "gclk" }
default_input_delay = 1.5
default_output_delay = 13.0
default_input_load = 20
default_output_load = 20
default_drive_cell = "dfntnh"
default_drive_pin = "q"
default_period = 16.0
default_max_transition = 1.5
default_uncertainty = 1.0

hdlin_force_use_ffgen = false


/*****************************************************************************/
/* set the path and read                                                     */
/*****************************************************************************/
search_path = search_path \
   + "../src" \
   + "../../inc" \
   + "../../syn"

read -f edif at_ew.edf
read -f edif at_tc.edf
read -f edif at_cc.edf
read -f edif at_bl.edf
read -f edif at_ms.edf
read -f verilog module + ".v"


/*****************************************************************************/
/* default environment                                                       */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top


/*****************************************************************************/
/* clock and reset constraints                                               */
/*****************************************************************************/
create_clock clocks -period default_period -waveform { 0.0 default_period / 2 }
set_clock_skew -propagated -uncertainty default_uncertainty clocks
set_dont_touch_network clocks


/*****************************************************************************/
/* default constraint                                                        */
/*****************************************************************************/
set_max_area 0
set_dont_touch { ne35hd130d/nt01d* }

set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null

set_drive 0 { clocks }
set_input_delay 0 { clock }

set_max_transition default_max_transition current_design


/*****************************************************************************/
/* custom constraints                                                        */
/*****************************************************************************/
/* at_bl */
set_output_delay 0.0 -clock clock st_dxz
set_output_delay 0.0 -clock clock st_dyz
set_output_delay 0.0 -clock clock color_image
set_output_delay 0.0 -clock clock z_image
set_output_delay 0.0 -clock clock tex_image
set_output_delay 0.0 -clock clock blend_color
set_output_delay 0.0 -clock clock fog_color
set_output_delay 0.0 -clock clock fill_color
set_output_delay 0.0 -clock clock other_modes
set_output_delay 0.0 -clock clock prim_depth
set_load 150 * standard_load other_modes

/* at_cc */
set_output_delay 0.0 -clock clock st_dxr
set_output_delay 0.0 -clock clock st_dxg
set_output_delay 0.0 -clock clock st_dxb
set_output_delay 0.0 -clock clock st_dxa
set_output_delay 0.0 -clock clock st_dyr
set_output_delay 0.0 -clock clock st_dyg
set_output_delay 0.0 -clock clock st_dyb
set_output_delay 0.0 -clock clock st_dya
set_output_delay 0.0 -clock clock combine_mode
set_output_delay 0.0 -clock clock env_color
set_output_delay 0.0 -clock clock prim_color
set_output_delay 0.0 -clock clock convert
set_output_delay 0.0 -clock clock key_r
set_output_delay 0.0 -clock clock key_gb

set_output_delay 11.0 -clock clock { noise }
set_load 150 * standard_load { noise }

/* at_ew */
set_output_delay 0.0 -clock clock ew_dxr
set_output_delay 0.0 -clock clock ew_dxg
set_output_delay 0.0 -clock clock ew_dxb
set_output_delay 0.0 -clock clock ew_dxa
set_output_delay 0.0 -clock clock ew_dxz
set_output_delay 0.0 -clock clock ew_dxs
set_output_delay 0.0 -clock clock ew_dxt
set_output_delay 0.0 -clock clock ew_dxw
set_output_delay 0.0 -clock clock ew_dxl
set_output_delay 0.0 -clock clock ew_dyr
set_output_delay 0.0 -clock clock ew_dyg
set_output_delay 0.0 -clock clock ew_dyb
set_output_delay 0.0 -clock clock ew_dya
set_output_delay 0.0 -clock clock ew_dyz
set_output_delay 0.0 -clock clock ew_dys
set_output_delay 0.0 -clock clock ew_dyt
set_output_delay 0.0 -clock clock ew_dyw
set_output_delay 0.0 -clock clock ew_dyl
set_output_delay 0.0 -clock clock scissor
set_output_delay 0.0 -clock clock ew_image_load

set_output_delay 11.0 -clock clock { ew_scissor_tlut }
set_load 150 * standard_load { ew_scissor_tlut }

/* at_ms */
set_output_delay 0.0 -clock clock ms_xi
set_output_delay 0.0 -clock clock ms_xf
set_output_delay 0.0 -clock clock ms_count
set_output_delay 0.0 -clock clock ms_load
set_output_delay 0.0 -clock clock ms_load_tlut
set_output_delay 0.0 -clock clock ms_xdec
set_output_delay 0.0 -clock clock spanbufmt

/* at_tc */
set_output_delay 0.0 -clock clock st_dxs
set_output_delay 0.0 -clock clock st_dxt
set_output_delay 0.0 -clock clock st_dxw
set_output_delay 0.0 -clock clock st_dxl
set_output_delay 0.0 -clock clock shift_coord
set_output_delay 0.0 -clock clock level
set_output_delay 0.0 -clock clock tile

set_false_path -fall -from reset_l
dont_touch_network reset_l
set_dont_touch { ne35hd130d/lan* }


/*****************************************************************************/
/* check                                                                     */
/*****************************************************************************/
check_design > module + ".lint"


/*****************************************************************************/
/* compile                                                                   */
/*****************************************************************************/
compile_no_new_cells_at_top_level = "true"
compile -incremental_mapping


/*****************************************************************************/
/* write                                                                     */
/*****************************************************************************/
include "report.dc"

change_names -rules compass_rules -hierarchy
write -format edif -hierarchy -o module + ".edf" module
write -format db -hierarchy -o module + ".db" module

quit