csgclk.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: csgclk.v,v 1.1.1.1 2002/05/17 06:07:45 blythe Exp $
/////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: csgclk
// description: contails logic clocked by gclk. Rams are not included
//
//
// designer: Mike M. Cai 8/11/94
//
/////////////////////////////////////////////////////////////////////////
module csgclk( // outputs
tile_addr, cs_tc_data, we_tile_size, we_tile_attr,
cs_ew_data, cs_ew_newprim,
read_adrs,
rm_addr, rl_addr,
cmd, start_prim, attr_valid,
// inputs
fifo_out,
texel_size,
words_fifo, empty,
rel_sync_tile, rel_sync_pipe, rel_sync_full, rel_sync_load,
ew_cs_busy, ms_busy, copy_fill,
reset_l, gclk
);
output [2:0] tile_addr;
output [47:0] cs_tc_data;
output we_tile_size, we_tile_attr;
output [63:0] cs_ew_data;
output cs_ew_newprim;
output [5:0] read_adrs;
output [4:0] rm_addr, rl_addr;
output [5:0] cmd;
output start_prim, attr_valid;
input [63:0] fifo_out;
input [1:0] texel_size;
input [5:0] words_fifo;
input empty;
input rel_sync_tile, rel_sync_pipe, rel_sync_full, rel_sync_load;
input ew_cs_busy, ms_busy, copy_fill;
input reset_l, gclk;
// csfiforptr signals
wire [5:0] read_adrs;
wire [4:0] base_adrs;
// csdecode signals
wire update_rptr, inc_shf_state,
one_word_cmd;
wire [63:0] cs_ew_data;
wire [2:0] tile_addr;
wire [47:0] cs_tc_data;
wire we_tile_size, we_tile_attr;
wire [5:0] cmd;
wire [4:0] cmd_size;
wire start_prim, attr_valid;
// csshuffle signals
wire [4:0] rm_addr, rl_addr;
wire [4:0] shf_state;
wire update_shf;
csfiforptr fiforead ( // outputs
.read_adrs(read_adrs),
.base_adrs(base_adrs),
// inputs
.update_rptr(update_rptr),
.one_word_cmd(one_word_cmd),
.cmd_size(cmd_size),
.reset_l(reset_l),
.gclk(gclk)
);
csdecode decode( // outputs
.update_rpt(update_rptr), .inc_shf_state(inc_shf_state),
.one_word_cmd(one_word_cmd), .new_prim(cs_ew_newprim),
.cs_ew_data(cs_ew_data),
.tile_addr(tile_addr), .cs_tc_data(cs_tc_data),
.we_tile_size(we_tile_size), .we_tile_attr(we_tile_attr),
.cmd(cmd), .cmd_size(cmd_size),
.start_prim(start_prim), .attr_valid(attr_valid),
// inputs
.fifo_out(fifo_out),
.texel_size(texel_size),
.shf_state(shf_state), .update_shf(update_shf),
.words_fifo(words_fifo), .empty(empty),
.rel_sync_tile(rel_sync_tile), .rel_sync_pipe(rel_sync_pipe),
.rel_sync_full(rel_sync_full), .rel_sync_load(rel_sync_load),
.ew_busy(ew_cs_busy),
.ms_busy(ms_busy),
.copy_fill(copy_fill),
.reset_l(reset_l), .gclk(gclk));
csshuffle shuffle(// outputs
.rm_addr(rm_addr), .rl_addr(rl_addr),
.shf_state(shf_state), .update_shf(update_shf),
// inputs
.cmd(cmd), .base_adrs(base_adrs),
.inc_shf_state(inc_shf_state),
.reset_l(reset_l), .gclk(gclk));
endmodule // csgclk