csdecode.ss
2.84 KB
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module = csdecode
/* set up a new search path */
search_path = search_path + "../../inc"
/* read the verilog sources */
read -f verilog ../src/csdecode.v
read -f edif cspartdec.edf
read -f edif csdatamux.edf
current_design = csdecode
/* compile restrictions */
set_dont_touch { ne35hd130d/nt01d* }
set_dont_use { ne35hd130d/mbnfnq ne35hd130d/mbnfnr }
set_dont_use { ne35hd130d/jk* }
/* setup operating conditions */
set_operating_conditions NOM
set_wire_load 128000 -mode top
link
check_design > csdecode.lint
/* timing/area constraints */
create_clock gclk -period 14.0 -waveform {7.0 14.0};
set_max_transition 0.8 current_design
/* input delays */
set_input_delay 9.0 -clock gclk {fifo_out[*]}
set_input_delay 2.0 -clock gclk {texel_size[*]}
set_input_delay 2.0 -clock gclk {shf_state[*]}
set_input_delay 4.0 -clock gclk {update_shf}
set_input_delay 5.0 -clock gclk {words_fifo[*]}
set_input_delay 6.0 -clock gclk {empty}
set_input_delay 4.0 -clock gclk {rel_sync_tile, rel_sync_pipe, rel_sync_full}
set_input_delay 4.0 -clock gclk {rel_sync_load}
set_input_delay 2.0 -clock gclk {ew_busy}
set_input_delay 2.0 -clock gclk {ms_busy}
set_driving_cell -cell dfntnh {fifo_out[*]}
set_driving_cell -cell dfntnb {texel_size[*]}
set_driving_cell -cell dfntnh {shf_state[*]}
set_driving_cell -cell nr05d1 {update_shf}
set_driving_cell -cell dfntnh {words_fifo[*]}
set_driving_cell -cell dfntnh {empty}
set_driving_cell -cell dfntnb {rel_sync_tile, rel_sync_pipe, rel_sync_full }
set_driving_cell -cell dfntnb {rel_sync_load}
set_driving_cell -cell dfntnb {ew_busy}
set_driving_cell -cell dfntnb {ms_busy}
/* output delays */
set_output_delay 6.0 -clock gclk {cs_ew_data[*]}
set_output_delay 6.0 -clock gclk {cs_tc_data[*]}
set_output_delay 6.0 -clock gclk {tile_addr[*]}
set_output_delay 10.0 -clock gclk {we_tile_size}
set_output_delay 10.0 -clock gclk {we_tile_attr}
set_output_delay 13.5 -clock gclk {cmd[*]}
set_output_delay 5.0 -clock gclk {cmd_size[*]}
set_output_delay 8.0 -clock gclk {start_prim}
set_output_delay 8.0 -clock gclk {attr_valid}
set_output_delay 4.0 -clock gclk {update_rpt}
set_output_delay 5.0 -clock gclk {inc_shf_state}
set_output_delay 4.0 -clock gclk {one_word_cmd}
set_output_delay 5.0 -clock gclk {new_prim}
/* output loading */
set_load 2.00 {cs_ew_data[*]}
set_load 1.00 {cs_tc_data[*]}
set_load 1.00 {tile_addr[*]}
set_load 1.00 {we_tile_size, we_tile_attr}
set_load 1.50 {cmd[*]}
set_load 0.05 {cmd_size[*]}
set_load 1.00 {start_prim}
set_load 1.00 {attr_valid}
set_load 0.05 {update_rpt}
set_load 0.20 {inc_shf_state, new_prim}
set_load 0.09 {one_word_cmd}
/* compile */
set_dont_touch cspartdec
set_dont_touch csdatamux
compile -map_effort high -ungroup_all
report -reference
/* enforce naming restrictions for Compass tools */
change_names -rules compass_rules -hierarchy
report_constraint -all_violators
write -f edif -o csdecode.edf -hier csdecode
quit