ewrf32b18w.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: ewrf32b18w.v,v 1.1.1.1 2002/05/17 06:07:45 blythe Exp $
/////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: ewrf32b18w
// description: two 9-word by 32-bit register files.
// One for attributes and the other for da/de.
// Both has a read port and a write port.
// The one for da/de has a bypass feather.
//
// designer: Mike M. Cai 6/28/94
//
/////////////////////////////////////////////////////////////////////////
module ewrf32b18w ( wa_data, wa_addr, wen_a, wde_data, wde_addr, wen_de,
ra_addr, rb_addr, // ra_addr is for attribute
ra_data, rb_data, // rb_addr is for da/de
ew_stall_attr, gclk);
input ew_stall_attr, gclk;
input wen_a, wen_de;
input [3:0] wa_addr;
input [3:0] wde_addr;
input [31:0] wa_data, wde_data;
input [3:0] ra_addr, rb_addr;
output [31:0] ra_data, rb_data;
reg [8:0] ra_line, rb_line;
reg [8:0] wa_line;
reg [8:0] wde_line;
wire [8:0] wa_line_wengclk, wde_line_wengclk;
wire [31:0] ra_data_m, rb_data_m;
// wire [31:0] wa_data_delay;
reg [31:0] rb_data_mm;
reg [31:0] ra_data, rb_data;
// decode address this
// read port a
always @(ra_addr)
case (ra_addr)
4'b0000: ra_line = 9'b000000001;
4'b0001: ra_line = 9'b000000010;
4'b0010: ra_line = 9'b000000100;
4'b0011: ra_line = 9'b000001000;
4'b0100: ra_line = 9'b000010000;
4'b0101: ra_line = 9'b000100000;
4'b0110: ra_line = 9'b001000000;
4'b0111: ra_line = 9'b010000000;
4'b1000: ra_line = 9'b100000000;
default: ra_line = 9'b100000000;
endcase
// read port b
always @(rb_addr)
case (rb_addr)
4'b0000: rb_line = 9'b000000001;
4'b0001: rb_line = 9'b000000010;
4'b0010: rb_line = 9'b000000100;
4'b0011: rb_line = 9'b000001000;
4'b0100: rb_line = 9'b000010000;
4'b0101: rb_line = 9'b000100000;
4'b0110: rb_line = 9'b001000000;
4'b0111: rb_line = 9'b010000000;
4'b1000: rb_line = 9'b100000000;
default: rb_line = 9'b100000000;
endcase
// write port for attributes
always @(wa_addr)
case (wa_addr)
4'b0000: wa_line = 9'h001;
4'b0001: wa_line = 9'h002;
4'b0010: wa_line = 9'h004;
4'b0011: wa_line = 9'h008;
4'b0100: wa_line = 9'h010;
4'b0101: wa_line = 9'h020;
4'b0110: wa_line = 9'h040;
4'b0111: wa_line = 9'h080;
4'b1000: wa_line = 9'h100;
default: wa_line = 9'h100;
endcase
assign wa_line_wengclk = wa_line & {9{wen_a}};
// write port for da/de
always @(wde_addr)
casez (wde_addr)
4'b0000: wde_line = 9'h001;
4'b0001: wde_line = 9'h002;
4'b0010: wde_line = 9'h004;
4'b0011: wde_line = 9'h008;
4'b0100: wde_line = 9'h010;
4'b0101: wde_line = 9'h020;
4'b0110: wde_line = 9'h040;
4'b0111: wde_line = 9'h080;
4'b1000: wde_line = 9'h100;
default: wde_line = 9'h100;
endcase
assign wde_line_wengclk = wde_line & {9{wen_de}};
// ewrfdelay delaywdata(.out_data(wa_data_delay), .in_data(wa_data));
ew32blatch
// attributes
word0 (ra_data_m, wa_data, ~wa_line_wengclk[0], ra_line[0], gclk),
word1 (ra_data_m, wa_data, ~wa_line_wengclk[1], ra_line[1], gclk),
word2 (ra_data_m, wa_data, ~wa_line_wengclk[2], ra_line[2], gclk),
word3 (ra_data_m, wa_data, ~wa_line_wengclk[3], ra_line[3], gclk),
word4 (ra_data_m, wa_data, ~wa_line_wengclk[4], ra_line[4], gclk),
word5 (ra_data_m, wa_data, ~wa_line_wengclk[5], ra_line[5], gclk),
word6 (ra_data_m, wa_data, ~wa_line_wengclk[6], ra_line[6], gclk),
word7 (ra_data_m, wa_data, ~wa_line_wengclk[7], ra_line[7], gclk),
word8 (ra_data_m, wa_data, ~wa_line_wengclk[8], ra_line[8], gclk),
// da/de
word9 (rb_data_m, wde_data, ~wde_line_wengclk[0], rb_line[0], gclk),
word10 (rb_data_m, wde_data, ~wde_line_wengclk[1], rb_line[1], gclk),
word11 (rb_data_m, wde_data, ~wde_line_wengclk[2], rb_line[2], gclk),
word12 (rb_data_m, wde_data, ~wde_line_wengclk[3], rb_line[3], gclk),
word13 (rb_data_m, wde_data, ~wde_line_wengclk[4], rb_line[4], gclk),
word14 (rb_data_m, wde_data, ~wde_line_wengclk[5], rb_line[5], gclk),
word15 (rb_data_m, wde_data, ~wde_line_wengclk[6], rb_line[6], gclk),
word16 (rb_data_m, wde_data, ~wde_line_wengclk[7], rb_line[7], gclk),
word17 (rb_data_m, wde_data, ~wde_line_wengclk[8], rb_line[8], gclk);
always @(posedge gclk)
begin
if ((rb_addr == wde_addr) && wen_de)
rb_data_mm = wde_data;
else
rb_data_mm = rb_data_m;
ra_data <= ew_stall_attr ? ra_data : ra_data_m;
rb_data <= ew_stall_attr ? rb_data : rb_data_mm;
end
endmodule // ewrf32b18w