#!/bin/csh -f
#
# CHIPCOMP
#
vlsishell << EOF
set echo on
utility chipcomp

load [nls]div

load [flr]div_floorplan
floor areas on
guidance on
floor property on
seed cell instances on
pad/conn seed off
net weight off
net width off
max capacitance off
ECO placement off
path delays off
clk net info off
accept

load [flr]div_conn_seeds
floor areas off
guidance off
floor property off
seed cell instances off
pad/conn seed on
net weight off
net width off
max capacitance off
ECO placement off
path delays off
clk net info off
accept

set up
initial placement v/h weight 2
initial placement optimize method high
improve vertical weight 2
improve horizontal weight 1
improve optimize on
add power strap on
std column routing passes 9
initial placement optimize seed 2146051399
improve optimize seed 2146051428
accept

seed clock nets
add 1
(1, netname) CLK
(1, frequency) 70M
(1, branchwidth) 6
accept

placecel
improvCel
routecel

set current guidance Vdd
multiply current guidance
connector width
set current guidance Vss
multiply current guidance
connector width
set current guidance by name CLK
multiply current guidance
connector width

routeBK

save
info

quit
exit
EOF
#