padring+nec35io12.tch
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#cell2 nec35io12 padring tch * 7 any 0 v8r4.6.4
# "2-Nov-94 GMT" "20:01:21 GMT" "2-Nov-94 GMT" "20:01:21 GMT" johnr * .
# 08-Aug-94 - padring.tch - for NE35IO120.
#
# rev date who what
# --- -------- ---- ------------------------------------------------------#
# 1.0 08-Aug-94 JAF Initial creation of this file.
# 1.1 24-Aug-94 JAF Removed non-SGI cells from this file.
# 1.2 09-Sep-94 JAF Changed MINPADSPACING from 85 to 20.
# 1.3 4-Oct-94 JDS Added pc3cl3, fixed power pad definitions.
# 1.4 17-Oct-94 JAF Added clkpwr/gnd pins to PADCONNECTOR definitions.
# 2-Noc-94 JR Added RAC phantom to padring.tch. This should not
# be included in official padring.tch i.e:customized
$GENERICPADS
# This section describes the generic pad cells available in all pad rings.
# The height and width here are approximate and are only used for the size
# of the displayed logical pads. (Use Lambda units for the height and width)
#
# The Flag fields are optional and can have the value of "noRouteCon",
# "noBondCon", "vdd", "vss", "doublePad" and "downBond".
# The "noRouteCon" Flag specifies that the cell has no connections to be
# routed to the core. The "noBondCon" Flag says that the cell has no
# connection to any bonding pads. The "vdd" and "vss" Flags indicate that
# this type of generic pad is a VDD or VSS pad used for internal power
# routing. The "doublePad" Flag specifies that the cell has two connections
# to be bonded, usually crystal oscillators. (The "doublePad" Flag may no
# longer be needed, as ChipComp now gets this information from the [mcp]).
# The "downBond" Flag specifies a fictitious pad that is used solely to
# indicate a package pin to downbond.
#
# NAME HEIGHT WIDTH FLAGS
rac_lower 2010 23984 nobondcon
pc3cl3 2010 1521 doublePad
pc3cl3w 2010 1800
spacer_pad 2010 600 nobondcon
pc3d01 2010 600
pc3d11 2010 600
pc3o04 2010 600
pc3o05 2010 600
pc3t04 2010 600
pc3t05 2010 600
pc3b04r 2010 600
pc3b05r 2010 600
pv0a 2010 600 noRouteCon
pv0b 2010 600 vss
pvda 2010 600 noRouteCon
pvdb 2010 600 vdd
$GENERICPADPARMS
# To list the names of the bonding pad connectors, used on an
# I/O cell, use the PADCONNECTOR parameter. This tells ChipComp
# to ignore core routing to that pin and gives the Simulator access
# to watch that pin. There is no stated limit on the number of
# characters used for the PADCONNECTOR name.
PADCONNECTOR pad xin xout clk vddo vsso clkpwr clkgnd
#
# The package pin number for a pad may be specified with a schematic
# parameter. The PINSEEDPARM defines this parameters name, in this
# case the Schematic or LA editors popup a choice for only the
# pinNumber parameter, although, in the popup you may add the
# padNumber, pin or pad parameters if you wish to set there values
# instead. (The first PINSEEDPARM parameter seems to be the default).
PINSEEDPARM pinNumber padNumber pin pad
$PADRING pad_limited(4.7mil)
# ChipComp uses the refrencePin connector name to align the I/O cells.
REFERENCEPIN pdc
#
# Pad spacing must be 0 or >= this amount (in Lambda units)
# This is due to a well-well spacing in the pre-drivers.
MINPADSPACING 0
#
# spacing between core and inside of pad ring. For SCR rules.
MINCORESPACING 0
#
#
# generic pads
# cell type height width flags
GENERIC [mcp]rac_lower rac_lower 2010 23984
GENERIC [mcp]pc3cl3 pc3cl3 2010 1521
GENERIC [mcp]pc3cl3w pc3cl3w 2010 1800
GENERIC [mcp]spacer_pad spacer_pad 2010 600
GENERIC [mcp]pc3d01 pc3d01 2010 600
GENERIC [mcp]pc3d11 pc3d11 2010 600
GENERIC [mcp]pc3o04 pc3o04 2010 600
GENERIC [mcp]pc3o05 pc3o05 2010 600
GENERIC [mcp]pc3t04 pc3t04 2010 600
GENERIC [mcp]pc3t05 pc3t05 2010 600
GENERIC [mcp]pc3b04r pc3b04r 2010 600
GENERIC [mcp]pc3b05r pc3b05r 2010 600
GENERIC [mcp]pv0a pv0a 2010 600
GENERIC [mcp]pv0b pv0b 2010 600
GENERIC [mcp]pvda pvda 2010 600
GENERIC [mcp]pvdb pvdb 2010 600
EMPTYCORNER [mcp]pc45freur 2010 2010 UR
EMPTYCORNER [mcp]pc45freul 2010 2010 UL
EMPTYCORNER [mcp]pc45frelr 2010 2010 LR
EMPTYCORNER [mcp]pc45frell 2010 2010 LL
$END