set_input_delay 8.0 -clock clk {reset_l};
set_input_delay 4.0 -clock clk {iddq_test};

set_input_delay 13.0 -clock clk {rd_base};
set_input_delay 12.0 -clock clk {rd_offset};
set_input_delay 8.0 -clock clk {rd_elem_num};
set_input_delay 13.0 -clock clk {vu_rd_ld_dec_k};
set_input_delay 13.0 -clock clk {vu_rd_st_dec_k};

set_input_delay 11.0 -clock clk {address}; 
set_input_delay 2.0 -clock clk {su_ex_store};
set_input_delay 2.0 -clock clk {su_ex_load};
set_input_delay 2.0 -clock clk {ex_su_byte_ls};
set_input_delay 2.0 -clock clk {ex_su_half_ls};
set_input_delay 2.0 -clock clk {ex_su_uns_ls};
set_input_delay 2.0 -clock clk {vu_ex_store};
set_input_delay 2.0 -clock clk {vu_ex_load};
set_input_delay 2.0 -clock clk {ex_mtc2};
set_input_delay 2.0 -clock clk {ex_mfc2};
set_input_delay 2.0 -clock clk {ex_cfc2};
set_input_delay 8.0 -clock clk {chip_sel};
set_input_delay 1.5 -clock clk {dma_address};
set_input_delay 4.0 -clock clk {dma_wen}; 
set_input_delay 2.0 -clock clk {ex_dma_rd_to_dm};
set_input_delay 2.0 -clock clk {ex_dma_dm_to_rd};

set_input_delay 2.0 -clock clk {df_ls_drive_ls_in_wb};
set_input_delay 2.0 -clock clk {df_pass_thru};


set_output_delay -max 13.0 -clock clk {rot_dp};
set_output_delay -max 9.0 -clock clk {rot_amt};
set_output_delay -max 13.5 -clock clk {vu_ex_st_dec};
set_output_delay -max 7.0 -clock clk {ex_dma_wen_noswap}; 
set_output_delay -max 7.0 -clock clk {ex_dma_wen_swap}; 
 
set_output_delay -max 10.0 -clock clk {df_chip_sel_l}; 
set_output_delay -max 12.0 -clock clk {df_wen_l}; 
set_output_delay -max 13.0 -clock clk {df_addr_low};
set_output_delay -max 10.5 -clock clk {df_addr_high};
set_output_delay -max 4.5 -clock clk {debug_df_dma_rd_to_dm}; 

set_output_delay -max 14.0 -clock clk {wb_dma_dm_to_rd};
set_output_delay -max 13.7 -clock clk {wb_su_uns_ls};
set_output_delay -max 13.7 -clock clk {wb_su_load};
set_output_delay -max 14.0 -clock clk {wb_pass_thru};
set_output_delay -max 14.0 -clock clk {wb_mfc2};
set_output_delay -max 14.0 -clock clk {wb_cfc2};
set_output_delay -max 13.3 -clock clk {wb_swap_dma};
set_output_delay -max 14.0 -clock clk {vu_wb_ld_dec};
set_output_delay -max 4.0 -clock clk {vu_bwe};
set_output_delay -max 14.0 -clock clk {ls_drive_ls};

set_driving_cell -cell dfntnb all_inputs()
set_driving_cell -none  clk
set_drive 0 clk

set_load 1.6 {vu_bwe};
set_load .7 {ls_drive_ls}; 
set_load .2 {rot_dp,wb_pass_thru,wb_dma_dm_to_rd};
set_load .2 {rot_amt,wb_cfc2,wb_mfc2}
set_load .2 {ex_dma_wen_noswap,ex_dma_wen_swap,vu_ex_st_dec,vu_wb_ld_dec}
set_load 1.5 {wb_swap_dma};