/************************************************************************\
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 \************************************************************************/

// $Id: mi.v,v 1.1.1.1 2002/05/17 06:07:47 blythe Exp $

module mi(clock, reset_l, 
   cbus_read_enable, cbus_write_enable, cbus_grant, dbus_read_enable,
   dbus_write_enable, dma_start, dma_last, sys_ad_in_h, sys_cmd_in_h,
   p_valid_l, cbus_select, cbus_command, pi_interrupt, vi_interrupt,
   ai_interrupt, si_interrupt, sp_interrupt, pipe_busy, version,
   dma_request, write_request, read_request, sys_ad_out_h,
   sys_cmd_out_h, e_valid_l, e_ok_l, int_l, sys_ad_enable_l,
   cbus_data, dbus_data, ebus_data);

`include "rcp.vh"

// DMA delays
parameter
	READ_DELAY = 8'd2,
	WRITE_DELAY = -8'd1;

parameter MI_BLOCK_SIZE = 5;
parameter COUNTER_SIZE = 4;

// MI registers
parameter MI_REG_ADDRESS_SIZE = 2;
parameter
	INIT_MODE_ADDRESS	= 0,
	VERSION_ADDRESS	= 1,
	INTERRUPT_ADDRESS	= 2,
	MASK_ADDRESS		= 3;

// IO buffer
parameter
	BUFFER_DATA_SIZE = 32,
	BUFFER_ADDRESS_SIZE = 2;

input clock;											// system clock
input reset_l;											// system reset_l

input cbus_read_enable;								// enable cbus read mux
input cbus_write_enable;							// enable cbus tristate drivers
input cbus_grant;										// SP DMA request granted
input dbus_read_enable;								// enable dbus register read
input dbus_write_enable;							// enable dbus tristate drivers
input dma_start;										// start of dbus transaction
input dma_last;										// valid data on dbus
input [SYS_AD_SIZE-1:0] sys_ad_in_h;			// address/data from CPU
input [SYS_CMD_SIZE-1:0] sys_cmd_in_h;			// command from CPU
input p_valid_l;										// sysAD bus valid from CPU
input [CBUS_SELECT_SIZE-1:0] cbus_select;		// cbus transaction type
input [CBUS_COMMAND_SIZE-1:0] cbus_command;	// cbus transaction type
input pi_interrupt;									// AD16 interrupt
input vi_interrupt;									// Video hblank interrupt
input ai_interrupt;									// audio half-full interrupt
input si_interrupt;									// PIF interrupt
input sp_interrupt;									// RSP interrupt
input pipe_busy;										// full sync interrupt
input [CBUS_DATA_SIZE-1:0] version;				// chip version

output dma_request;									// request a dma cycle
output write_request;								// request a cbus write cycle
output read_request;									// request a cbus read cycle
output [SYS_AD_SIZE-1:0] sys_ad_out_h;			// data to CPU
output [SYS_CMD_SIZE-1:0] sys_cmd_out_h;		// command to CPU
output e_valid_l;										// sysAD bus valid to CPU
output e_ok_l;											// RCP ready to CPU
output int_l;											// interrupt to CPU
output [4:0] sys_ad_enable_l;						// enable RCP on sysAD bus

inout [CBUS_DATA_SIZE-1:0] cbus_data;			// IO bus
inout [DBUS_DATA_SIZE-1:0] dbus_data;			// DMA bus
inout [EBUS_DATA_SIZE-1:0] ebus_data;			// extended DMA bus


// input/output registers
reg [CBUS_COMMAND_SIZE-1:0] cbus_command_reg;
reg [CBUS_DATA_SIZE-1:0] cbus_data_reg;
reg [DBUS_DATA_SIZE-1:0] dbus_data_reg;
reg [EBUS_DATA_SIZE-1:0] ebus_data_reg;
reg dma_request;
reg write_request;
reg read_request;
reg [SYS_AD_SIZE-1:0] sys_ad_in;
reg [SYS_AD_SIZE-1:0] sys_ad_out;
reg [SYS_CMD_SIZE-1:0] sys_cmd_in;
reg [SYS_CMD_SIZE-1:0] sys_cmd_out;
reg e_valid_l;
reg e_ok_l;
reg int_l;
reg sys_ad_enable;

// internal registers
reg [SYS_AD_SIZE-1:0] sys_address;
reg p_valid_l_d1;
reg e_ok_l_d1, e_ok_l_d2;
reg write_transaction;
reg block_transaction;
reg [SYS_CMD_BLOCK_SIZE-1:0] transaction_size;
reg dbus_transfer;
reg cbus_transfer;
reg mi_transfer;
reg dma_start_d1;
reg read_pending;
reg write_pending;
reg init_mode;
reg [DMA_LENGTH_SIZE-1:0] init_length;
reg dp_mask;
reg pi_mask;
reg vi_mask;
reg ai_mask;
reg si_mask;
reg sp_mask;
reg increment_write_address;
reg [COUNTER_SIZE-1:0] counter;
reg ebus_test_mode;
reg pipe_busy_d1;
reg dp_interrupt;
reg rdram_reg_mode;

// memory interface registers
reg write_buffer_0;
reg write_buffer_1;
reg [BUFFER_ADDRESS_SIZE-1:0] read_address;
reg [BUFFER_ADDRESS_SIZE-1:0] write_address;

// various busses
wire sys_cmd_data;
wire sys_cmd_write;
wire sys_cmd_block;
wire [SYS_CMD_BLOCK_SIZE-1:0] sys_cmd_block_size;
wire sys_cmd_more;
wire [MI_REG_ADDRESS_SIZE-1:0] reg_address;
wire [BUFFER_DATA_SIZE-1:0] read_data_0, read_data_1;
wire [DBUS_DATA_SIZE/2-1:0] dbus_data_0, dbus_data_1;
wire [EBUS_DATA_SIZE/2-1:0] ebus_data_0, ebus_data_1;


// BUS state machine
reg [3:0] bus_state;
parameter
	STATE_BUS_IDLE					= 0,
	STATE_BUS_WRITE_1				= 1,
	STATE_BUS_WRITE_2				= 2,
	STATE_BUS_WRITE_3				= 3,
	STATE_BUS_WRITE_4				= 4,
	STATE_BUS_WRITE_5				= 5,
	STATE_BUS_WRITE_6				= 6,
	STATE_BUS_WRITE_7				= 7,
	STATE_BUS_WRITE_8				= 8,
	STATE_BUS_READ_1				= 9,
	STATE_BUS_READ_2				= 10,
	STATE_BUS_READ_3				= 11,
	STATE_BUS_READ_4				= 12,
	STATE_BUS_READ_5				= 13,
	STATE_BUS_READ_6				= 14;

// DMA state machine
reg [1:0] dma_state;
parameter
	STATE_DMA_IDLE				= 0,
	STATE_DMA_WRITE			= 1,
	STATE_DMA_READ				= 2;


// tristate drivers
cbus_driver cbus_driver_0(cbus_data_reg, cbus_write_enable, cbus_data);
dbus_driver dbus_driver_0(dbus_data_reg, dbus_write_enable, dbus_data);
ebus_driver ebus_driver_0(ebus_data_reg, dbus_write_enable, ebus_data);

assign sys_ad_enable_l = ~{5{sys_ad_enable}};
assign sys_cmd_out_h = sys_cmd_out;
assign sys_ad_out_h = sys_ad_out;

assign {sys_cmd_data, sys_cmd_write, sys_cmd_block, sys_cmd_block_size}
   = sys_cmd_in;
assign sys_cmd_more = sys_cmd_in[SYS_CMD_MORE];
assign reg_address = sys_address >> IO_OFFSET_SIZE;

assign {dbus_data_0, dbus_data_1} = dbus_data_reg;
assign {ebus_data_0, ebus_data_1} = ebus_data_reg;

always @(posedge clock) begin
	dbus_data_reg <= dbus_read_enable ? dbus_data : {read_data_0, read_data_1};
	ebus_data_reg <= dbus_read_enable
	  ? ebus_data
	  : ebus_test_mode
	    ? {read_data_0[3:0], read_data_1[3:0]}
		 : {{2{read_data_0[16]}}, {2{read_data_0[0]}},
		    {2{read_data_1[16]}}, {2{read_data_1[0]}}};
	end

mi_buffer mi_buffer_0(clock, dbus_data_0, ebus_data_0, sys_ad_in,
  write_buffer_0, write_transaction, read_address, write_address,
  ebus_test_mode, read_data_0);

mi_buffer mi_buffer_1(clock, dbus_data_1, ebus_data_1, sys_ad_in,
  write_buffer_1, write_transaction, read_address, write_address,
  ebus_test_mode, read_data_1);

// synopsys translate_off
integer log_file;
initial log_file = 0;
// synopsys translate_on


always @(posedge clock) begin : cbus_data_block
	reg [CBUS_DATA_SIZE-1:0] cbus_data_out;
	reg [DMA_LENGTH_SIZE-1:0] length;

	sys_ad_in <= sys_ad_in_h;
	sys_cmd_in <= sys_cmd_in_h;
	p_valid_l_d1 <= p_valid_l;
	dma_start_d1 <= dma_start;
	e_ok_l_d2 <= e_ok_l_d1;
	e_ok_l_d1 <= e_ok_l;
	pipe_busy_d1 <= pipe_busy;

	// decode the transfer length in bytes
	case ({block_transaction, transaction_size})
		0 : length = 0;
		1 : length = 1;
		2 : length = 2;
		3 : length = 3;
		4 : length = 7;
		5 : length = 15;
		6 : length = 31;
		default : length = 'bx;
		endcase

	if (init_mode) begin
		length = init_length;
		end
	else if (!block_transaction) begin
		length = length + sys_address[2:0];
		end

	case (cbus_select)
		CBUS_ADDRESS_SELECT : cbus_data_out = sys_address;

		CBUS_LENGTH_SELECT :
			case ({block_transaction, write_transaction})
				2'b00 : cbus_data_out = {DMA_BLOCK, DMA_NON_MASKED, DMA_UP,
				  DMA_SEQ, BUS_DEVICE_MI, READ_DELAY, DMA_READ, length};

				2'b01 : cbus_data_out = {DMA_BLOCK, DMA_NON_MASKED, DMA_UP,
				  DMA_SEQ, BUS_DEVICE_MI, WRITE_DELAY, DMA_WRITE, length};

				2'b10 : cbus_data_out = {DMA_SUBBLOCK, DMA_NON_MASKED, DMA_UP,
				  DMA_NSEQ, BUS_DEVICE_MI, READ_DELAY, DMA_READ, length};

				2'b11 : cbus_data_out = {DMA_BLOCK, DMA_NON_MASKED, DMA_UP,
				  DMA_SEQ, BUS_DEVICE_MI, WRITE_DELAY, DMA_WRITE, length};

				default : cbus_data_out = 'bx;
				endcase

		CBUS_DATA_SELECT : cbus_data_out = read_data_0;

		default : cbus_data_out = 'bx;
		endcase

	cbus_command_reg <= cbus_command;
	cbus_data_reg <= cbus_read_enable ? cbus_data : cbus_data_out;
	end


always @(posedge clock or negedge reset_l) begin
	if (!reset_l) begin
		// resetable registers
		dma_request <= LOW;
		write_request <= LOW;
		read_request <= LOW;
		e_valid_l <= HIGH;
		sys_ad_enable <= LOW;
		e_ok_l <= HIGH;
		int_l <= HIGH;
		read_pending <= LOW;
		write_pending <= LOW;
		init_mode <= LOW;
		dp_mask <= LOW;
		pi_mask <= LOW;
		vi_mask <= LOW;
		ai_mask <= LOW;
		si_mask <= LOW;
		sp_mask <= LOW;
		increment_write_address <= LOW;
		write_buffer_0 <= LOW;
		write_buffer_1 <= LOW;
		read_address <= 0;
		write_address <= 0;
		ebus_test_mode <= LOW;
		dp_interrupt <= LOW;
		rdram_reg_mode <= LOW;

		// non-resetable registers
		sys_ad_out <= 'bx;
		sys_cmd_out <= 'bx;
		sys_address <= 0;
		write_transaction <= 0;
		block_transaction <= 0;
		transaction_size <= 0;
		dbus_transfer <= 0;
		cbus_transfer <= 0;
		mi_transfer <= 0;
		init_length <= 0;
		counter <= 0;

		// state register
		bus_state <= STATE_BUS_IDLE;
		dma_state <= STATE_DMA_IDLE;
		end
	else begin : main_block
		reg increment_read_address;
		reg decrement_counter;
		reg next_increment_write_address;
		reg next_write_buffer_0;
		reg next_write_buffer_1;
		reg next_e_ok_l;
		reg next_e_valid_l;
		reg next_dma_request;
		reg next_write_request;
		reg next_read_request;
		reg next_sys_ad_enable;
		reg [SYS_AD_SIZE-1:0] next_sys_ad_out;
		reg [SYS_CMD_SIZE-1:0] next_sys_cmd_out;
		reg [BUFFER_ADDRESS_SIZE-1:0] next_read_address;
		reg [BUFFER_ADDRESS_SIZE-1:0] next_write_address;
		reg next_dbus_transfer;
		reg next_cbus_transfer;
		reg next_mi_transfer;
		reg [CBUS_DATA_SIZE-1:0] reg_read_data;
		reg set_ebus_test_mode, clear_ebus_test_mode;
		reg set_rdram_reg_mode, clear_rdram_reg_mode;
		reg set_init_mode, clear_init_mode;
		reg [DMA_LENGTH_SIZE-1:0] next_init_length;
		reg set_dp_mask, clear_dp_mask;
		reg set_pi_mask, clear_pi_mask;
		reg set_vi_mask, clear_vi_mask;
		reg set_ai_mask, clear_ai_mask;
		reg set_si_mask, clear_si_mask;
		reg set_sp_mask, clear_sp_mask;
		reg set_dp_interrupt, clear_dp_interrupt;
      reg [BUS_ID_SIZE-1:0] next_id;

		increment_read_address = LOW;
		decrement_counter = LOW;
		next_increment_write_address = LOW;
		next_write_buffer_0 = LOW;
		next_write_buffer_1 = LOW;
		next_e_ok_l = HIGH;
		next_e_valid_l = HIGH;
		next_dma_request = LOW;
		next_read_request = LOW;
		next_write_request = LOW;
		next_sys_ad_enable = LOW;
		next_sys_ad_out = 'bx;
		next_sys_cmd_out = 'bx;
		next_read_address = read_address + 1;
		next_write_address = write_address + 1;
		next_init_length = 'bx;

		set_ebus_test_mode = LOW;
		clear_ebus_test_mode = LOW;
		set_rdram_reg_mode = LOW;
		clear_rdram_reg_mode = LOW;
		set_init_mode = LOW;
		clear_init_mode = LOW;
		set_dp_mask = LOW;
		clear_dp_mask = LOW;
		set_pi_mask = LOW;
		clear_pi_mask = LOW;
		set_vi_mask = LOW;
		clear_vi_mask = LOW;
		set_ai_mask = LOW;
		clear_ai_mask = LOW;
		set_si_mask = LOW;
		clear_si_mask = LOW;
		set_sp_mask = LOW;
		clear_sp_mask = LOW;
		set_dp_interrupt = !pipe_busy && pipe_busy_d1;
		clear_dp_interrupt = LOW;

      next_id = sys_ad_in >> BUS_ID_OFFSET;
		next_dbus_transfer = next_id < BUS_ID_CBUS_START;
		next_mi_transfer = next_id == BUS_ID_MI;
		next_cbus_transfer = next_id < BUS_ID_EXT_START
		  && !next_mi_transfer && !next_dbus_transfer;

		case (reg_address)
			INIT_MODE_ADDRESS: reg_read_data = {rdram_reg_mode,
			  ebus_test_mode, init_mode, init_length};
			VERSION_ADDRESS : reg_read_data = version;
			INTERRUPT_ADDRESS : reg_read_data
			  = {dp_interrupt, pi_interrupt, vi_interrupt, ai_interrupt,
			     si_interrupt, sp_interrupt};
			MASK_ADDRESS : reg_read_data
			  = {dp_mask, pi_mask, vi_mask, ai_mask, si_mask, sp_mask};
			default : reg_read_data = 'bx;
		endcase

		case (bus_state)
			STATE_BUS_IDLE : begin
				if (p_valid_l_d1) begin
					// SysAD idle
					next_e_ok_l = LOW;
					bus_state <= STATE_BUS_IDLE;
					end
				else begin
					// SysAD transaction requested
					write_transaction <= sys_cmd_write;
					block_transaction <= sys_cmd_block;
					transaction_size <= sys_cmd_block_size;
					dbus_transfer <= next_dbus_transfer;
					cbus_transfer <= next_cbus_transfer;
					mi_transfer <= next_mi_transfer;

					if (sys_cmd_data) begin
						// middle of a canceled cycle
						next_e_ok_l = LOW;
						bus_state <= STATE_BUS_IDLE;
						end
					else if (sys_cmd_write) begin
						sys_address <= sys_ad_in;

						if (e_ok_l) begin
							// command issued in two cycles.
							next_e_ok_l = LOW;
							bus_state <= STATE_BUS_WRITE_1;
							end
						else if (e_ok_l_d1) begin
							// command issued on the next cycle
							next_e_ok_l = LOW;
							bus_state <= STATE_BUS_WRITE_2;
							end
						else if (e_ok_l_d2) begin
							// command issued this cycle
							if (!next_dbus_transfer && !next_cbus_transfer) begin
								next_e_ok_l = LOW;
								end

							bus_state <= STATE_BUS_WRITE_3;
							end
						else begin
							// command already issued
							next_write_buffer_0 = HIGH;
							next_write_buffer_1 = HIGH;

							if (!next_dbus_transfer && !next_cbus_transfer) begin
								next_e_ok_l = LOW;
								end

							bus_state <= STATE_BUS_WRITE_4;
							end
						end
					else begin
						next_e_ok_l = LOW;
						sys_address <= sys_ad_in;

						if (next_dbus_transfer) begin
							// dbus read
							next_dma_request = HIGH;
							end
						else if (sys_cmd_block) begin
							// multiword cbus read
							$display("%m: Panic!  non-dbus block read not supported");
							$finish;
							end
						else if (next_cbus_transfer) begin
							// one word cbus read
							next_read_request = HIGH;
							end

						if (e_ok_l) begin
							// command issued in two cycles.
							bus_state <= STATE_BUS_READ_1;
							end
						else if (e_ok_l_d1) begin
							// command issued on the next cycle
							bus_state <= STATE_BUS_READ_2;
							end
						else if (e_ok_l_d2) begin
							// command issued this cycle
							bus_state <= STATE_BUS_READ_3;
							end
						else begin
							// command already issued
							if (next_dbus_transfer || next_cbus_transfer
							  || next_mi_transfer) begin
								next_sys_ad_enable = HIGH;
								end
							bus_state <= STATE_BUS_READ_3;
							end
						end
					end
				end

			STATE_BUS_WRITE_1 : begin
				next_e_ok_l = LOW;
				bus_state <= STATE_BUS_WRITE_2;
				end

			STATE_BUS_WRITE_2 : begin
				if (!dbus_transfer && !cbus_transfer) begin
					next_e_ok_l = LOW;
					end
				bus_state <= STATE_BUS_WRITE_3;
				end

			STATE_BUS_WRITE_3 : begin
				next_write_buffer_0 = HIGH;
				next_write_buffer_1 = HIGH;
				if (!dbus_transfer && !cbus_transfer) begin
					next_e_ok_l = LOW;
					end
				bus_state <= STATE_BUS_WRITE_4;
				end

			STATE_BUS_WRITE_4 : begin
				if (dbus_transfer) begin
					next_increment_write_address = HIGH;
					if (sys_cmd_more) begin
						next_write_buffer_1 = HIGH;
						bus_state <= STATE_BUS_WRITE_5;
						end
					else begin
						next_dma_request = HIGH;
						bus_state <= STATE_BUS_WRITE_6;
						end
					end
				else if (cbus_transfer) begin
					if (cbus_grant) begin
						next_e_ok_l = LOW;
						bus_state <= STATE_BUS_IDLE;
						end
					else begin
						next_write_request = HIGH;
						bus_state <= STATE_BUS_WRITE_4;
						end
					end
				else begin
					next_e_ok_l = LOW;
					if (mi_transfer) begin
						case (reg_address)
							INIT_MODE_ADDRESS: {
							  set_rdram_reg_mode, clear_rdram_reg_mode,
							  clear_dp_interrupt,
							  set_ebus_test_mode, clear_ebus_test_mode,
							  set_init_mode, clear_init_mode,
							  next_init_length } = sys_ad_in;
							MASK_ADDRESS: {
							  set_dp_mask, clear_dp_mask,
							  set_pi_mask, clear_pi_mask,
							  set_vi_mask, clear_vi_mask,
							  set_ai_mask, clear_ai_mask,
							  set_si_mask, clear_si_mask,
							  set_sp_mask, clear_sp_mask } = sys_ad_in;
							endcase
						end
					// synopsys translate_off
					else begin
						if (!log_file) begin
							log_file = $fopen("rcp.log");
							end
						$fdisplay(log_file, "%h @ %h", sys_ad_in, sys_address);
						end
					// synopsys translate_on
					bus_state <= STATE_BUS_IDLE;
					end
				end

			STATE_BUS_WRITE_5 : begin
				if (sys_cmd_more) begin
					next_write_buffer_0 = HIGH;
					bus_state <= STATE_BUS_WRITE_4;
					end
				else begin
					next_dma_request = HIGH;
					bus_state <= STATE_BUS_WRITE_6;
					end
				end

			STATE_BUS_WRITE_6 : begin
				if (cbus_grant) begin
					if (write_pending) begin
						$display("%m: Panic!  Multiple MI write DMAs");
						$finish;
						end
					else begin
						write_pending <= HIGH;
						end
					bus_state <= STATE_BUS_WRITE_7;
					end
				else begin
					next_dma_request = HIGH;
					bus_state <= STATE_BUS_WRITE_6;
					end
				end

			STATE_BUS_WRITE_7 : begin
				if (dma_start) begin
					if (!init_mode || dma_last) begin
						next_e_ok_l = LOW;
						clear_init_mode = HIGH;
						bus_state <= STATE_BUS_IDLE;
						end
					else begin
						bus_state <= STATE_BUS_WRITE_8;
						end
					end
				else begin
					bus_state <= STATE_BUS_WRITE_7;
					end
				end

			STATE_BUS_WRITE_8 : begin
				if (dma_last) begin
					next_e_ok_l = LOW;
					clear_init_mode = HIGH;
					bus_state <= STATE_BUS_IDLE;
					end
				else begin
					bus_state <= STATE_BUS_WRITE_8;
					end
				end

			STATE_BUS_READ_1 : begin
				next_e_ok_l = LOW;

				if (dbus_transfer) begin
					// dbus read
					next_dma_request = HIGH;
					end
				else if (cbus_transfer) begin
					// one word cbus read
					next_read_request = HIGH;
					end

				bus_state <= STATE_BUS_READ_2;
				end

			STATE_BUS_READ_2 : begin
				next_e_ok_l = LOW;

				if (dbus_transfer) begin
					// dbus read
					if (cbus_grant) begin
						bus_state <= STATE_BUS_READ_4;
						end
					else begin
						next_dma_request = HIGH;
						bus_state <= STATE_BUS_READ_3;
						end
					end
				else if (cbus_transfer) begin
					// cbus read
					if (cbus_grant) begin
						bus_state <= STATE_BUS_READ_4;
						end
					else begin
						next_read_request = HIGH;
						bus_state <= STATE_BUS_READ_3;
						end
					end
				else begin
					// MI register read
					bus_state <= STATE_BUS_READ_3;
					end
				end

			STATE_BUS_READ_3 : begin
				next_e_ok_l = LOW;

				if (dbus_transfer) begin
					// dbus read
					next_sys_ad_enable = HIGH;
					if (cbus_grant) begin
						if (read_pending) begin
							$display("%m: Panic!  Multiple MI read DMAs");
							$finish;
							end
						else begin
							read_pending <= HIGH;
							end
						bus_state <= STATE_BUS_READ_4;
						end
					else begin
						next_dma_request = HIGH;
						bus_state <= STATE_BUS_READ_3;
						end
					end
				else if (cbus_transfer) begin
					// cbus read
					next_sys_ad_enable = HIGH;
					if (cbus_grant) begin
						bus_state <= STATE_BUS_READ_4;
						end
					else begin
						next_read_request = HIGH;
						bus_state <= STATE_BUS_READ_3;
						end
					end
				else if (mi_transfer) begin
					// MI register read
					next_sys_ad_enable = HIGH;
					next_sys_ad_out = reg_read_data;
					next_sys_cmd_out = SYS_CMD_DATA_LAST;
					next_e_valid_l = LOW;
					bus_state <= STATE_BUS_IDLE;
					end
				else begin
					// external read
					decrement_counter = HIGH;
					if (counter) begin
						bus_state <= STATE_BUS_READ_3;
						end
					else begin
						next_e_valid_l = LOW;
						bus_state <= STATE_BUS_IDLE;
						end
					end
				end

			STATE_BUS_READ_4 : begin
				next_e_ok_l = LOW;
				next_sys_ad_enable = HIGH;

				if (dbus_transfer) begin
					// dbus read
					if (dma_start_d1) begin
					 	next_e_valid_l = LOW;
						if (sys_address[2] && !rdram_reg_mode) begin
							// read odd word
							next_sys_ad_out = read_data_1;
							end
						else begin
							// read even word
							next_sys_ad_out = read_data_0;
							end

						if (block_transaction) begin
							// block read
							next_sys_cmd_out = SYS_CMD_DATA_NEXT;
							bus_state <= STATE_BUS_READ_5;
							end
						else begin
							// one word read
							increment_read_address = HIGH;
							next_sys_cmd_out = SYS_CMD_DATA_LAST;
							bus_state <= STATE_BUS_IDLE;
							end
						end
					else begin
						bus_state <= STATE_BUS_READ_4;
						end
					end
				else begin
					// cbus read
					next_sys_ad_out = cbus_data_reg;
					next_sys_cmd_out = SYS_CMD_DATA_LAST;
					if (cbus_command_reg == CBUS_RESPONSE_COMMAND) begin
						next_e_valid_l = LOW;
						bus_state <= STATE_BUS_IDLE;
						end
					else begin
						bus_state <= STATE_BUS_READ_4;
						end
					end
				end

			STATE_BUS_READ_5 : begin
			 	next_e_valid_l = LOW;
				next_e_ok_l = LOW;
				next_sys_ad_enable = HIGH;
				increment_read_address = HIGH;
				decrement_counter = HIGH;

				if (sys_address[2]) begin
					// read even word
					next_sys_ad_out = read_data_0;
					end
				else begin
					// read odd word
					next_sys_ad_out = read_data_1;
					end

				if (counter) begin
					next_sys_cmd_out = SYS_CMD_DATA_NEXT;
					bus_state <= STATE_BUS_READ_6;
					end
				else begin
					next_sys_cmd_out = SYS_CMD_DATA_LAST;
					bus_state <= STATE_BUS_IDLE;
					end
				end

			STATE_BUS_READ_6 : begin
			 	next_e_valid_l = LOW;
				next_e_ok_l = LOW;
				next_sys_ad_enable = HIGH;
				next_sys_cmd_out = SYS_CMD_DATA_NEXT;
				decrement_counter = HIGH;

				if (sys_address[2]) begin
					// read odd word
					next_sys_ad_out = read_data_1;
					end
				else begin
					// read even word
					next_sys_ad_out = read_data_0;
					end

				bus_state <= STATE_BUS_READ_5;
				end

			default : begin
				sys_address <= 'bx;
				bus_state <= 'bx;

				$display("%m: Panic!  MI bus state unknown");
				$finish;
				end
			endcase


		case (dma_state)
			STATE_DMA_IDLE : begin
				if (dma_start && write_pending) begin
					increment_read_address = HIGH;
					write_pending <= LOW;
					if (dma_last) begin
						dma_state <= STATE_DMA_IDLE;
						end
					else begin
						dma_state <= STATE_DMA_WRITE;
						end
					end
				else if (dma_start && read_pending) begin
					next_write_buffer_0 = HIGH;
					next_write_buffer_1 = HIGH;
					next_increment_write_address = HIGH;
					read_pending <= LOW;
					if (dma_last) begin
						dma_state <= STATE_DMA_IDLE;
						end
					else begin
						dma_state <= STATE_DMA_READ;
						end
					end
				else begin
					dma_state <= STATE_DMA_IDLE;
					end
				end

			STATE_DMA_WRITE : begin
				increment_read_address = HIGH;
				if (dma_last) begin
					dma_state <= STATE_DMA_IDLE;
					end
				else begin
					dma_state <= STATE_DMA_WRITE;
					end
				end

			STATE_DMA_READ : begin
				next_write_buffer_0 = HIGH;
				next_write_buffer_1 = HIGH;
				next_increment_write_address = HIGH;
				if (dma_last) begin
					dma_state <= STATE_DMA_IDLE;
					end
				else begin
					dma_state <= STATE_DMA_READ;
					end
				end

			default : begin
				dma_state <= 'bx;

				$display("%m: Panic!  MI DMA state unknown");
				$finish;
				end
			endcase

		e_valid_l <= next_e_valid_l;
		e_ok_l <= next_e_ok_l;
		sys_ad_enable <= next_sys_ad_enable;
		dma_request <= next_dma_request;
		read_request <= next_read_request;
		write_request <= next_write_request;
		sys_ad_out <= next_sys_ad_out;
		sys_cmd_out <= next_sys_cmd_out;
		increment_write_address <= next_increment_write_address;

		write_buffer_0 <= next_write_buffer_0;
		write_buffer_1 <= next_write_buffer_1;

		case ({set_ebus_test_mode, clear_ebus_test_mode})
			2'b10 : ebus_test_mode <= HIGH;
			2'b01 : ebus_test_mode <= LOW;
			endcase

		case ({set_rdram_reg_mode, clear_rdram_reg_mode})
			2'b10 : rdram_reg_mode <= HIGH;
			2'b01 : rdram_reg_mode <= LOW;
			endcase

		case ({set_init_mode, clear_init_mode})
			2'b10 : begin
				init_mode <= HIGH;
				init_length <= next_init_length;
				end
			2'b01 : init_mode <= LOW;
			endcase

		case ({set_dp_mask, clear_dp_mask})
			2'b10 : dp_mask <= HIGH;
			2'b01 : dp_mask <= LOW;
			endcase

		case ({set_pi_mask, clear_pi_mask})
			2'b10 : pi_mask <= HIGH;
			2'b01 : pi_mask <= LOW;
			endcase

		case ({set_vi_mask, clear_vi_mask})
			2'b10 : vi_mask <= HIGH;
			2'b01 : vi_mask <= LOW;
			endcase

		case ({set_ai_mask, clear_ai_mask})
			2'b10 : ai_mask <= HIGH;
			2'b01 : ai_mask <= LOW;
			endcase

		case ({set_si_mask, clear_si_mask})
			2'b10 : si_mask <= HIGH;
			2'b01 : si_mask <= LOW;
			endcase

		case ({set_sp_mask, clear_sp_mask})
			2'b10 : sp_mask <= HIGH;
			2'b01 : sp_mask <= LOW;
			endcase

		case ({set_dp_interrupt, clear_dp_interrupt})
			2'b10 : dp_interrupt <= HIGH;
			2'b01 : dp_interrupt <= LOW;
			endcase

		int_l <= 
		  !(   (dp_mask && dp_interrupt)
		    || (pi_mask && pi_interrupt)
		    || (vi_mask && vi_interrupt)
		    || (ai_mask && ai_interrupt)
		    || (si_mask && si_interrupt)
		    || (sp_mask && sp_interrupt) );

		if (!init_mode && increment_write_address) begin
			write_address <= next_write_address;
			end

		if (!init_mode && increment_read_address) begin
			read_address <= next_read_address;
			end

		if (decrement_counter) begin
			counter <= counter - 1;
			end
		else if (dbus_transfer) begin
			case (transaction_size)
				0 : counter <= 0;
				1 : counter <= 2;
				2 : counter <= 6;
				default : counter <= 'bx;
				endcase
			end
		else begin
			counter <= -1;
			end
		end
	end
endmodule


module mi_buffer(clock, dbus_data, ebus_data, sys_ad, write_enable,
  write_transaction, read_address, write_address, ebus_test_mode, read_data);

`include "rcp.vh"

// IO buffer
parameter
	BUFFER_DATA_SIZE = 32,
	BUFFER_ADDRESS_SIZE = 2;

input clock;
input [DBUS_DATA_SIZE/2-1:0] dbus_data;
input [EBUS_DATA_SIZE/2-1:0] ebus_data;
input [SYS_AD_SIZE-1:0] sys_ad;
input write_enable;
input write_transaction;
input [BUFFER_ADDRESS_SIZE-1:0] read_address;
input [BUFFER_ADDRESS_SIZE-1:0] write_address;
input ebus_test_mode;
output [BUFFER_DATA_SIZE-1:0] read_data;

reg [BUFFER_DATA_SIZE/2-1:0] latch_0_l, latch_0_h;
reg [BUFFER_DATA_SIZE/2-1:0] latch_1_l, latch_1_h;
reg [BUFFER_DATA_SIZE/2-1:0] latch_2_l, latch_2_h;
reg [BUFFER_DATA_SIZE/2-1:0] latch_3_l, latch_3_h;

wire [BUFFER_DATA_SIZE/2-1:0] write_data_l, write_data_h;
reg [BUFFER_DATA_SIZE-1:0] read_data;
wire write_0, write_1, write_2, write_3;
wire enable_0, enable_1, enable_2, enable_3;
wire enable_0n, enable_1n, enable_2n, enable_3n;

assign {write_data_l, write_data_h} = write_transaction
  ? sys_ad
  : ebus_test_mode
    ? ebus_data
    : dbus_data;

always @(
  latch_0_l or latch_0_h or
  latch_1_l or latch_1_h or
  latch_2_l or latch_2_h or
  latch_3_l or latch_3_h or
  read_address) begin

	case (read_address)
		0 : read_data = {latch_0_l, latch_0_h};
		1 : read_data = {latch_1_l, latch_1_h};
		2 : read_data = {latch_2_l, latch_2_h};
		3 : read_data = {latch_3_l, latch_3_h};
		endcase
	end

assign write_0 = !(write_enable && (write_address == 0));
assign write_1 = !(write_enable && (write_address == 1));
assign write_2 = !(write_enable && (write_address == 2));
assign write_3 = !(write_enable && (write_address == 3));

nr02d2
	g_0_l(.a1(write_0), .a2(clock), .zn(enable_0_l)),
	g_0_h(.a1(write_0), .a2(clock), .zn(enable_0_h)),
	g_1_l(.a1(write_1), .a2(clock), .zn(enable_1_l)),
	g_1_h(.a1(write_1), .a2(clock), .zn(enable_1_h)),
	g_2_l(.a1(write_2), .a2(clock), .zn(enable_2_l)),
	g_2_h(.a1(write_2), .a2(clock), .zn(enable_2_h)),
	g_3_l(.a1(write_3), .a2(clock), .zn(enable_3_l)),
	g_3_h(.a1(write_3), .a2(clock), .zn(enable_3_h));


always @(enable_0_l or write_data_l) begin
	if (enable_0_l) latch_0_l = write_data_l;
	end

always @(enable_0_h or write_data_h) begin
	if (enable_0_h) latch_0_h = write_data_h;
	end

always @(enable_1_l or write_data_l) begin
	if (enable_1_l) latch_1_l = write_data_l;
	end

always @(enable_1_h or write_data_h) begin
	if (enable_1_h) latch_1_h = write_data_h;
	end

always @(enable_2_l or write_data_l) begin
	if (enable_2_l) latch_2_l = write_data_l;
	end

always @(enable_2_h or write_data_h) begin
	if (enable_2_h) latch_2_h = write_data_h;
	end

always @(enable_3_l or write_data_l) begin
	if (enable_3_l) latch_3_l = write_data_l;
	end

always @(enable_3_h or write_data_h) begin
	if (enable_3_h) latch_3_h = write_data_h;
	end

endmodule