/*****************************************************************************/
/* custom variables                                                          */
/*****************************************************************************/
module = "ms"
wire_load = 256000
standard_load = 0.01
clock = "clock"
clocks = { clock gclock }
default_input_delay = 1.5
default_output_delay = 13.0
default_input_load = 20
default_output_load = 20
default_drive_cell = "dfntnh"
default_drive_pin = "q"
default_period = 16.0
default_max_transition = 1.5
default_uncertainty = 1.0


/*****************************************************************************/
/* set the path and read                                                     */
/*****************************************************************************/
search_path = search_path \
   + "../src" \
   + "../../inc" \
   + "../../../lib/verilog/user" \
   + "../../syn"

read -f verilog dbus_driver.v
read -f verilog ebus_driver.v
read -f verilog tmem_driver.v
read -f edif ms_dma.edf
read -f edif ms_rand.edf
read -f edif ms_rp.edf
read -f edif ms_sc.edf
read -f edif ms_si.edf
read -f edif ms_sm.edf
read -f edif ms_debug.edf
read -f verilog module + .v

current_design = module


/*****************************************************************************/
/* default environment                                                       */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top


/*****************************************************************************/
/* clock constraints                                                         */
/*****************************************************************************/
create_clock clocks -period default_period -waveform { 0.0 default_period / 2 }
set_clock_skew -propagated -uncertainty default_uncertainty clocks
set_dont_touch_network clocks


/*****************************************************************************/
/* default constraints                                                       */
/*****************************************************************************/
set_max_area 0
set_dont_touch { ne35hd130d/nt01d* }

set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null

set_drive 0 { clocks }
set_input_delay 0 { clocks }

set_max_transition default_max_transition current_design


/*****************************************************************************/
/* custom constraints                                                        */
/*****************************************************************************/
set_driving_cell -cell ni01d5 { cbus_read_enable cbus_write_enable }

set_driving_cell -cell nt01d4 { cbus_data }
set_load 200 * standard_load { cbus_data dbus_data ebus_data }
set_input_delay 2.0 -clock clock { cbus_data }
set_output_delay 4.0 -clock clock { cbus_data }

set_driving_cell -cell ni01d5 { cbus_command cbus_select }
set_load 100 * standard_load { cbus_command cbus_select }
set_max_fanout 10 * standard_load { cbus_command cbus_select }

set_driving_cell -cell ni01d5 { dma_read_enable dma_write_enable }

set_driving_cell -cell nt01d4 { cbus_data dbus_data ebus_data }
set_load 200 * standard_load { cbus_data dbus_data ebus_data }
set_input_delay 2.0 -clock clock { cbus_data dbus_data ebus_data }
set_output_delay 4.0 -clock clock { cbus_data dbus_data ebus_data }

set_driving_cell -cell ni01d5 { start finish }
set_load 100 * standard_load { start finish }
set_max_fanout 10 * standard_load { start finish }

remove_output_delay { stopgclock }

set_load 150 * standard_load \
   { start_gclk pipe_busy load_dv bist_done bist_go bist_check }

set_output_delay 11.0 -clock clock \
   { pipe_busy load_dv bist_done bist_go bist_check }

set_output_delay 4.0 -clock clock { start_gclk }
set_max_transition 1.0 { start_gclk }

set_output_delay 12.0 -clock clock { rdramreq }
set_output_delay 12.0 -clock clock { copy_load }
set_output_delay 12.0 -clock clock { rdpralpha }
set_output_delay 12.0 -clock clock { rdramrw }

set_load 0.50 { we0d we1d addr0d[*] addr1d[*] dind[*] }

set_false_path -fall -from reset_l
set_max_fanout 2 * standard_load reset_l

set_disable_timing sb0 -from di[0] -to dout[0]
set_disable_timing sb0 -from di[1] -to dout[1]
set_disable_timing sb0 -from di[2] -to dout[2]
set_disable_timing sb0 -from di[3] -to dout[3]
set_disable_timing sb0 -from di[4] -to dout[4]
set_disable_timing sb0 -from di[5] -to dout[5]
set_disable_timing sb0 -from di[6] -to dout[6]
set_disable_timing sb0 -from di[7] -to dout[7]
set_disable_timing sb0 -from di[8] -to dout[8]
set_disable_timing sb0 -from di[9] -to dout[9]
set_disable_timing sb0 -from di[10] -to dout[10]
set_disable_timing sb0 -from di[11] -to dout[11]
set_disable_timing sb0 -from di[12] -to dout[12]
set_disable_timing sb0 -from di[13] -to dout[13]
set_disable_timing sb0 -from di[14] -to dout[14]
set_disable_timing sb0 -from di[15] -to dout[15]
set_disable_timing sb0 -from di[16] -to dout[16]
set_disable_timing sb0 -from di[17] -to dout[17]
set_disable_timing sb0 -from di[18] -to dout[18]
set_disable_timing sb0 -from di[19] -to dout[19]
set_disable_timing sb0 -from di[20] -to dout[20]
set_disable_timing sb0 -from di[21] -to dout[21]
set_disable_timing sb0 -from di[22] -to dout[22]
set_disable_timing sb0 -from di[23] -to dout[23]
set_disable_timing sb0 -from di[24] -to dout[24]
set_disable_timing sb0 -from di[25] -to dout[25]
set_disable_timing sb0 -from di[26] -to dout[26]
set_disable_timing sb0 -from di[27] -to dout[27]
set_disable_timing sb0 -from di[28] -to dout[28]
set_disable_timing sb0 -from di[29] -to dout[29]
set_disable_timing sb0 -from di[30] -to dout[30]
set_disable_timing sb0 -from di[31] -to dout[31]
set_disable_timing sb0 -from di[32] -to dout[32]
set_disable_timing sb0 -from di[33] -to dout[33]
set_disable_timing sb0 -from di[34] -to dout[34]
set_disable_timing sb0 -from di[35] -to dout[35]
set_disable_timing sb0 -from di[36] -to dout[36]
set_disable_timing sb0 -from di[37] -to dout[37]
set_disable_timing sb0 -from di[38] -to dout[38]
set_disable_timing sb0 -from di[39] -to dout[39]
set_disable_timing sb0 -from di[40] -to dout[40]
set_disable_timing sb0 -from di[41] -to dout[41]
set_disable_timing sb0 -from di[42] -to dout[42]
set_disable_timing sb0 -from di[43] -to dout[43]
set_disable_timing sb0 -from di[44] -to dout[44]
set_disable_timing sb0 -from di[45] -to dout[45]
set_disable_timing sb0 -from di[46] -to dout[46]
set_disable_timing sb0 -from di[47] -to dout[47]
set_disable_timing sb0 -from di[48] -to dout[48]
set_disable_timing sb0 -from di[49] -to dout[49]
set_disable_timing sb0 -from di[50] -to dout[50]
set_disable_timing sb0 -from di[51] -to dout[51]
set_disable_timing sb0 -from di[52] -to dout[52]
set_disable_timing sb0 -from di[53] -to dout[53]
set_disable_timing sb0 -from di[54] -to dout[54]
set_disable_timing sb0 -from di[55] -to dout[55]
set_disable_timing sb0 -from di[56] -to dout[56]
set_disable_timing sb0 -from di[57] -to dout[57]
set_disable_timing sb0 -from di[58] -to dout[58]
set_disable_timing sb0 -from di[59] -to dout[59]
set_disable_timing sb0 -from di[60] -to dout[60]
set_disable_timing sb0 -from di[61] -to dout[61]
set_disable_timing sb0 -from di[62] -to dout[62]
set_disable_timing sb0 -from di[63] -to dout[63]
set_disable_timing sb0 -from di[64] -to dout[64]
set_disable_timing sb0 -from di[65] -to dout[65]
set_disable_timing sb0 -from di[66] -to dout[66]
set_disable_timing sb0 -from di[67] -to dout[67]
set_disable_timing sb0 -from di[68] -to dout[68]
set_disable_timing sb0 -from di[69] -to dout[69]
set_disable_timing sb0 -from di[70] -to dout[70]
set_disable_timing sb0 -from di[71] -to dout[71]

set_disable_timing sb0 -from clk -to dout[0]
set_disable_timing sb0 -from clk -to dout[1]
set_disable_timing sb0 -from clk -to dout[2]
set_disable_timing sb0 -from clk -to dout[3]
set_disable_timing sb0 -from clk -to dout[4]
set_disable_timing sb0 -from clk -to dout[5]
set_disable_timing sb0 -from clk -to dout[6]
set_disable_timing sb0 -from clk -to dout[7]
set_disable_timing sb0 -from clk -to dout[8]
set_disable_timing sb0 -from clk -to dout[9]
set_disable_timing sb0 -from clk -to dout[10]
set_disable_timing sb0 -from clk -to dout[11]
set_disable_timing sb0 -from clk -to dout[12]
set_disable_timing sb0 -from clk -to dout[13]
set_disable_timing sb0 -from clk -to dout[14]
set_disable_timing sb0 -from clk -to dout[15]
set_disable_timing sb0 -from clk -to dout[16]
set_disable_timing sb0 -from clk -to dout[17]
set_disable_timing sb0 -from clk -to dout[18]
set_disable_timing sb0 -from clk -to dout[19]
set_disable_timing sb0 -from clk -to dout[20]
set_disable_timing sb0 -from clk -to dout[21]
set_disable_timing sb0 -from clk -to dout[22]
set_disable_timing sb0 -from clk -to dout[23]
set_disable_timing sb0 -from clk -to dout[24]
set_disable_timing sb0 -from clk -to dout[25]
set_disable_timing sb0 -from clk -to dout[26]
set_disable_timing sb0 -from clk -to dout[27]
set_disable_timing sb0 -from clk -to dout[28]
set_disable_timing sb0 -from clk -to dout[29]
set_disable_timing sb0 -from clk -to dout[30]
set_disable_timing sb0 -from clk -to dout[31]
set_disable_timing sb0 -from clk -to dout[32]
set_disable_timing sb0 -from clk -to dout[33]
set_disable_timing sb0 -from clk -to dout[34]
set_disable_timing sb0 -from clk -to dout[35]
set_disable_timing sb0 -from clk -to dout[36]
set_disable_timing sb0 -from clk -to dout[37]
set_disable_timing sb0 -from clk -to dout[38]
set_disable_timing sb0 -from clk -to dout[39]
set_disable_timing sb0 -from clk -to dout[40]
set_disable_timing sb0 -from clk -to dout[41]
set_disable_timing sb0 -from clk -to dout[42]
set_disable_timing sb0 -from clk -to dout[43]
set_disable_timing sb0 -from clk -to dout[44]
set_disable_timing sb0 -from clk -to dout[45]
set_disable_timing sb0 -from clk -to dout[46]
set_disable_timing sb0 -from clk -to dout[47]
set_disable_timing sb0 -from clk -to dout[48]
set_disable_timing sb0 -from clk -to dout[49]
set_disable_timing sb0 -from clk -to dout[50]
set_disable_timing sb0 -from clk -to dout[51]
set_disable_timing sb0 -from clk -to dout[52]
set_disable_timing sb0 -from clk -to dout[53]
set_disable_timing sb0 -from clk -to dout[54]
set_disable_timing sb0 -from clk -to dout[55]
set_disable_timing sb0 -from clk -to dout[56]
set_disable_timing sb0 -from clk -to dout[57]
set_disable_timing sb0 -from clk -to dout[58]
set_disable_timing sb0 -from clk -to dout[59]
set_disable_timing sb0 -from clk -to dout[60]
set_disable_timing sb0 -from clk -to dout[61]
set_disable_timing sb0 -from clk -to dout[62]
set_disable_timing sb0 -from clk -to dout[63]
set_disable_timing sb0 -from clk -to dout[64]
set_disable_timing sb0 -from clk -to dout[65]
set_disable_timing sb0 -from clk -to dout[66]
set_disable_timing sb0 -from clk -to dout[67]
set_disable_timing sb0 -from clk -to dout[68]
set_disable_timing sb0 -from clk -to dout[69]
set_disable_timing sb0 -from clk -to dout[70]
set_disable_timing sb0 -from clk -to dout[71]

set_disable_timing sb1 -from di[0] -to dout[0]
set_disable_timing sb1 -from di[1] -to dout[1]
set_disable_timing sb1 -from di[2] -to dout[2]
set_disable_timing sb1 -from di[3] -to dout[3]
set_disable_timing sb1 -from di[4] -to dout[4]
set_disable_timing sb1 -from di[5] -to dout[5]
set_disable_timing sb1 -from di[6] -to dout[6]
set_disable_timing sb1 -from di[7] -to dout[7]
set_disable_timing sb1 -from di[8] -to dout[8]
set_disable_timing sb1 -from di[9] -to dout[9]
set_disable_timing sb1 -from di[10] -to dout[10]
set_disable_timing sb1 -from di[11] -to dout[11]
set_disable_timing sb1 -from di[12] -to dout[12]
set_disable_timing sb1 -from di[13] -to dout[13]
set_disable_timing sb1 -from di[14] -to dout[14]
set_disable_timing sb1 -from di[15] -to dout[15]
set_disable_timing sb1 -from di[16] -to dout[16]
set_disable_timing sb1 -from di[17] -to dout[17]
set_disable_timing sb1 -from di[18] -to dout[18]
set_disable_timing sb1 -from di[19] -to dout[19]
set_disable_timing sb1 -from di[20] -to dout[20]
set_disable_timing sb1 -from di[21] -to dout[21]
set_disable_timing sb1 -from di[22] -to dout[22]
set_disable_timing sb1 -from di[23] -to dout[23]
set_disable_timing sb1 -from di[24] -to dout[24]
set_disable_timing sb1 -from di[25] -to dout[25]
set_disable_timing sb1 -from di[26] -to dout[26]
set_disable_timing sb1 -from di[27] -to dout[27]
set_disable_timing sb1 -from di[28] -to dout[28]
set_disable_timing sb1 -from di[29] -to dout[29]
set_disable_timing sb1 -from di[30] -to dout[30]
set_disable_timing sb1 -from di[31] -to dout[31]
set_disable_timing sb1 -from di[32] -to dout[32]
set_disable_timing sb1 -from di[33] -to dout[33]
set_disable_timing sb1 -from di[34] -to dout[34]
set_disable_timing sb1 -from di[35] -to dout[35]
set_disable_timing sb1 -from di[36] -to dout[36]
set_disable_timing sb1 -from di[37] -to dout[37]
set_disable_timing sb1 -from di[38] -to dout[38]
set_disable_timing sb1 -from di[39] -to dout[39]
set_disable_timing sb1 -from di[40] -to dout[40]
set_disable_timing sb1 -from di[41] -to dout[41]
set_disable_timing sb1 -from di[42] -to dout[42]
set_disable_timing sb1 -from di[43] -to dout[43]
set_disable_timing sb1 -from di[44] -to dout[44]
set_disable_timing sb1 -from di[45] -to dout[45]
set_disable_timing sb1 -from di[46] -to dout[46]
set_disable_timing sb1 -from di[47] -to dout[47]
set_disable_timing sb1 -from di[48] -to dout[48]
set_disable_timing sb1 -from di[49] -to dout[49]
set_disable_timing sb1 -from di[50] -to dout[50]
set_disable_timing sb1 -from di[51] -to dout[51]
set_disable_timing sb1 -from di[52] -to dout[52]
set_disable_timing sb1 -from di[53] -to dout[53]
set_disable_timing sb1 -from di[54] -to dout[54]
set_disable_timing sb1 -from di[55] -to dout[55]
set_disable_timing sb1 -from di[56] -to dout[56]
set_disable_timing sb1 -from di[57] -to dout[57]
set_disable_timing sb1 -from di[58] -to dout[58]
set_disable_timing sb1 -from di[59] -to dout[59]
set_disable_timing sb1 -from di[60] -to dout[60]
set_disable_timing sb1 -from di[61] -to dout[61]
set_disable_timing sb1 -from di[62] -to dout[62]
set_disable_timing sb1 -from di[63] -to dout[63]
set_disable_timing sb1 -from di[64] -to dout[64]
set_disable_timing sb1 -from di[65] -to dout[65]
set_disable_timing sb1 -from di[66] -to dout[66]
set_disable_timing sb1 -from di[67] -to dout[67]
set_disable_timing sb1 -from di[68] -to dout[68]
set_disable_timing sb1 -from di[69] -to dout[69]
set_disable_timing sb1 -from di[70] -to dout[70]
set_disable_timing sb1 -from di[71] -to dout[71]

set_disable_timing sb1 -from clk -to dout[0]
set_disable_timing sb1 -from clk -to dout[1]
set_disable_timing sb1 -from clk -to dout[2]
set_disable_timing sb1 -from clk -to dout[3]
set_disable_timing sb1 -from clk -to dout[4]
set_disable_timing sb1 -from clk -to dout[5]
set_disable_timing sb1 -from clk -to dout[6]
set_disable_timing sb1 -from clk -to dout[7]
set_disable_timing sb1 -from clk -to dout[8]
set_disable_timing sb1 -from clk -to dout[9]
set_disable_timing sb1 -from clk -to dout[10]
set_disable_timing sb1 -from clk -to dout[11]
set_disable_timing sb1 -from clk -to dout[12]
set_disable_timing sb1 -from clk -to dout[13]
set_disable_timing sb1 -from clk -to dout[14]
set_disable_timing sb1 -from clk -to dout[15]
set_disable_timing sb1 -from clk -to dout[16]
set_disable_timing sb1 -from clk -to dout[17]
set_disable_timing sb1 -from clk -to dout[18]
set_disable_timing sb1 -from clk -to dout[19]
set_disable_timing sb1 -from clk -to dout[20]
set_disable_timing sb1 -from clk -to dout[21]
set_disable_timing sb1 -from clk -to dout[22]
set_disable_timing sb1 -from clk -to dout[23]
set_disable_timing sb1 -from clk -to dout[24]
set_disable_timing sb1 -from clk -to dout[25]
set_disable_timing sb1 -from clk -to dout[26]
set_disable_timing sb1 -from clk -to dout[27]
set_disable_timing sb1 -from clk -to dout[28]
set_disable_timing sb1 -from clk -to dout[29]
set_disable_timing sb1 -from clk -to dout[30]
set_disable_timing sb1 -from clk -to dout[31]
set_disable_timing sb1 -from clk -to dout[32]
set_disable_timing sb1 -from clk -to dout[33]
set_disable_timing sb1 -from clk -to dout[34]
set_disable_timing sb1 -from clk -to dout[35]
set_disable_timing sb1 -from clk -to dout[36]
set_disable_timing sb1 -from clk -to dout[37]
set_disable_timing sb1 -from clk -to dout[38]
set_disable_timing sb1 -from clk -to dout[39]
set_disable_timing sb1 -from clk -to dout[40]
set_disable_timing sb1 -from clk -to dout[41]
set_disable_timing sb1 -from clk -to dout[42]
set_disable_timing sb1 -from clk -to dout[43]
set_disable_timing sb1 -from clk -to dout[44]
set_disable_timing sb1 -from clk -to dout[45]
set_disable_timing sb1 -from clk -to dout[46]
set_disable_timing sb1 -from clk -to dout[47]
set_disable_timing sb1 -from clk -to dout[48]
set_disable_timing sb1 -from clk -to dout[49]
set_disable_timing sb1 -from clk -to dout[50]
set_disable_timing sb1 -from clk -to dout[51]
set_disable_timing sb1 -from clk -to dout[52]
set_disable_timing sb1 -from clk -to dout[53]
set_disable_timing sb1 -from clk -to dout[54]
set_disable_timing sb1 -from clk -to dout[55]
set_disable_timing sb1 -from clk -to dout[56]
set_disable_timing sb1 -from clk -to dout[57]
set_disable_timing sb1 -from clk -to dout[58]
set_disable_timing sb1 -from clk -to dout[59]
set_disable_timing sb1 -from clk -to dout[60]
set_disable_timing sb1 -from clk -to dout[61]
set_disable_timing sb1 -from clk -to dout[62]
set_disable_timing sb1 -from clk -to dout[63]
set_disable_timing sb1 -from clk -to dout[64]
set_disable_timing sb1 -from clk -to dout[65]
set_disable_timing sb1 -from clk -to dout[66]
set_disable_timing sb1 -from clk -to dout[67]
set_disable_timing sb1 -from clk -to dout[68]
set_disable_timing sb1 -from clk -to dout[69]
set_disable_timing sb1 -from clk -to dout[70]
set_disable_timing sb1 -from clk -to dout[71]



/*****************************************************************************/
/* check                                                                     */
/*****************************************************************************/
link
check_design > module + ".lint"


/*****************************************************************************/
/* compile                                                                   */
/*****************************************************************************/
/* set_fix_hold all_clocks() */
compile -ungroup_all -incremental_mapping


/*****************************************************************************/
/* write                                                                     */
/*****************************************************************************/
include "report.dc"

change_names -rules compass_rules -hierarchy
write -format edif -hierarchy -o module + ".edf" module
write -format db -hierarchy -o module + ".db" module

quit