si.v
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/************************************************************************\
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or cosied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
\************************************************************************/
// $Id: si.v,v 1.1.1.1 2002/05/17 06:07:48 blythe Exp $
module si(clk, reset_l,
cbus_read_enable, cbus_write_enable, cbus_select, cbus_command,
dma_start, dbus_enable, dma_grant, read_grant, pif_rsp,
dma_request, read_request, interrupt, pif_cmd, pif_clk,
cbus_data, dbus_data);
`include "si.vh"
input clk; // system clock
input reset_l; // system reset
input cbus_read_enable; // enable cbus read mux
input cbus_write_enable; // enable cbus tristate drivers
input [CBUS_SELECT_SIZE-1:0] cbus_select; // cbus data select
input [CBUS_COMMAND_SIZE-1:0] cbus_command; // cbus data type
input dma_start; // first dbus word flag
input dbus_enable; // enable dbus tristate drivers
input dma_grant; // DMA request granted
input read_grant; // read request granted
input pif_rsp; // PIF serial input
output dma_request; // request a DMA cycle
output read_request; // request a read response cycle
output interrupt; // SI interrupt source
output pif_cmd; // PIF serial output
output pif_clk; // PIF serial clock
inout [CBUS_DATA_SIZE-1:0] cbus_data; // IO bus
inout [DBUS_DATA_SIZE-1:0] dbus_data; // DMA bus
wire dma_read;
wire [DRAM_ADDRESS_SIZE-1:0] dma_address;
wire [DMA_LENGTH_SIZE-1:0] dma_length;
wire [CBUS_DATA_SIZE-1:0] reg_read_data;
wire [SI_REG_WRITE_SIZE-1:0] reg_write_data;
wire [SI_REG_ADDRESS_SIZE-1:0] reg_address;
wire [SI_IO_ADDRESS_SIZE-1:2] io_address;
wire reg_write_enable;
wire pif_clk;
wire [1:0] div_cnt;
wire pchclk;
wire pch_reg_msb;
wire pch_cmd_valid;
wire pch_rsp_reg;
wire pch_rsp_reg_d1;
si_dma si_dma_0 ( .clk(clk), .reset_l(reset_l),
.cbus_read_enable(cbus_read_enable), .cbus_write_enable(cbus_write_enable),
.cbus_select(cbus_select), .cbus_command(cbus_command),
.read_grant(read_grant), .dma_read(dma_read),
.dma_address(dma_address), .dma_length(dma_length),
.reg_read_data(reg_read_data), .io_busy(io_busy),
.read_request(read_request), .reg_write_data(reg_write_data),
.reg_address(reg_address), .io_address(io_address),
.reg_write_enable(reg_write_enable), .cbus_data(cbus_data));
si_control si_control_0 ( .clk(clk), .reset_l(reset_l),
.dbus_enable(dbus_enable), .dma_grant(dma_grant),
.dma_start(dma_start),
.write_data(reg_write_data), .reg_address(reg_address),
.io_address(io_address), .write_enable(reg_write_enable),
.div_cnt(div_cnt),
.pch_rsp_reg(pch_rsp_reg), .pch_rsp_reg_d1(pch_rsp_reg_d1),
.pch_reg_msb(pch_reg_msb), .pch_cmd_valid(pch_cmd_valid),
.dma_req(dma_request), .dma_read(dma_read), .dma_adrs(dma_address),
.dma_length(dma_length), .read_data(reg_read_data),
.interrupt(interrupt), .io_busy(io_busy),
.dbus_data(dbus_data));
si_pif_if si_pif_if_0(.pchclk(pchclk), .pch_reg_msb(pch_reg_msb),
.pch_cmd_valid(pch_cmd_valid), .pch_rsp_in(pif_rsp),
.pch_cmd_reg(pif_cmd),
.pch_rsp_reg(pch_rsp_reg), .pch_rsp_reg_d1(pch_rsp_reg_d1),
.pif_clk(pif_clk) );
si_pchclk si_pchclk_0(.clk(clk), .reset_l(reset_l),
.pchclk(pchclk), .div_cnt(div_cnt));
endmodule