vclk_driver.v
3.12 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
/************************************************************************\
* *
* Copyright(C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
\************************************************************************/
// $Id: vclk_driver.v,v 1.1.1.1 2002/05/17 06:07:48 blythe Exp $
module vclk_driver(vclk_in, reset_l, vbus_data, vbus_sync,
vbus_data_reg, vbus_sync_reg, vclk);
input vclk_in;
input reset_l;
input [6:0] vbus_data;
input vbus_sync;
output [6:0] vbus_data_reg;
output vbus_sync_reg;
output vclk;
wire vclk_int;
wire vclk_reg;
wire [6:0] vbus_data_int;
wire vbus_sync_int;
in01d4 g_0(.i(vclk_in), .zn(vclk_int));
in01d5 g_01(.i(vclk_int), .zn(vclk));
in01d5 g_02(.i(vclk_int), .zn(vclk));
in01d5 g_03(.i(vclk_int), .zn(vclk));
in01d5 g_04(.i(vclk_int), .zn(vclk));
in01d5 g_05(.i(vclk_int), .zn(vclk));
in01d5 g_06(.i(vclk_int), .zn(vclk));
in01d5 g_07(.i(vclk_int), .zn(vclk));
in01d5 g_08(.i(vclk_int), .zn(vclk));
in01d5 g_09(.i(vclk_int), .zn(vclk));
in01d5 g_10(.i(vclk_int), .zn(vclk));
in01d5 g_11(.i(vclk_int), .zn(vclk));
in01d5 g_12(.i(vclk_int), .zn(vclk));
in01d5 g_13(.i(vclk_int), .zn(vclk));
in01d5 g_14(.i(vclk_int), .zn(vclk));
in01d5 g_15(.i(vclk_int), .zn(vclk));
in01d5 g_16(.i(vclk_int), .zn(vclk));
in01d5 g_17(.i(vclk_int), .zn(vclk));
in01d5 g_18(.i(vclk_int), .zn(vclk));
in01d5 g_19(.i(vclk_int), .zn(vclk));
in01d5 g_20(.i(vclk_int), .zn(vclk));
ni01d5 g_reg(.i(vclk_in), .z(vclk_reg));
dfctnh vrs(.d(vbus_sync), .cp(vclk_reg), .cdn(reset_l),
.q(vbus_sync_int));
dfctnh vr0(.d(vbus_data[0]), .cp(vclk_reg), .cdn(reset_l),
.q(vbus_data_int[0]));
dfctnh vr1(.d(vbus_data[1]), .cp(vclk_reg), .cdn(reset_l),
.q(vbus_data_int[1]));
dfctnh vr2(.d(vbus_data[2]), .cp(vclk_reg), .cdn(reset_l),
.q(vbus_data_int[2]));
dfctnh vr3(.d(vbus_data[3]), .cp(vclk_reg), .cdn(reset_l),
.q(vbus_data_int[3]));
dfctnh vr4(.d(vbus_data[4]), .cp(vclk_reg), .cdn(reset_l),
.q(vbus_data_int[4]));
dfctnh vr5(.d(vbus_data[5]), .cp(vclk_reg), .cdn(reset_l),
.q(vbus_data_int[5]));
dfctnh vr6(.d(vbus_data[6]), .cp(vclk_reg), .cdn(reset_l),
.q(vbus_data_int[6]));
ni01d5 vbs(.i(vbus_sync_int), .z(vbus_sync_reg));
ni01d5 vb0(.i(vbus_data_int[0]), .z(vbus_data_reg[0]));
ni01d5 vb1(.i(vbus_data_int[1]), .z(vbus_data_reg[1]));
ni01d5 vb2(.i(vbus_data_int[2]), .z(vbus_data_reg[2]));
ni01d5 vb3(.i(vbus_data_int[3]), .z(vbus_data_reg[3]));
ni01d5 vb4(.i(vbus_data_int[4]), .z(vbus_data_reg[4]));
ni01d5 vb5(.i(vbus_data_int[5]), .z(vbus_data_reg[5]));
ni01d5 vb6(.i(vbus_data_int[6]), .z(vbus_data_reg[6]));
endmodule