ststwl.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: ststwl.v,v 1.1.1.1 2002/05/17 06:07:48 blythe Exp $
/* Project Reality
MDP
Created by Mike M. Cai 5/25/94
*/
module ststwl( att_data_out,
att_data_in, dx,
left_major, load, ncyc, gclk);
output [15:0] att_data_out;
input [26:0] att_data_in, dx;
input left_major, load, ncyc, gclk;
wire [26:0] att_cur_m, att_accum, dx_dir;
reg [26:0] att_cur_s;
wire [15:0] att_data_out;
reg comp_new;
always @(posedge gclk)
begin
att_cur_s <= load ? att_data_in : att_accum;
comp_new <= load ? ~ncyc : (ncyc ? ~comp_new : comp_new);
end
assign
dx_dir = (dx ~^ {27{left_major}}) & {27{comp_new}};
adder27b adder ( .sum(att_accum), .a(att_cur_s), .b(dx_dir),
.ci(~left_major & comp_new));
assign att_data_out = att_cur_s[26:11];
endmodule // ststwl