issue.ss
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/*****************************************************************************/
/* custom variables */
/*****************************************************************************/
module = issue
wire_load = 256000
standard_load = 0.01
clock = clk
default_input_delay = 1.5
default_output_delay = 1.0
default_input_load = 20
default_output_load = 20
default_drive_cell = dfntnh
default_drive_pin = q
/*****************************************************************************/
/* set the path and read */
/*****************************************************************************/
search_path = search_path + "../src"
read -f verilog ../src/issue.v
read -f verilog ../../rsp/src/spasdff_1_1.v
read -f verilog ../../rsp/src/spasdff_1_0.v
read -f verilog ../../rsp/src/spasdff_1_0_h.v
read -f verilog ../../rsp/src/spasdff_3_0.v
read -f verilog ../../rsp/src/spasdff_4_0.v
read -f verilog ../../rsp/src/spasdff_5_0.v
read -f verilog ../../rsp/src/spasdff_6_0.v
read -f verilog ../../rsp/src/spasdff_24_0.v
read -f verilog ../../rsp/src/spasdff_32_0.v
read -f verilog ../../rsp/src/spasdffen_1_0.v
read -f verilog ../../rsp/src/spasdffen_9_0.v
read -f verilog ../../rsp/src/spasdffen_10_0.v
read -f verilog ../../rsp/src/spasdffen_10_0_h.v
read -f verilog ../../rsp/src/spasdffen_32_0.v
read -f verilog ../../rsp/src/spasdffen_64_h.v
current_design = module
/*****************************************************************************/
/* default environment */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top
/*****************************************************************************/
/* default constraint */
/*****************************************************************************/
/* set_max_area 0 */
create_clock clk -period 16.0 -waveform {0.0 8.0}
set_input_delay default_input_delay -clock clk all_inputs()
set_output_delay default_output_delay -clock clk all_outputs()
set_load default_output_load * standard_load all_outputs()
set_load default_input_load * standard_load all_inputs()
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs()
/*****************************************************************************/
/* clock and reset constraints */
/*****************************************************************************/
set_drive 0 clock
set_arrival 0 clock
set_dont_touch_network clock
set_drive 0 reset_l
set_input_delay 6 -clock clock reset_l
/*****************************************************************************/
/* custom constraints */
/*****************************************************************************/
set_max_fanout 8 module
set_max_transition 1.0 module
include module + ".con"
/*****************************************************************************/
/* check */
/*****************************************************************************/
check_design > module + ".lint"
/* link ??? */
/*****************************************************************************/
/* compile */
/*****************************************************************************/
ungroup -flatten *_ff
ungroup -flatten *_bufs
ungroup -flatten *su_inst_a_mux
ungroup -flatten *vu_inst_a_mux
set_dont_touch *_ff*
set_dont_touch *_bufs*
set_dont_touch *su_inst_a_mux*
set_dont_touch *vu_inst_a_mux*
compile -no_map
set_dont_touch *_ff* false
set_dont_touch *_bufs* false
set_dont_touch *su_inst_a_mux* false
set_dont_touch *vu_inst_a_mux* false
compile -map_effort high -ungroup_all -incremental_mapping
/*****************************************************************************/
/* write */
/*****************************************************************************/
report -reference
report_constraint -all_violators
report_timing -path full -delay max -max_paths 100;
change_names -rules compass_rules -hierarchy
write -format edif -hierarchy -o module + ".edf" module
write -format verilog -hierarchy -o module + ".vsyn" module
write -format db -hierarchy -o module + ".db" module
quit