/*
*************************************************************************
*									*
*               Copyright (C) 1994, Silicon Graphics, Inc.		*
*									*
*  These coded instructions, statements, and computer programs  contain	*
*  unpublished  proprietary  information of Silicon Graphics, Inc., and	*
*  are protected by Federal copyright  law.  They  may not be disclosed	*
*  to  third  parties  or copied or duplicated in any form, in whole or	*
*  in part, without the prior written consent of Silicon Graphics, Inc.	*
*									*
*************************************************************************
*/

// $Id: vu.v,v 1.1.1.1 2002/05/17 06:07:49 blythe Exp $


/*
*************************************************************************
*									*
*	Project Reality							*
*									*
*	Module:		vu						*
*	Description:	Top level vector unit which incorporates 4	* 
*			vector unit slice and one divide unit.		*
*			Each vector unit slice includes two vector 	*
*			unit datapaths, the unique control for each	*
*									*
*									*
*	Designer:	Brian Ferguson					*
*	Date:		8/10/94						*
*									*
*************************************************************************
*/

// vu.v: 	RSP vector unit top level - instantiation of datapath and control

`timescale 1ns / 10ps

module	vu (	clk, reset_l, 
		su_instvld_rd, su_storeinst_rd, su_storecfc2_rd, 
		su_vseqone_rd, su_instelem_rd, su_instfunc_rd, 
		su_rdcmpcd_rd, su_rdcryout_rd, su_rdcmpcdad_rd,
		su_wrcmpcd_wb, su_wrcryout_wb, su_wrcmpcdad_wb,

		su_st_rnum_rd,
		su_xp_rnum_rd,
		su_ld_rnum_ac,
		su_vs_addr_rd,
		su_vt_addr_rd,
		su_vt_addr_cpy_rd,
		su_vd_addr_ac,
		su_wbv_wr_en_ac,
		su_bwe_ac,
		su_xposeop_rdac,

		su_data_to_from
	   ) ;


	input	clk;				/* vu clock */
	input	reset_l;			/* vu active low reset */

	input	su_instvld_rd;			/* valid CP2 instruction for vu */
	input	su_storeinst_rd;		/* store from VU */
	input	su_storecfc2_rd;		/* store or move control from VU */
	input	su_vseqone_rd;			/* vs field of instruction equal to 1 */
	input   [3:0] su_instelem_rd;		/* element field of instruction */
	input   [5:0] su_instfunc_rd;		/* function field of instruction */

	input	su_rdcmpcd_rd;			/* read vector compare code register */
	input	su_rdcryout_rd;			/* read vector carry out register */
	input	su_rdcmpcdad_rd;		/* read vector compare add register */

	input	su_wrcmpcd_wb;			/* write vector compare code register */
	input	su_wrcryout_wb;			/* write vector carry out register */
	input	su_wrcmpcdad_wb;		/* write vector compare add register */

/*
*	The following input signals are for register file address decoding
*	only.
*/

	input	[4:0]	su_st_rnum_rd;		/* register number for stores */
	input	[4:0]	su_xp_rnum_rd;		/* register number for xpose stores */
	input	[4:0]	su_ld_rnum_ac;		/* register number for load */
	input	[4:0]	su_vs_addr_rd;		/* register number for vs read */
	input	[31:0]	su_vt_addr_rd;		/* decoded register number for vt read */
	input	[31:0]	su_vt_addr_cpy_rd;	/* decoded register number for vt read */
	input	[4:0]	su_vd_addr_ac;		/* register number for datapath writeback */
	input		su_wbv_wr_en_ac;	/* write enable for datapath results */
	input	[15:0]	su_bwe_ac;		/* load port byte write enable */
	input		su_xposeop_rdac;	/* transpose op in rd (store) or ac (load) */

	inout	[127:0]	su_data_to_from;	/* data field to/from vu */
	
/*
*	The following signals are the input signals to the 
*	vector unit control block.
*
*	The first group are input signals to the control block 
*	which provide general control such as clocks, reset
*	hold and instruction decoding.
*
*/


/*
*	The following are wires for connecting between vector unit datapath slice
*	modules.
*/

	wire	[15:0]	vdp_hlfout0_rd;		/* data from datapaths 0 for scalar half */
	wire	[15:0]	vdp_hlfout1_rd;		/* data from datapaths 1 for scalar half */
	wire	[15:0]	vdp_hlfout2_rd;		/* data from datapaths 2 for scalar half */
	wire	[15:0]	vdp_hlfout3_rd;		/* data from datapaths 3 for scalar half */
	wire	[15:0]	vdp_hlfout4_rd;		/* data from datapaths 4 for scalar half */
	wire	[15:0]	vdp_hlfout5_rd;		/* data from datapaths 5 for scalar half */
	wire	[15:0]	vdp_hlfout6_rd;		/* data from datapaths 6 for scalar half */
	wire	[15:0]	vdp_hlfout7_rd;		/* data from datapaths 7 for scalar half */

	wire	[15:0]	vdp_whlout0_rd;		/* data from datapaths 0 for scalar whole */
	wire	[15:0]	vdp_whlout1_rd;		/* data from datapaths 1 for scalar whole */
	wire	[15:0]	vdp_whlout2_rd;		/* data from datapaths 2 for scalar whole */
	wire	[15:0]	vdp_whlout3_rd;		/* data from datapaths 3 for scalar whole */
	wire	[15:0]	vdp_whlout4_rd;		/* data from datapaths 4 for scalar whole */
	wire	[15:0]	vdp_whlout5_rd;		/* data from datapaths 5 for scalar whole */
	wire	[15:0]	vdp_whlout6_rd;		/* data from datapaths 6 for scalar whole */
	wire	[15:0]	vdp_whlout7_rd;		/* data from datapaths 7 for scalar whole */


	wire	vct_hlflosl01_rd;		/* select VT scalar value from 0,1,4,5 vectors */
	wire	[2:0]	vct_whllosl01_rd;	/* select VT scalar value from 0,1,2,3 vectors */
	wire	vct_hlfhisl01_rd;		/* select VT scalar value from 2,3,6,7 vectors */
	wire	[2:0]	vct_whlhisl01_rd;	/* select VT scalar value from 4,5,6,7 vectors */

	wire	vct_hlflosl23_rd;		/* select VT scalar value from 0,1,4,5 vectors */
	wire	[2:0]	vct_whllosl23_rd;	/* select VT scalar value from 0,1,2,3 vectors */
	wire	vct_hlfhisl23_rd;		/* select VT scalar value from 2,3,6,7 vectors */
	wire	[2:0]	vct_whlhisl23_rd;	/* select VT scalar value from 4,5,6,7 vectors */

	wire	vct_hlflosl45_rd;		/* select VT scalar value from 0,1,4,5 vectors */
	wire	[2:0]	vct_whllosl45_rd;	/* select VT scalar value from 0,1,2,3 vectors */
	wire	vct_hlfhisl45_rd;		/* select VT scalar value from 2,3,6,7 vectors */
	wire	[2:0]	vct_whlhisl45_rd;	/* select VT scalar value from 4,5,6,7 vectors */

	wire	vct_hlflosl67_rd;		/* select VT scalar value from 0,1,4,5 vectors */
	wire	[2:0]	vct_whllosl67_rd;	/* select VT scalar value from 0,1,2,3 vectors */
	wire	vct_hlfhisl67_rd;		/* select VT scalar value from 2,3,6,7 vectors */
	wire	[2:0]	vct_whlhisl67_rd;	/* select VT scalar value from 4,5,6,7 vectors */

	wire	su_storeinst01_mu;		/* store from VU slice 01 */
	wire	su_storeinst23_mu;		/* store from VU slice 23 */
	wire	su_storeinst45_mu;		/* store from VU slice 45 */
	wire	su_storeinst67_mu;		/* store from VU slice 67 */

	wire	su_storecfc201_mu;		/* store or move control from VU slice 01 */
	wire	su_storecfc223_mu;		/* store or move control from VU slice 23 */
	wire	su_storecfc245_mu;		/* store or move control from VU slice 45 */
	wire	su_storecfc267_mu;		/* store or move control from VU slice 67 */

	wire	[15:0]	vdi_divrslt_wb;		/* result from divide unit */

vusl	vusl01 (
		.clk				(clk),
		.reset_l			(reset_l), 
		.su_storeinst_rd		(su_storeinst_rd),
		.su_storecfc2_rd		(su_storecfc2_rd), 
		.su_instvld_rd			(su_instvld_rd),
		.su_vseqone_rd			(su_vseqone_rd),
		.su_instelem_rd			(su_instelem_rd),
		.su_instfunc_rd			(su_instfunc_rd), 
		.su_rdcmpcd_rd			(su_rdcmpcd_rd),
		.su_rdcryout_rd			(su_rdcryout_rd),
		.su_rdcmpcdad_rd		(su_rdcmpcdad_rd),
		.su_wrcmpcd_wb			(su_wrcmpcd_wb),
		.su_wrcryout_wb			(su_wrcryout_wb),
		.su_wrcmpcdad_wb		(su_wrcmpcdad_wb),

		.su_st_rnum_rd			(su_st_rnum_rd),
		.su_xp_rnum_rd			(su_xp_rnum_rd),
		.su_ld_rnum_ac			(su_ld_rnum_ac),
		.su_vs_addr_rd			(su_vs_addr_rd),
		.su_vt_addr_rd			(su_vt_addr_rd),
		.su_vd_addr_ac			(su_vd_addr_ac),
		.su_wbv_wr_en_ac		(su_wbv_wr_en_ac),
		.su_bwe_ac			(su_bwe_ac[15:12]),
		.su_xposeop_rdac		(su_xposeop_rdac),
		.vct_slice0			(3'h0),
		.vct_slice1			(3'h1),

		.vdi_divrslt0_wb		(vdi_divrslt_wb),
		.vdi_divrslt1_wb		(vdi_divrslt_wb),

		.vdp_hlfin0_rd			(vdp_hlfout2_rd),
		.vdp_hlfin1_rd			(vdp_hlfout2_rd),

		.vdp_whlin0_rd			(vdp_whlout4_rd),
		.vdp_whlin1_rd			(vdp_whlout4_rd),

		.vct_hlfsl0_rd			(vct_hlflosl01_rd),
		.vct_hlfsl1_rd			(vct_hlflosl01_rd),

		.vct_whlsl0_rd			(vct_whllosl01_rd),
		.vct_whlsl1_rd			(vct_whllosl01_rd),


		.vct_hlflosl_rd			(vct_hlflosl01_rd),
		.vct_hlfhisl_rd			(vct_hlfhisl01_rd),
		.vct_whllosl_rd			(vct_whllosl01_rd),
		.vct_whlhisl_rd			(vct_whlhisl01_rd),

		.vdp_hlfout0_rd			(vdp_hlfout0_rd),
		.vdp_hlfout1_rd			(vdp_hlfout1_rd),

		.vdp_whlout0_rd			(vdp_whlout0_rd),
		.vdp_whlout1_rd			(vdp_whlout1_rd),

		.vdp_datatristen0_mu		(su_storecfc201_mu),
		.vdp_datatristen1_mu		(su_storeinst01_mu),

		.su_storeinst_mu		(su_storeinst01_mu), 
		.su_storecfc2_mu		(su_storecfc201_mu),

		.su_data_to_from		(su_data_to_from[127:96]),
		.su_cont_to_from		({su_data_to_from[105:104],su_data_to_from[97:96]})

	   ) ;



vusl	vusl23 (
		.clk				(clk),
		.reset_l			(reset_l), 
		.su_storeinst_rd		(su_storeinst_rd),
		.su_storecfc2_rd		(su_storecfc2_rd), 
		.su_instvld_rd			(su_instvld_rd),
		.su_vseqone_rd			(su_vseqone_rd),
		.su_instelem_rd			(su_instelem_rd),
		.su_instfunc_rd			(su_instfunc_rd), 
		.su_rdcmpcd_rd			(su_rdcmpcd_rd),
		.su_rdcryout_rd			(su_rdcryout_rd),
		.su_rdcmpcdad_rd		(su_rdcmpcdad_rd),
		.su_wrcmpcd_wb			(su_wrcmpcd_wb),
		.su_wrcryout_wb			(su_wrcryout_wb),
		.su_wrcmpcdad_wb		(su_wrcmpcdad_wb),

		.su_st_rnum_rd			(su_st_rnum_rd),
		.su_xp_rnum_rd			(su_xp_rnum_rd),
		.su_ld_rnum_ac			(su_ld_rnum_ac),
		.su_vs_addr_rd			(su_vs_addr_rd),
		.su_vt_addr_rd			(su_vt_addr_rd),
		.su_vd_addr_ac			(su_vd_addr_ac),
		.su_wbv_wr_en_ac		(su_wbv_wr_en_ac),
		.su_bwe_ac			(su_bwe_ac[11:8]),
		.su_xposeop_rdac		(su_xposeop_rdac),
		.vct_slice0			(3'h2),
		.vct_slice1			(3'h3),

		.vdi_divrslt0_wb		(vdi_divrslt_wb),
		.vdi_divrslt1_wb		(vdi_divrslt_wb),

		.vdp_hlfin0_rd			(vdp_hlfout1_rd),
		.vdp_hlfin1_rd			(vdp_hlfout1_rd),

		.vdp_whlin0_rd			(vdp_whlout4_rd),
		.vdp_whlin1_rd			(vdp_whlout4_rd),

		.vct_hlfsl0_rd			(vct_hlfhisl23_rd),
		.vct_hlfsl1_rd			(vct_hlfhisl23_rd),

		.vct_whlsl0_rd			(vct_whllosl23_rd),
		.vct_whlsl1_rd			(vct_whllosl23_rd),


		.vct_hlflosl_rd			(vct_hlflosl23_rd),
		.vct_hlfhisl_rd			(vct_hlfhisl23_rd),
		.vct_whllosl_rd			(vct_whllosl23_rd),
		.vct_whlhisl_rd			(vct_whlhisl23_rd),

		.vdp_hlfout0_rd			(vdp_hlfout2_rd),
		.vdp_hlfout1_rd			(vdp_hlfout3_rd),

		.vdp_whlout0_rd			(vdp_whlout2_rd),
		.vdp_whlout1_rd			(vdp_whlout3_rd),

		.vdp_datatristen0_mu		(su_storecfc223_mu),
		.vdp_datatristen1_mu		(su_storecfc223_mu),

		.su_storeinst_mu		(su_storeinst23_mu), 
		.su_storecfc2_mu		(su_storecfc223_mu),

		.su_data_to_from		(su_data_to_from[95:64]),
		.su_cont_to_from		({su_data_to_from[107:106],su_data_to_from[99:98]})

	   ) ;


vusl	vusl45 (
		.clk				(clk),
		.reset_l			(reset_l), 
		.su_storeinst_rd		(su_storeinst_rd),
		.su_storecfc2_rd		(su_storecfc2_rd), 
		.su_instvld_rd			(su_instvld_rd),
		.su_vseqone_rd			(su_vseqone_rd),
		.su_instelem_rd			(su_instelem_rd),
		.su_instfunc_rd			(su_instfunc_rd), 
		.su_rdcmpcd_rd			(su_rdcmpcd_rd),
		.su_rdcryout_rd			(su_rdcryout_rd),
		.su_rdcmpcdad_rd		(su_rdcmpcdad_rd),
		.su_wrcmpcd_wb			(su_wrcmpcd_wb),
		.su_wrcryout_wb			(su_wrcryout_wb),
		.su_wrcmpcdad_wb		(su_wrcmpcdad_wb),

		.su_st_rnum_rd			(su_st_rnum_rd),
		.su_xp_rnum_rd			(su_xp_rnum_rd),
		.su_ld_rnum_ac			(su_ld_rnum_ac),
		.su_vs_addr_rd			(su_vs_addr_rd),
		.su_vt_addr_rd			(su_vt_addr_cpy_rd),
		.su_vd_addr_ac			(su_vd_addr_ac),
		.su_wbv_wr_en_ac		(su_wbv_wr_en_ac),
		.su_bwe_ac			(su_bwe_ac[7:4]),
		.su_xposeop_rdac		(su_xposeop_rdac),
		.vct_slice0			(3'h4),
		.vct_slice1			(3'h5),

		.vdi_divrslt0_wb		(vdi_divrslt_wb),
		.vdi_divrslt1_wb		(vdi_divrslt_wb),

		.vdp_hlfin0_rd			(vdp_hlfout6_rd),
		.vdp_hlfin1_rd			(vdp_hlfout6_rd),

		.vdp_whlin0_rd			(vdp_whlout3_rd),
		.vdp_whlin1_rd			(vdp_whlout3_rd),

		.vct_hlfsl0_rd			(vct_hlflosl45_rd),
		.vct_hlfsl1_rd			(vct_hlflosl45_rd),

		.vct_whlsl0_rd			(vct_whlhisl45_rd),
		.vct_whlsl1_rd			(vct_whlhisl45_rd),


		.vct_hlflosl_rd			(vct_hlflosl45_rd),
		.vct_hlfhisl_rd			(vct_hlfhisl45_rd),
		.vct_whllosl_rd			(vct_whllosl45_rd),
		.vct_whlhisl_rd			(vct_whlhisl45_rd),

		.vdp_hlfout0_rd			(vdp_hlfout4_rd),
		.vdp_hlfout1_rd			(vdp_hlfout5_rd),

		.vdp_whlout0_rd			(vdp_whlout4_rd),
		.vdp_whlout1_rd			(vdp_whlout5_rd),

		.vdp_datatristen0_mu		(su_storecfc245_mu),
		.vdp_datatristen1_mu		(su_storecfc245_mu),

		.su_storeinst_mu		(su_storeinst45_mu), 
		.su_storecfc2_mu		(su_storecfc245_mu),

		.su_data_to_from		(su_data_to_from[63:32]),
		.su_cont_to_from		({su_data_to_from[109:108],su_data_to_from[101:100]})

	   ) ;


vusl	vusl67 (
		.clk				(clk),
		.reset_l			(reset_l), 
		.su_storeinst_rd		(su_storeinst_rd),
		.su_storecfc2_rd		(su_storecfc2_rd), 
		.su_instvld_rd			(su_instvld_rd),
		.su_vseqone_rd			(su_vseqone_rd),
		.su_instelem_rd			(su_instelem_rd),
		.su_instfunc_rd			(su_instfunc_rd), 
		.su_rdcmpcd_rd			(su_rdcmpcd_rd),
		.su_rdcryout_rd			(su_rdcryout_rd),
		.su_rdcmpcdad_rd		(su_rdcmpcdad_rd),
		.su_wrcmpcd_wb			(su_wrcmpcd_wb),
		.su_wrcryout_wb			(su_wrcryout_wb),
		.su_wrcmpcdad_wb		(su_wrcmpcdad_wb),

		.su_st_rnum_rd			(su_st_rnum_rd),
		.su_xp_rnum_rd			(su_xp_rnum_rd),
		.su_ld_rnum_ac			(su_ld_rnum_ac),
		.su_vs_addr_rd			(su_vs_addr_rd),
		.su_vt_addr_rd			(su_vt_addr_cpy_rd),
		.su_vd_addr_ac			(su_vd_addr_ac),
		.su_wbv_wr_en_ac		(su_wbv_wr_en_ac),
		.su_bwe_ac			(su_bwe_ac[3:0]),
		.su_xposeop_rdac		(su_xposeop_rdac),
		.vct_slice0			(3'h6),
		.vct_slice1			(3'h7),

		.vdi_divrslt0_wb		(vdi_divrslt_wb),
		.vdi_divrslt1_wb		(vdi_divrslt_wb),

		.vdp_hlfin0_rd			(vdp_hlfout5_rd),
		.vdp_hlfin1_rd			(vdp_hlfout5_rd),

		.vdp_whlin0_rd			(vdp_whlout3_rd),
		.vdp_whlin1_rd			(vdp_whlout3_rd),

		.vct_hlfsl0_rd			(vct_hlfhisl67_rd),
		.vct_hlfsl1_rd			(vct_hlfhisl67_rd),

		.vct_whlsl0_rd			(vct_whlhisl67_rd),
		.vct_whlsl1_rd			(vct_whlhisl67_rd),


		.vct_hlflosl_rd			(vct_hlflosl67_rd),
		.vct_hlfhisl_rd			(vct_hlfhisl67_rd),
		.vct_whllosl_rd			(vct_whllosl67_rd),
		.vct_whlhisl_rd			(vct_whlhisl67_rd),

		.vdp_hlfout0_rd			(vdp_hlfout6_rd),
		.vdp_hlfout1_rd			(vdp_hlfout7_rd),

		.vdp_whlout0_rd			(vdp_whlout6_rd),
		.vdp_whlout1_rd			(vdp_whlout7_rd),

		.vdp_datatristen0_mu		(su_storecfc267_mu),
		.vdp_datatristen1_mu		(su_storecfc267_mu),

		.su_storeinst_mu		(su_storeinst67_mu), 
		.su_storecfc2_mu		(su_storecfc267_mu),

		.su_data_to_from		(su_data_to_from[31:0]),
		.su_cont_to_from		({su_data_to_from[111:110],su_data_to_from[103:102]})

	   ) ;




div	div1  (
		.CLK				(clk),
		.Reset_l			(reset_l),
		.OpCode				(su_instfunc_rd),
		.OpCodeValid			(su_instvld_rd),
		.VTH				(vdp_whlout7_rd),
		.VTL				(vdp_whlout2_rd),
		.El2				(su_instelem_rd[2]),

		.DivOut				(vdi_divrslt_wb)
	      ) ;


endmodule