/*
*************************************************************************
*									*
*               Copyright (C) 1994, Silicon Graphics, Inc.		*
*									*
*  These coded instructions, statements, and computer programs  contain	*
*  unpublished  proprietary  information of Silicon Graphics, Inc., and	*
*  are protected by Federal copyright  law.  They  may not be disclosed	*
*  to  third  parties  or copied or duplicated in any form, in whole or	*
*  in part, without the prior written consent of Silicon Graphics, Inc.	*
*									*
*************************************************************************
*/

// $Id: vuctl.v,v 1.1.1.1 2002/05/17 06:07:49 blythe Exp $

/*
*************************************************************************
*									*
*	Project Reality							*
*									*
*	Module:		vuctl						*
*	Description:	vector unit control for all two vector unit	* 
*			datapaths and two multipliers.			*
*									*
*	Designer:	Brian Ferguson					*
*	Date:		8/11/94						*
*									*
*************************************************************************
*/

// vuctl.v: 	RSP vector unit control

`timescale 1ns / 10ps

`include "vopcodes.h"

module	vuctl (	clk, reset_l,
		su_instvld_rd, su_storeinst_rd, su_storecfc2_rd,
		su_vseqone_rd, 
		su_instelem_rd, su_instfunc_rd,
		su_rdcmpcd_rd, su_rdcryout_rd, su_rdcmpcdad_rd, 
		su_wrcmpcd_wb, su_wrcryout_wb, su_wrcmpcdad_wb,

		vdp_vs_sign0_rd, vdp_vs_sign1_rd,

		vdp_vs_zero0_mu, vdp_vs_zero1_mu,

		vdp_vt_zero0_mu, vdp_vt_zero1_mu,

		vdp_vt_sign0_mu, vdp_vt_sign1_mu,

		vdp_aluovr0_mu,
		vdp_aluco0_mu, vdp_aluzero0_mu, vdp_aluone0_mu,

		vdp_aluovr1_mu,
		vdp_aluco1_mu, vdp_aluzero1_mu, vdp_aluone1_mu,

		vdp_addlwco0_ac, vdp_addlwov0_ac,
		vdp_csupco0_ac, vdp_addupco0_ac,

		vdp_addlwco1_ac, vdp_addlwov1_ac, 
		vdp_csupco1_ac, vdp_addupco1_ac,

		vmu_co_clal0_ac, vmu_co_clal1_ac,
		vmu_co_clah0_ac, vmu_co_clah1_ac,

		vdp_acc0bit15_wb, vdp_acc0bit21_wb,
		vdp_acc0bit31_wb, vdp_acc0bit47_wb,
		vdp_achizero0_wb, vdp_achione0_wb,
		vdp_acmizero0_wb,

		vdp_acc1bit15_wb, vdp_acc1bit21_wb,
		vdp_acc1bit31_wb, vdp_acc1bit47_wb,
		vdp_achizero1_wb, vdp_achione1_wb,
		vdp_acmizero1_wb,

		vct_regopssl_rd,
		vct_qurtlosl_rd, vct_halflosl_rd, vct_whllosl_rd,
		vct_qurthisl_rd, vct_halfhisl_rd, vct_whlhisl_rd, 

		vct_couprsl_mu, vct_smuprsl_mu, 
		vct_colwrsl_mu, 

		vct_smlwrsl0_mu, 
		vct_smlwrsl1_mu, 

		vct_sgnmplr_mu, vct_sgnmplcnd_mu, vct_shftlftone_mu,

		vct_aluctl0_mu, vct_alucin0_mu,
		vct_compvt0_mu,

		vct_aluctl1_mu, vct_alucin1_mu,
		vct_compvt1_mu,

		vct_aclwsl0_ac, 
		vct_aclwsl1_ac, 

		vct_cslwcsl_ac,
		vct_csupcen0_ac,
		vct_csupcen1_ac,

		vct_acmisl0_ac,
		vct_acmisl1_ac,

		vct_acupsl0_ac, 
		vct_acupsl1_ac, 

		vct_rndvlu0_ac,
		vct_cslwasl0_ac, vct_cslwbsl0_ac,
		vct_addlwci0_ac,
		vct_csupasl0_ac, vct_csupbsl0_ac,
		vct_incrdwn0_ac, vct_incrci0_ac,
		vct_incrmxsl0_ac,

		vct_rndvlu1_ac,
		vct_cslwasl1_ac, vct_cslwbsl1_ac,
		vct_addlwci1_ac,
		vct_csupasl1_ac, vct_csupbsl1_ac,
		vct_incrdwn1_ac, vct_incrci1_ac,
		vct_incrmxsl1_ac,

		vct_rsltsl0_wb, vct_rsltsl1_wb,

		vct_clprslt0_wb, vct_clprslt1_wb,

		su_storeinst_mu, su_storecfc2_mu,

		su_cont_to_from, 

/*
*	The following signals are for register file address decoding
*	only.
*/

		su_st_rnum_rd,
		su_xp_rnum_rd,
		su_ld_rnum_ac,
		su_vs_addr_rd,
		su_vt_addr_rd,
		su_vd_addr_ac,
		su_wbv_wr_en_ac,
		su_bwe_ac,
		su_xposeop_rdac,
		vct_slice0,
		vct_slice1,

		vct_rfadrt_hi0_wb,
		vct_rfadrf_hi0_wb,
		vct_rfadrt_lo0_wb,
		vct_rfadrf_lo0_wb,
		vct_rfadrt_st0_rd,
		vct_rfadrf_st0_rd,
		vct_rfadrt_vs0_rd,
		vct_rfadrf_vs0_rd, 
		vct_rfadrt_vt0_rd,
		vct_rfadrf_vt0_rd,
		vct_rfadrt_vd0_wb,
		vct_rfadrf_vd0_wb,

		vct_rfadrt_hi1_wb,
		vct_rfadrf_hi1_wb,
		vct_rfadrt_lo1_wb,
		vct_rfadrf_lo1_wb,
		vct_rfadrt_st1_rd,
		vct_rfadrf_st1_rd,
		vct_rfadrt_vs1_rd,
		vct_rfadrf_vs1_rd, 
		vct_rfadrt_vt1_rd,
		vct_rfadrf_vt1_rd,
		vct_rfadrt_vd1_wb,
		vct_rfadrf_vd1_wb

		);


/*
*	The following signals are the input signals to the 
*	vector unit control block.
*
*	The first group are input signals to the control block 
*	which provide general control such as clocks, reset
*	hold, instruction decoding and reading/writing the 
*	control registers.
*/

	input	clk;			/* vu clock */
	input	reset_l;		/* vu active low reset */

	input	su_instvld_rd;		/* valid CP2 instruction for vu */
	input	su_storeinst_rd;	/* store from VU */
	input	su_storecfc2_rd;	/* store or move control from VU */
	input	su_vseqone_rd;		/* vs field of instruction equal to 1 */
	input   [3:0] su_instelem_rd;	/* element field of instruction */
	input   [5:0] su_instfunc_rd;	/* function field of instruction */

	input	su_rdcmpcd_rd;		/* read vector compare code register */
	input	su_rdcryout_rd;		/* read vector carry out register */
	input	su_rdcmpcdad_rd;	/* read vector compare add register */

	input	su_wrcmpcd_wb;		/* write vector compare code register */
	input	su_wrcryout_wb;		/* write vector carry out register */
	input	su_wrcmpcdad_wb;	/* write vector compare add register */

/*
*	The next group are input signals to the control block from
*	the register file read stage of the vector unit datapaths.
*/
	input	vdp_vs_sign0_rd;	/* vs sign bit from vector 0 */
	input	vdp_vs_sign1_rd;	/* vs sign bit from vector 1 */

/*
*	The next group are input signals to the control block from
*	the multiply stage of the vector unit datapaths.
*/


	input	vdp_vs_zero0_mu;	/* vs operand is equal to zero vector 0 */
	input	vdp_vs_zero1_mu;	/* vs operand is equal to zero vector 1 */

	input	vdp_vt_zero0_mu;	/* vt operand is equal to zero vector 0 */
	input	vdp_vt_zero1_mu;	/* vt operand is equal to zero vector 1 */

	input	vdp_vt_sign0_mu;	/* vt sign bit from vector 0 */
	input	vdp_vt_sign1_mu;	/* vt sign bit from vector 1 */

	input	vdp_aluovr0_mu;		/* overflow bit from alu vector 0 */
	input	vdp_aluco0_mu;		/* carry out from alu vector 0 */
	input	vdp_aluzero0_mu;	/* alu result equal to zero vector 0 */
	input	vdp_aluone0_mu;		/* alu result is equal to one vector 0 */

	input	vdp_aluovr1_mu;		/* overflow bit from alu vector 1 */
	input	vdp_aluco1_mu;		/* carry out from alu vector 1 */
	input	vdp_aluzero1_mu;	/* alu result is equal to zero vector 1 */
	input	vdp_aluone1_mu;		/* alu result is equal to one vector 1 */

/*
*	The next group are input signals to the control block from
*	the accumulate stage of the vector unit datapaths.
*/

	input	vdp_addlwco0_ac;	/* carry out from low adder vector 0 */
	input	vdp_addlwov0_ac;	/* overflow from low csa vector 0 */
	input	vdp_csupco0_ac;		/* carry out from high csa vector 0 */
	input	vdp_addupco0_ac;	/* carry out from high adder vector 0 */

	input	vdp_addlwco1_ac;	/* carry out from low adder vector 1 */
	input	vdp_addlwov1_ac;	/* overflow from low csa vector 1 */
	input	vdp_csupco1_ac;		/* carry out from high csa vector 1 */
	input	vdp_addupco1_ac;	/* carry out from high adder vector 1 */

	input	vmu_co_clal0_ac;	/* carry out from 16 bit product of multiplier vector 0 */
	input	vmu_co_clal1_ac;	/* carry out from 16 bit product of multiplier vector 1 */
	input	vmu_co_clah0_ac;	/* false carry out from multiplier vector 0 */
	input	vmu_co_clah1_ac;	/* false carry out from multiplier vector 1 */



/*
*	The next group are input signals to the control block from
*	the writeback stage of the vector unit datapaths.
*/


	input	vdp_acc0bit15_wb;	/* bit 15 of accumulator used to determine sign vector 0 */
	input	vdp_acc0bit21_wb;	/* bit 21 of accumulator used for macq vector 0 */
	input	vdp_acc0bit31_wb;	/* bit 31 of accumulator used to determine sign vector 0 */
	input	vdp_acc0bit47_wb;	/* bit 47 of accumulator used to determine sign vector 0 */

	input	vdp_achizero0_wb;	/* 47:32 of accumulator equal zero vector 0 */
	input	vdp_acmizero0_wb;	/* 31:16 of accumulator equal zero vector 0 */
	input	vdp_achione0_wb;	/* 47:32 of accumulator equal one vector 0 */

	input	vdp_acc1bit15_wb;	/* bit 15 of accumulator used to determine sign vector 1*/
	input	vdp_acc1bit21_wb;	/* bit 21 of accumulator used for macq vector 1 */
	input	vdp_acc1bit31_wb;	/* bit 31 of accumulator used to determine sign vector 1 */
	input	vdp_acc1bit47_wb;	/* bit 47 of accumulator used to determine sign vector 1 */

	input	vdp_achizero1_wb;	/* 47:32 of accumulator equal zero vector 1 */
	input	vdp_acmizero1_wb;	/* 31:16 of accumulator equal zero vector 1 */
	input	vdp_achione1_wb;	/* 47:32 of accumulator equal one vector 1 */


/*
*	The following input signals are for register file address decoding
*	only.
*/

	input	[4:0]	su_st_rnum_rd;		/* register number for stores */
	input	[4:0]	su_xp_rnum_rd;		/* register number for xpose stores */
	input	[4:0]	su_ld_rnum_ac;		/* register number for load */
	input	[4:0]	su_vs_addr_rd;		/* register number for vs read */
	input	[31:0]	su_vt_addr_rd;		/* register number for vt read */
	input	[4:0]	su_vd_addr_ac;		/* register number for datapath writeback */
	input		su_wbv_wr_en_ac;	/* write enable for datapath results */
	input	[3:0]	su_bwe_ac;		/* load port byte write enable */
	input		su_xposeop_rdac;	/* transpose op in rd (store) or ac (load) */
	input	[2:0]	vct_slice0;		/* slice number of register file decode use */
	input	[2:0]	vct_slice1;		/* slice number of register file decode use */


/*
*	The following signals are the output signals for the 
*	vector unit control block.
*
*	The first group are output control signals for the
*	register file read stage of the vector unit datapath.
*/

	output	[2:0]	vct_regopssl_rd;	/* select for VS register in RD stage */

	output	vct_qurtlosl_rd;		/* select VT scalar value from even vectors */
	output	vct_halflosl_rd;		/* select VT scalar value from 0,1,4,5 vectors */
	output	[2:0]	vct_whllosl_rd;		/* select VT scalar value from 0,1,2,3 vectors */

	output	vct_qurthisl_rd;		/* select VT scalar value from odd vectors */
	output	vct_halfhisl_rd;		/* select VT scalar value from 2,3,6,7 vectors */
	output	[2:0]	vct_whlhisl_rd;		/* select VT scalar value from 4,5,6,7 vectors */


/*
*	The next group are output control signals for the
*	multiply stage of the vector unit datapath.
*/

	output	[2:0]	vct_couprsl_mu;		/* select for multiply upper carry out vector */
	output	[2:0]	vct_smuprsl_mu;		/* select for multiply upper sum out vector */

	output	[2:0]	vct_colwrsl_mu;		/* selects for multiply lower carry out register all vectors */

	output	[2:0]	vct_smlwrsl0_mu;	/* selects for multiply lower sum out vector 0 */
	output	[2:0]	vct_smlwrsl1_mu;	/* selects for multiply lower sum out vector 1 */

	output	vct_sgnmplr_mu;			/* signed multiplier */
	output	vct_sgnmplcnd_mu;		/* signed multiplicand */
	output	vct_shftlftone_mu;		/* shift left by 1 for MULF, MACF, MULU, MACU */


	output	[4:0]	vct_aluctl0_mu;		/* control for alu vector 0 */
	output	vct_alucin0_mu;			/* carry in to alu vector 0 */
	output	vct_compvt0_mu;			/* complement vt for writing -VT for CH, CL, CR vector 0 */

	output	[4:0]	vct_aluctl1_mu;		/* control for alu vector 1 */
	output	vct_alucin1_mu;			/* carry in to alu vector 1 */
	output	vct_compvt1_mu;			/* complement vt for writing -VT for CH, CL, CR vector 1 */


/*
*	The next group are output control signals for the
*	accumulate stage of the vector unit datapath.
*/

	output	[2:0]	vct_aclwsl0_ac;		/* selects input for lower mux of accumulator vector 0 */
	output	[2:0]	vct_aclwsl1_ac;		/* selects input for lower mux of accumulator vector 1 */

	output	vct_cslwcsl_ac;			/* select for input c of lower csa all vectors */
	output	vct_csupcen0_ac;		/* input c enable for upper csa even vectors */
	output	vct_csupcen1_ac;		/* input c enable for upper csa odd vectors */

	output	[2:0]	vct_acmisl0_ac;		/* selects input for middle mux of accumulator vector 0 */
	output	[2:0]	vct_acmisl1_ac;		/* selects input for middle mux of accumulator vector 1 */

	output	[1:0]	vct_incrmxsl0_ac;	/* mux select for incrementer output vector 0 */
	output	[1:0]	vct_incrmxsl1_ac;	/* mux select for incrementer output vector 1 */

	output	[2:0]	vct_acupsl0_ac;		/* selects input for upper mux of accumulator vector 0 */
	output	[2:0]	vct_acupsl1_ac;		/* selects input for upper mux of accumulator vector 1 */

	output	[3:0]	vct_rndvlu0_ac;		/* round value for multiplies/byte adds vector 0 */
	output	[2:0]	vct_cslwasl0_ac;	/* selects for input a of lower csa vector 0 */
	output	[2:0]	vct_cslwbsl0_ac;	/* selects for input b of lower csa vector 0 */
	output	vct_addlwci0_ac;		/* carry in to lower adder vector 0 */
	output	[1:0]	vct_csupasl0_ac;	/* selects for input a of upper csa vector 0 */
	output	[1:0]	vct_csupbsl0_ac;	/* selects for input b of upper csa vector 0 */
	output	vct_incrdwn0_ac;		/* increment/decrement control signal vector 0 */
	output	vct_incrci0_ac;			/* increment/decrement enable signal vector 0 */

	output	[3:0]	vct_rndvlu1_ac;		/* round value for multiplies/byte adds vector 1 */
	output	[2:0]	vct_cslwasl1_ac;	/* selects for input a of lower csa vector 1 */
	output	[2:0]	vct_cslwbsl1_ac;	/* selects for input b of lower csa vector 1 */
	output	vct_addlwci1_ac;		/* carry in to lower adder vector 1 */
	output	[1:0]	vct_csupasl1_ac;	/* selects for input a of upper csa vector 1 */
	output	[1:0]	vct_csupbsl1_ac;	/* selects for input b of upper csa vector 1 */
	output	vct_incrdwn1_ac;		/* increment/decrement control signal vector 1 */
	output	vct_incrci1_ac;			/* increment/decrement enable signal vector 1 */


/*
*	The next group are output control signals for the
*	write back stage of the vector unit datapath.
*/

	output	[5:0]	vct_rsltsl0_wb;		/* selects for result mux vector 0 */
	output	[5:0]	vct_rsltsl1_wb;		/* selects for result mux vector 1 */

	output	[2:0]	vct_clprslt0_wb;	/* clamp value for all clamping vector 0 */
	output	[2:0]	vct_clprslt1_wb;	/* clamp value for all clamping vector 1 */

/*
*	The following output signals are for addressing the register file only.
*/
   	output	[31:0]  vct_rfadrt_hi0_wb;	/* decoded wb load high byte address element 0 */
   	output	[31:0]  vct_rfadrf_hi0_wb;	/* complement decoded wb load high byte address element 0 */
   	output	[31:0]  vct_rfadrt_lo0_wb;	/* decoded wb load low byte address element 0 */
   	output	[31:0]  vct_rfadrf_lo0_wb;	/* complement decoded wb load low byte address element 0 */
   	output	[31:0]  vct_rfadrt_st0_rd;	/* decoded rd store read address element 0 */
   	output	[31:0]  vct_rfadrf_st0_rd;	/* complement decoded rd store read address element 0 */

   	output	[31:0]  vct_rfadrt_vs0_rd;	/* decoded rd read vs address element 0 */
   	output	[31:0]  vct_rfadrf_vs0_rd;	/* complement decoded rf read vs address element 0 */
   	output	[31:0]  vct_rfadrt_vt0_rd;	/* decoded rd read vt address element 0 */
   	output	[31:0]  vct_rfadrf_vt0_rd;	/* complement decoded rf read vt address element 0 */
   	output	[31:0]  vct_rfadrt_vd0_wb;	/* decoded wb write vd address element 0 */
   	output	[31:0]  vct_rfadrf_vd0_wb;	/* complement decoded wb write vd address element 0 */

   	output	[31:0]  vct_rfadrt_hi1_wb;	/* decoded wb load high byte address element 1 */
   	output	[31:0]  vct_rfadrf_hi1_wb;	/* complement decoded wb load high byte address element 1 */
   	output	[31:0]  vct_rfadrt_lo1_wb;	/* decoded wb load low byte address element 1 */
   	output	[31:0]  vct_rfadrf_lo1_wb;	/* complement decoded wb load low byte address element 1 */
   	output	[31:0]  vct_rfadrt_st1_rd;	/* decoded rd store read address element 1 */
   	output	[31:0]  vct_rfadrf_st1_rd;	/* complement decoded rd store read address element 1 */

   	output	[31:0]  vct_rfadrt_vs1_rd;	/* decoded rd read vs address element 1 */
   	output	[31:0]  vct_rfadrf_vs1_rd;	/* complement decoded rf read vs address element 1 */
   	output	[31:0]  vct_rfadrt_vt1_rd;	/* decoded rd read vt address element 1 */
   	output	[31:0]  vct_rfadrf_vt1_rd;	/* complement decoded rf read vt address element 1 */
   	output	[31:0]  vct_rfadrt_vd1_wb;	/* decoded wb write vd address element 1 */
   	output	[31:0]  vct_rfadrf_vd1_wb;	/* complement decoded wb write vd address element 1 */

	output	su_storeinst_mu;	/* store from VU */
	output	su_storecfc2_mu;	/* store or move control from VU */

	inout	[3:0]	su_cont_to_from;	/* Data for moving to/from vector control registers. */



/*
*	Pipechain for instruction valid, instruction function, vs and element fields.
*/
	wire	vct_instvld_mu;		/* valid CP2 instruction in MU */
	wire	vct_instvld_ac;		/* valid CP2 instruction in AC */

	asdff #(1, 0)	vctinstvldffmu (vct_instvld_mu, su_instvld_rd, clk, reset_l );

	asdff #(1, 0)	vctinstvldffac (vct_instvld_ac, vct_instvld_mu, clk, reset_l );


	wire	[5:0]	vct_instfunc_mu;	/* function field of instruction in MU */
	wire	[5:0]	vct_instfunc_ac;	/* function field of instruction in AC */

	asdffen #(6, 0)	vctinstfuncffmu (vct_instfunc_mu, su_instfunc_rd, su_instvld_rd, clk, reset_l );

	asdffen #(6, 0)	vctinstfuncffac (vct_instfunc_ac, vct_instfunc_mu, vct_instvld_mu, clk, reset_l );


	wire	[2:0]	vct_vs_addr_rd;	/* vs field of instruction in RD */
	wire	[2:0]	vct_vs_addr_mu;	/* vs field of instruction in MU */
	wire	[2:0]	vct_vs_addr_ac;	/* vs field of instruction in AC */
	wire	[2:0]	vct_vs_addr_wb;	/* vs field of instruction in WB */

	assign	vct_vs_addr_rd =	su_vs_addr_rd[2:0];
	asdffen #(3, 0)	vctvsaddrffmu (vct_vs_addr_mu, vct_vs_addr_rd, su_instvld_rd, clk, reset_l );
	asdffen #(3, 0)	vctvsaddrffac (vct_vs_addr_ac, vct_vs_addr_mu, vct_instvld_mu, clk, reset_l );
	asdffen #(3, 0)	vctvsaddrffwb (vct_vs_addr_wb, vct_vs_addr_ac, vct_instvld_ac, clk, reset_l );


	wire	[4:0]	su_vd_addr_wb;		/* register number for datapath writeback */
	wire		su_wbv_wr_en_wb;	/* write enable for datapath results */
	wire	[3:0]	su_bwe_wb;		/* load port byte write enable */

	asdffen #(5, 0)	vctvdaddrrgwb (su_vd_addr_wb, su_vd_addr_ac, vct_instvld_ac, clk, reset_l );

	asdff #(1, 0)	vctwbvwrenffwb (su_wbv_wr_en_wb, su_wbv_wr_en_ac, clk, reset_l );

	asdff #(4, 0)	vctbweffwb (su_bwe_wb, su_bwe_ac, clk, reset_l );



	wire	[3:0]	vct_instelem_mu;	/* element field of instruction in MU */
	wire	[3:0]	vct_instelem_ac;	/* element field of instruction in AC */

	asdffen #(4, 0)	vctinstelemffmu (vct_instelem_mu, su_instelem_rd, su_instvld_rd, clk, reset_l );

	asdffen #(4, 0)	vctinstelemffac (vct_instelem_ac, vct_instelem_mu, vct_instvld_mu, clk, reset_l );



	wire	vct_vseqone_mu;		/* vs field of instruction equal to 1 in MU */
	wire	vct_vseqone_ac;		/* vs field of instruction equal to 1 in AC */

	asdffen #(1, 0)	vctvseqoneffmu (vct_vseqone_mu, su_vseqone_rd, su_instvld_rd, clk, reset_l );

	asdffen #(1, 0)	vctvseqoneffac (vct_vseqone_ac, vct_vseqone_mu, vct_instvld_mu, clk, reset_l );


	asdff #(1, 0)	vctstoreinstffmu (su_storeinst_mu, su_storeinst_rd, clk, reset_l );

	asdff #(1, 0)	vctstorecfc2ffmu (su_storecfc2_mu, su_storecfc2_rd, clk, reset_l );



/*
*	The following is the code for the instruction decode in the
*	RD stage.
*/

	wire	vct_elemsclr_rd;	/* Op which uses element field to select scalar operands */
	wire	vct_sarop_rd;		/* SAR instruction in RF stage. */
	wire	vct_rndop_rd;		/* RNDP or RNDN instructions in RF stage */

	assign	vct_sarop_rd =		su_instfunc_rd == `VSAR ;

	assign	vct_elemsclr_rd =	!vct_sarop_rd ;

	assign	vct_rndop_rd =		( su_instfunc_rd == `VRNDP ) || ( su_instfunc_rd == `VRNDN) ;

/*
*	Instruction decode of select instructions in the RD stage.
*/
	wire	vct_stgelcpop_rd;	/* select compare LT, EQ, NEQ ot VGE instruction in MU stage */

	assign	vct_stgelcpop_rd =	( su_instfunc_rd == `VLT ) || ( su_instfunc_rd == `VEQ ) ||
					( su_instfunc_rd == `VNE ) || ( su_instfunc_rd == `VGE ) ;

	wire	vct_stcrop_rd;		/* -VT <= VS <= VT select instruction 1's comp */

	assign	vct_stcrop_rd	=	su_instvld_rd && ( su_instfunc_rd == `VCR ) ;


/*
*	Instruction decode of add instructions in the RD stage.
*/

	wire	vct_subcop_rd;			/* SUBC instruction in RD */

	assign	vct_subcop_rd	=	( su_instfunc_rd == `VSUBC ) ;


	wire	vct_sbtypop_rd;		/* Subtract type VS-VT instruction in RD */

	assign	vct_sbtypop_rd =	(su_instfunc_rd == `VSUB) || (su_instfunc_rd == `VSUBC) ;


	wire	vct_vandop_rd;		/* VAND instruction in RD */

	assign	vct_vandop_rd =		( su_instfunc_rd == `VAND ) ;


	wire	vct_vnandop_rd;		/* VNAND instruction in RD */

	assign	vct_vnandop_rd =	( su_instfunc_rd == `VNAND ) ;


	wire	vct_vorop_rd;		/* VOR instruction in RD */

	assign	vct_vorop_rd =		( su_instfunc_rd == `VOR ) ;


	wire	vct_vnorop_rd;		/* VNOR instruction in RD */

	assign	vct_vnorop_rd =		( su_instfunc_rd == `VNOR ) ;


	wire	vct_vxorop_rd;		/* VXOR instruction in RD */

	assign	vct_vxorop_rd =		( su_instfunc_rd == `VXOR ) ;


	wire	vct_vxnorop_rd;		/* VXNOR instruction in RD */

	assign	vct_vxnorop_rd =	( su_instfunc_rd == `VXNOR ) ;


/*
*	The following is the code for the instruction decode in the
*	MU stage.
*/
/*
*	Instruction decoding for select ops in MU stage.
*/

	wire	vct_stcpop_mu;		/* select compare instruction in MU stage */

	assign	vct_stcpop_mu	=	( vct_instfunc_mu == `VLT ) || ( vct_instfunc_mu == `VEQ ) ||
					( vct_instfunc_mu == `VNE ) || ( vct_instfunc_mu == `VGE ) ||
					( vct_instfunc_mu == `VCH ) || ( vct_instfunc_mu == `VCR ) ||
					( vct_instfunc_mu == `VCL ) ;
/*
*	The data to the vector unit control register is a timing critical path therefore valid
*	is taken into account at the instruction decode level to eliminate it from the critical
*	timing of the data.
*/

	wire	vct_stltop_mu;		/* VS < VT select instruction in MU stage */

	assign	vct_stltop_mu	=	vct_instvld_mu && ( vct_instfunc_mu == `VLT ) ;


	wire	vct_steqop_mu;		/* VS == VT select instruction in MU stage */

	assign	vct_steqop_mu	=	vct_instvld_mu && ( vct_instfunc_mu == `VEQ ) ;


	wire	vct_stneop_mu;		/* VS != VT select instruction in MU stage */

	assign	vct_stneop_mu	=	vct_instvld_mu && ( vct_instfunc_mu == `VNE ) ;


	wire	vct_stgeop_mu;		/* VS >= VT select instruction in MU stage */

	assign	vct_stgeop_mu	=	vct_instvld_mu && ( vct_instfunc_mu == `VGE ) ;

/*
*	The signals vct_stchop_mu, vct_stclop_mu and vct_stcrop_mu are decoded in the 
*	RD stage and then register so that they available early in the cycle for 
*	generating the vct_aluctl_mu and vct_alucin_mu signals.	
*/
	wire	vct_stchop_rd;		/* -VT <= VS <= VT select instruction 2's comp single precison */
	wire	vct_stchop_mu;		/* -VT <= VS <= VT select instruction 2's comp single precison */

	assign	vct_stchop_rd	=	su_instvld_rd && ( su_instfunc_rd == `VCH ) ;

	asdff #(1, 0)	vctstchopffmu (vct_stchop_mu, vct_stchop_rd, clk, reset_l );


	wire	vct_stchrop_rd;		/* -VT <= VS <= VT select instruction 2's or 1's comp */
	wire	vct_stchrop_mu;		/* -VT <= VS <= VT select instruction 2's or 1's comp */

	assign	vct_stchrop_rd	=	su_instvld_rd && ( vct_stchop_rd || vct_stcrop_rd ) ;

	asdff #(1, 0)	vctstchropffmu (vct_stchrop_mu, vct_stchrop_rd, clk, reset_l );


	wire	vct_stclop_rd;		/* -VT<=VS<=VT select instruction 2's comp double precision*/
	wire	vct_stclop_mu;		/* -VT<=VS<=VT select instruction 2's comp double precision*/

	assign	vct_stclop_rd	=	su_instvld_rd && ( su_instfunc_rd == `VCL ) ;

	asdff #(1, 0)	vctstclopffmu (vct_stclop_mu, vct_stclop_rd, clk, reset_l );


	wire	vct_stcrop_mu;		/* -VT<=VS<=VT select instruction 1's comp */

	asdff #(1, 0)	vctstcropffmu (vct_stcrop_mu, vct_stcrop_rd, clk, reset_l );



	wire	vct_stmrgop_mu;		/* MERGE select instruction in MU stage */

	assign	vct_stmrgop_mu	=	( vct_instfunc_mu == `VMRG ) ;


/*
*	Instruction decoding for adds and subtracts in MU stage.
*/
	wire	vct_absop_rd;		/* ABS instruction in RD stage. */
	wire	vct_absop_mu;		/* ABS instruction in MU stage. */

	assign	vct_absop_rd =	( su_instfunc_rd == `VABS ) ;

	asdffen #(1, 0)	vctabsopffmu (vct_absop_mu, vct_absop_rd, su_instvld_rd, clk, reset_l );


	wire	vct_addcop_mu;			/* ADDC instruction in MU */

	assign	vct_addcop_mu	=	( vct_instfunc_mu == `VADDC ) ;


	wire	vct_addop_rd;			/* ADD instruction in RD */
	wire	vct_addop_mu;			/* ADD instruction in MU */
	wire	vct_addop_ac;			/* ADD instruction in AC */

	assign	vct_addop_rd	=	( su_instfunc_rd == `VADD ) ;

	asdffen #(1, 0)	vctaddopffmu (vct_addop_mu, vct_addop_rd, su_instvld_rd, clk, reset_l );

	asdffen #(1, 0)	vctaddopffac (vct_addop_ac, vct_addop_mu, vct_instvld_mu, clk, reset_l );


	wire	vct_subcop_mu;			/* SUBC instruction in MU */

	assign	vct_subcop_mu	=	( vct_instfunc_mu == `VSUBC ) ;


	wire	vct_addspop_mu;			/* Single precision add/sub instruction in MU */

	assign	vct_addspop_mu	=	( vct_instfunc_mu == `VADD ) ||
					( vct_instfunc_mu == `VSUB ) ;

	wire	vct_subop_rd;			/* SUB instruction in RD */
	wire	vct_subop_mu;			/* SUB instruction in MU */
	wire	vct_subop_ac;			/* SUB instruction in AC */

	assign	vct_subop_rd	=	( su_instfunc_rd == `VSUB ) ;

	asdffen #(1, 0)	vctsubopffmu (vct_subop_mu, vct_subop_rd, su_instvld_rd, clk, reset_l );

	asdffen #(1, 0)	vctsubopffac (vct_subop_ac, vct_subop_mu, vct_instvld_mu, clk, reset_l );

	wire	vct_substclop_rd;	/* sub or -VT<=VS<=VT select op 2's comp double precision*/
	wire	vct_substclop_mu;	/* sub or -VT<=VS<=VT select op 2's comp double precision*/

	assign	vct_substclop_rd =	vct_stclop_rd || vct_subop_rd ;

	asdffen #(1, 0)	vctsubstclopffmu (vct_substclop_mu, vct_substclop_rd, su_instvld_rd, clk, reset_l );



/*
*	Instruction decoding for multiplies in MU stage.
*/

	wire	vct_mulfop_mu ;		/* MULF instruction in MU stage. */
	wire	vct_macfop_mu ;		/* MACF instruction in MU stage. */
	wire	vct_muluop_mu ;		/* MULU instruction in MU stage. */
	wire	vct_macuop_mu ;		/* MACU instruction in MU stage. */
	wire	vct_mulqop_mu ;		/* MULQ instruction in MU stage. */
	wire	vct_macqop_mu ;		/* MACQ instruction in MU stage. */
	wire	vct_mudlop_mu ;		/* MUDL instruction in MU stage. */
	wire	vct_madlop_mu ;		/* MADL instruction in MU stage. */
	wire	vct_mudmop_mu ;		/* MUDM instruction in MU stage. */
	wire	vct_madmop_mu ;		/* MADM instruction in MU stage. */
	wire	vct_mudnop_mu ;		/* MUDN instruction in MU stage. */
	wire	vct_madnop_mu ;		/* MADN instruction in MU stage. */
	wire	vct_mudhop_mu ;		/* MUDH instruction in MU stage. */
	wire	vct_madhop_mu ;		/* MADH instruction in MU stage. */


	assign	vct_mulfop_mu =	( vct_instfunc_mu == `VMULF ) ;

	assign	vct_macfop_mu =	( vct_instfunc_mu == `VMACF ) ;

	assign	vct_muluop_mu =	( vct_instfunc_mu == `VMULU ) ;

	assign	vct_macuop_mu =	( vct_instfunc_mu == `VMACU ) ;

	assign	vct_mulqop_mu =	( vct_instfunc_mu == `VMULQ ) ;

	assign	vct_macqop_mu =	( vct_instfunc_mu == `VMACQ ) ;

	assign	vct_mudlop_mu =	( vct_instfunc_mu == `VMUDL ) ;

	assign	vct_madlop_mu =	( vct_instfunc_mu == `VMADL ) ;

	assign	vct_mudmop_mu =	( vct_instfunc_mu == `VMUDM ) ;

	assign	vct_madmop_mu =	( vct_instfunc_mu == `VMADM ) ;

	assign	vct_mudnop_mu =	( vct_instfunc_mu == `VMUDN ) ;

	assign	vct_madnop_mu =	( vct_instfunc_mu == `VMADN ) ;

	assign	vct_mudhop_mu =	( vct_instfunc_mu == `VMUDH ) ;

	assign	vct_madhop_mu =	( vct_instfunc_mu == `VMADH ) ;



	wire	vct_multtypop_mu;	/* Multiply type instruction not MACQ in MU stage. */

	assign	vct_multtypop_mu =	vct_mulfop_mu || vct_macfop_mu ||
					vct_muluop_mu || vct_macuop_mu ||
					vct_mulqop_mu ||
					vct_mudlop_mu || vct_madlop_mu ||
					vct_mudmop_mu || vct_madmop_mu ||
					vct_mudnop_mu || vct_madnop_mu ||
					vct_mudhop_mu || vct_madhop_mu ;

					
	wire	vct_vs_sgnmu_mu;		/* Multiply instruction with operand s signed */



	assign	vct_vs_sgnmu_mu	=	vct_mulfop_mu || vct_macfop_mu ||
					vct_muluop_mu || vct_macuop_mu ||
					vct_mulqop_mu || vct_macqop_mu ||
					vct_mudmop_mu || vct_madmop_mu ||
					vct_mudhop_mu || vct_madhop_mu ;


	wire	vct_vt_sgnmu_mu;		/* Multiply instruction with operand t signed */

	assign	vct_vt_sgnmu_mu	=	vct_mulfop_mu || vct_macfop_mu ||
					vct_muluop_mu || vct_macuop_mu ||
					vct_mulqop_mu || vct_macqop_mu ||
					vct_mudnop_mu || vct_madnop_mu ||
					vct_mudhop_mu || vct_madhop_mu ;


	wire	vct_rndpop_mu;		/* RNDP op in MU stage */
	wire	vct_rndnop_mu;		/* RNDN op in MU stage */
	wire	vct_rndop_mu;		/* Round op in MU stage */

	assign	vct_rndpop_mu =		( vct_instfunc_mu == `VRNDP ) ;

	assign	vct_rndnop_mu =		( vct_instfunc_mu == `VRNDN ) ;

	assign	vct_rndop_mu =		vct_rndpop_mu || vct_rndnop_mu ;


	wire	vct_dvnomovop_mu;	/* Divide type op other than move in MU */
	wire	vct_dvnomovop_ac;	/* Divide type op other than move in AC */
	wire	vct_divrsltsl_wb;	/* Divide type op other than move in WB */

	assign	vct_dvnomovop_mu =	( vct_instfunc_mu == `VRCP ) || ( vct_instfunc_mu == `VRCPL ) || 
					( vct_instfunc_mu == `VRCPH ) || ( vct_instfunc_mu == `VRSQ ) ||
					( vct_instfunc_mu == `VRSQL ) || ( vct_instfunc_mu == `VRSQH ) ;
	
	asdffen #(1, 0)	vctdvnomovopac (vct_dvnomovop_ac, vct_dvnomovop_mu, vct_instvld_mu, clk, reset_l );
	asdffen #(1, 0)	vctdivrsltslwb (vct_divrsltsl_wb, vct_dvnomovop_ac, vct_instvld_ac, clk, reset_l );


	wire	vct_dvmovop_mu;		/* Divide move op in MU */
	wire	vct_dvmovop_ac;		/* Divide move op in AC */

	assign	vct_dvmovop_mu =	( vct_instfunc_mu == `VMOV ) ;	

	asdffen #(1, 0)	vctdvmovopac (vct_dvmovop_ac, vct_dvmovop_mu, vct_instvld_mu, clk, reset_l );


	wire	vct_dvtypop_mu;	/* divide or move type instruction in MU */
	wire	vct_dvtypop_ac;	/* divide or move type instruction in AC */
	wire	vct_dvtypop_wb;	/* divide or move type instruction in WB */

	assign	vct_dvtypop_mu =	vct_dvnomovop_mu || vct_dvmovop_mu;

	asdffen #(1, 0)	vctdvtypopac (vct_dvtypop_ac, vct_dvtypop_mu, vct_instvld_mu, clk, reset_l );
	asdffen #(1, 0)	vctdvtypopwb (vct_dvtypop_wb, vct_dvtypop_ac, vct_instvld_ac, clk, reset_l );


/*
*	Instruction decoding to determine loading of Vector carry out and vector compare code
*	registers other than explicit move to control instruction.
*/
	wire	vct_cryoutld_mu;		/* Load enable for vector carry out/equal register */

	assign	vct_cryoutld_mu	=	( vct_instvld_mu &&
					  ( vct_addcop_mu || vct_subcop_mu || /* actual setting of VCO bits */
					    vct_addspop_mu || vct_stcpop_mu ||   /* Clear VCO on select instructions */
					    vct_stmrgop_mu
					  ) 
					) ||
					su_wrcryout_wb ;

	wire	vct_cmpcdld_mu;		/* Load enable for vector compare code register */

	assign	vct_cmpcdld_mu	=	( vct_instvld_mu && vct_stcpop_mu ) || su_wrcmpcd_wb ;


	wire	vct_cmpcdadld_mu;	/* Load enable for vector compare add register */

	assign	vct_cmpcdadld_mu =	( vct_instvld_mu && 
					  ( vct_stcrop_mu || vct_stchop_mu || vct_stclop_mu )
					) || 
					su_wrcmpcdad_wb ;



/*
*	The following is the code for the instruction decode in the
*	AC stage.
*/

	wire	vct_absop_ac;			/* ABS instruction in AC stage. */

	asdffen #(1, 0)	vctabsopffac (vct_absop_ac, vct_absop_mu, vct_instvld_mu, clk, reset_l );


	wire	vct_stcpop_ac;			/* select compare/merge instruction in AC stage. */

	assign	vct_stcpop_ac	=	( vct_instfunc_ac == `VLT ) || ( vct_instfunc_ac == `VEQ ) ||
					( vct_instfunc_ac == `VNE ) || ( vct_instfunc_ac == `VGE ) ||
					( vct_instfunc_ac == `VCH ) || ( vct_instfunc_ac == `VCR ) ||
					( vct_instfunc_ac == `VCL ) || ( vct_instfunc_ac == `VMRG ) ;

	wire	vct_stchop_ac;		/* -VT<=VS<=VT select op 2's comp single precison */

	asdffen #(1, 0)	vctstchopffac (vct_stchop_ac, vct_stchop_mu, vct_instvld_mu, clk, reset_l );

	wire	vct_stclop_ac;		/* -VT<=VS<=VT select op 2's comp double precision*/

	asdffen #(1, 0)	vctstclopffac (vct_stclop_ac, vct_stclop_mu, vct_instvld_mu, clk, reset_l );

	wire	vct_stnclrdop_ac;		/* Select instruction that is not CL, CLD or CR */

	assign	vct_stnclrdop_ac	=	( vct_instfunc_ac == `VLT ) || ( vct_instfunc_ac == `VEQ ) ||
						( vct_instfunc_ac == `VNE ) || ( vct_instfunc_ac == `VGE )  ||
						( vct_instfunc_ac == `VMRG ) ;


	wire	vct_stclrdop_ac;		/* Select instruction that is CL, CLD or CR */

	assign	vct_stclrdop_ac	=	( vct_instfunc_ac == `VCH ) || ( vct_instfunc_ac == `VCL ) ||
					( vct_instfunc_ac == `VCR ) ;


	wire	vct_mulfop_ac ;		/* MULF instruction in AC stage. */
	wire	vct_macfop_ac ;		/* MACF instruction in AC stage. */
	wire	vct_muluop_ac ;		/* MULU instruction in AC stage. */
	wire	vct_macuop_ac ;		/* MACU instruction in AC stage. */
	wire	vct_rndpop_ac ;		/* RNDP instruction in AC stage. */
	wire	vct_rndnop_ac ;		/* RNDN instruction in AC stage. */
	wire	vct_mulqop_ac ;		/* MULQ instruction in AC stage. */
	wire	vct_macqop_ac ;		/* MACQ instruction in AC stage. */
	wire	vct_mudlop_ac ;		/* MUDL instruction in AC stage. */
	wire	vct_madlop_ac ;		/* MADL instruction in AC stage. */
	wire	vct_mudmop_ac ;		/* MUDM instruction in AC stage. */
	wire	vct_madmop_ac ;		/* MADM instruction in AC stage. */
	wire	vct_mudnop_ac ;		/* MUDN instruction in AC stage. */
	wire	vct_madnop_ac ;		/* MADN instruction in AC stage. */
	wire	vct_mudhop_ac ;		/* MUDH instruction in AC stage. */
	wire	vct_madhop_ac ;		/* MADH instruction in AC stage. */

/*
*	To improve timing many of the instruction decode signals are deocded in
*	the multiply stage and piped along to the accumulator stage.
*/

	asdffen #(1, 0)	vctmulfopffac (vct_mulfop_ac, vct_mulfop_mu, vct_instvld_mu, clk, reset_l );

	asdffen #(1, 0)	vctmacfopffac (vct_macfop_ac, vct_macfop_mu, vct_instvld_mu, clk, reset_l );

	asdffen #(1, 0)	vctmuluopffac (vct_muluop_ac, vct_muluop_mu, vct_instvld_mu, clk, reset_l );

	asdffen #(1, 0)	vctmacuopffac (vct_macuop_ac, vct_macuop_mu, vct_instvld_mu, clk, reset_l );

	asdffen #(1, 0)	vctrndpopffac (vct_rndpop_ac, vct_rndpop_mu, vct_instvld_mu, clk, reset_l );

	asdffen #(1, 0)	vctrndnopffac (vct_rndnop_ac, vct_rndnop_mu, vct_instvld_mu, clk, reset_l );

	asdffen #(1, 0)	vctmulqopffac (vct_mulqop_ac, vct_mulqop_mu, vct_instvld_mu, clk, reset_l );

	asdffen #(1, 0)	vctmacqopffac (vct_macqop_ac, vct_macqop_mu, vct_instvld_mu, clk, reset_l );

	asdffen #(1, 0)	vctmudlopffac (vct_mudlop_ac, vct_mudlop_mu, vct_instvld_mu, clk, reset_l );

	asdffen #(1, 0)	vctmadlopffac (vct_madlop_ac, vct_madlop_mu, vct_instvld_mu, clk, reset_l );

	asdffen #(1, 0)	vctmudmopffac (vct_mudmop_ac, vct_mudmop_mu, vct_instvld_mu, clk, reset_l );

	asdffen #(1, 0)	vctmadmopffac (vct_madmop_ac, vct_madmop_mu, vct_instvld_mu, clk, reset_l );

	asdffen #(1, 0)	vctmudnopffac (vct_mudnop_ac, vct_mudnop_mu, vct_instvld_mu, clk, reset_l );

	asdffen #(1, 0)	vctmadnopffac (vct_madnop_ac, vct_madnop_mu, vct_instvld_mu, clk, reset_l );

	asdffen #(1, 0)	vctmudhopffac (vct_mudhop_ac, vct_mudhop_mu, vct_instvld_mu, clk, reset_l );

	asdffen #(1, 0)	vctmadhopffac (vct_madhop_ac, vct_madhop_mu, vct_instvld_mu, clk, reset_l );


/*
*	Use multiply type op signal from the MU stage.
*/

	wire	vct_multtypop_ac;		/* Multiply type op other than MACQ in AC */

	asdffen #(1, 0)	vctmulttypopffac (vct_multtypop_ac, vct_multtypop_mu, vct_instvld_mu, clk, reset_l );


	wire	vct_multndlop_mu;		/* Multiply type op other than MACQ in MU */
	wire	vct_multndlop_ac;		/* Multiply type op other than MACQ in AC */

	assign	vct_multndlop_mu =	vct_mulfop_mu || vct_macfop_mu ||
					vct_muluop_mu || vct_macuop_mu ||
					vct_mulqop_mu ||
					vct_mudmop_mu || vct_madmop_mu ||
					vct_mudnop_mu || vct_madnop_mu ||
					vct_mudhop_mu || vct_madhop_mu ;


	asdffen #(1, 0)	vctmultndlopffac (vct_multndlop_ac, vct_multndlop_mu, vct_instvld_mu, clk, reset_l );


	wire	vct_multactyp_mu;	/* MACF, MACU, MADL, MADM, MADN, RNDP and RNDP type ops */
	wire	vct_multactyp_ac;	/* MACF, MACU, MADL, MADM, MADN, RNDP and RNDP type ops */

	assign	vct_multactyp_mu =	( vct_macfop_mu || vct_macuop_mu ||
					  vct_madlop_mu || vct_madmop_mu ||
					  vct_madnop_mu || vct_rndpop_mu || vct_rndnop_mu
					) ;

	asdffen #(1, 0)	vctmultactypopffac (vct_multactyp_ac, vct_multactyp_mu, vct_instvld_mu, clk, reset_l );


	wire	vct_multincop_mu;	/* MACF, MACU, MADL, MADM and MADN type ops */
	wire	vct_multincop_ac;	/* MACF, MACU, MADL, MADM and MADN type ops */

	assign	vct_multincop_mu =	( vct_macfop_mu || vct_macuop_mu ||
					  vct_madlop_mu || vct_madmop_mu ||
					  vct_madnop_mu
					) ;

	asdffen #(1, 0)	vctmultincopffac (vct_multincop_ac, vct_multincop_mu, vct_instvld_mu, clk, reset_l );



	wire	vct_sarop_ac;		/* SAR instruction in AC stage. */

	assign	vct_sarop_ac =		vct_instfunc_ac == `VSAR ;



	wire	vct_addtypop_ac;	/* Add type instruction in the AC stage */

	assign	vct_addtypop_ac = ( vct_instfunc_ac == `VADD ) || ( vct_instfunc_ac == `VSUB ) || 
				  ( vct_instfunc_ac == `VADDC ) || ( vct_instfunc_ac == `VSUBC ) ||
				  ( vct_instfunc_ac == `VABS ) ;	



	wire	vct_logtypop_ac;	/* logical type instruction in the WB stage */

	assign	vct_logtypop_ac = ( vct_instfunc_ac == `VAND ) || ( vct_instfunc_ac == `VNAND ) || 
				  ( vct_instfunc_ac == `VOR ) || ( vct_instfunc_ac == `VNOR ) || 
				  ( vct_instfunc_ac == `VXOR ) || ( vct_instfunc_ac == `VXNOR ) ;




/*
*	The following is the decoding of the VS and VD register file 
*	addrress.  Does the 5 to 32 bit decoding producing the true
*	and complement.
*/

   	wire	[31:0]  vurfile_vs_t;	/* decoded rd read vs address true */
   	wire	[31:0]  vurfile_vs_f;	/* decoded rd read vs address complement */

regfile_decode decode_vs (	.rNumdecode	(vurfile_vs_t),  
				.rNumdecode_b	(vurfile_vs_f),  
				.rNum		(su_vs_addr_rd) 
			 );

	assign	vct_rfadrt_vs0_rd =	vurfile_vs_t ;

	assign	vct_rfadrt_vs1_rd =	vurfile_vs_t ;

	assign	vct_rfadrf_vs0_rd =	vurfile_vs_f ;

	assign	vct_rfadrf_vs1_rd =	vurfile_vs_f ;


   	wire	[31:0]  vurfile_vt_t;	/* decoded rd read vt address true */
   	wire	[31:0]  vurfile_vt_f;	/* decoded rd read vt address complement */

/*
*	Removed since register file decoding is now done in
*	scalar unit.	
*
* regfile_decode decode_vt (	.rNumdecode	(vurfile_vt_t),  
*				.rNumdecode_b	(vurfile_vt_f),  
*				.rNum		(su_vt_addr_rd) 
*			  );
*
*	assign	vct_rfadrt_vt0_rd =	vurfile_vt_t ;
*
*	assign	vct_rfadrt_vt1_rd =	vurfile_vt_t ;
*
*	assign	vct_rfadrf_vt0_rd =	vurfile_vt_f ;
*
*	assign	vct_rfadrf_vt1_rd =	vurfile_vt_f ;
*/

	buffer_ninv vctvtaddr0ninvrd	(	.vt_addr_in	(su_vt_addr_rd),
						.vt_addr_out	(vct_rfadrt_vt0_rd)
					);

	buffer_ninv vctvtaddr1ninvrd	(	.vt_addr_in	(su_vt_addr_rd),
						.vt_addr_out	(vct_rfadrt_vt1_rd)
					);


	buffer_inv vctvtaddr0invrd	(	.vt_addr_in	 (su_vt_addr_rd),
						.vt_addr_out_inv (vct_rfadrf_vt0_rd)
					);

	buffer_inv vctvtaddr1invrd	(	.vt_addr_in	 (su_vt_addr_rd),
						.vt_addr_out_inv (vct_rfadrf_vt1_rd)
					);


/*
*	The following are output control signals for the
*	register file read stage of the vector unit datapath.
*/


	assign	vct_regopssl_rd[0] =	!su_instvld_rd && reset_l ;

	assign	vct_regopssl_rd[1] =	su_instvld_rd && reset_l && !vct_rndop_rd;

	assign	vct_regopssl_rd[2] =	0 ;


	assign	vct_qurtlosl_rd =	vct_elemsclr_rd &&
					(
					  ( su_instelem_rd == 4'h3 ) ||	/* quarter even element */
					  ( (su_instelem_rd[3:2] == 2'b01) && su_instelem_rd[0] ) ||
										/* half even element */
					  ( su_instelem_rd[3] && su_instelem_rd[0] ) 	/* whole even element */
					) ;

	assign	vct_halflosl_rd =	vct_elemsclr_rd &&
					(
					  ( su_instelem_rd[3:1] == 3'b011 ) ||	     /* half element from 2,3,6,7 */
					  ( su_instelem_rd[3] && su_instelem_rd[1] ) /* whole element from 2,3,6,7 */
					) ;

	assign	vct_whllosl_rd[0] =	reset_l && !su_instvld_rd ;

	assign	vct_whllosl_rd[1] =	reset_l && su_instvld_rd && 
					( !vct_elemsclr_rd || (su_instelem_rd[3:2] != 2'b11) ) ;

	assign	vct_whllosl_rd[2] =	reset_l && su_instvld_rd &&		/* whole element from 4-7 */  
					vct_elemsclr_rd && (su_instelem_rd[3:2] == 2'b11) ;


	assign	vct_qurthisl_rd =	vct_elemsclr_rd &&
					(
					  ( su_instelem_rd == 4'h2 ) ||			/* quarter odd element */
					  ( (su_instelem_rd[3:2] == 2'b01) && !su_instelem_rd[0] ) || /* half odd element */
					  ( su_instelem_rd[3] && !su_instelem_rd[0] ) 	/* whole odd element */
					) ;

	assign	vct_halfhisl_rd =	vct_elemsclr_rd &&
					(
					  ( su_instelem_rd[3:1] == 3'b010 ) ||		/* half element from 0,1,4,5 */
					  ( su_instelem_rd[3] && !su_instelem_rd[1] )	/* whole element from 0,1,4,5 */
					) ;

	assign	vct_whlhisl_rd[0] =	reset_l && !su_instvld_rd ;

	assign	vct_whlhisl_rd[1] =	reset_l && su_instvld_rd &&
					( !vct_elemsclr_rd || (su_instelem_rd[3:2] != 2'b10) ) ;

	assign	vct_whlhisl_rd[2] =	reset_l && su_instvld_rd &&		/* whole element from 4-7 */  
					vct_elemsclr_rd && (su_instelem_rd[3:2] == 2'b10) ;


/*
*	The next group are output control signals for the
*	multiply stage of the vector unit datapath.
*/
/*
*	This code does the decoding of the instructions for generation of the alu control
*	and alu carry in signals that is NOT dependent on the data.  These signals are 
*	then sent to vuctlsl.v where they are gated with specific data values of the 
*	datapath, such as signs or carry out, to produce the final signals which control
*	the datapath.
*/

	wire	[4:0]	vct_aluprectl_rd;	/* alu control signals without operand signs rd stg */
	wire	[3:0]	vct_aluprectl_mu;	/* alu control signals without operand signs mu stg */

/*
*	assign	vct_aluprectl_rd =	( su_instfunc_rd == `VAND ) ? 5'h14
*					  : ( su_instfunc_rd == `VNAND ) ? 5'h1c
*					    : ( su_instfunc_rd == `VOR ) ? 5'h1f
*					      : ( su_instfunc_rd == `VNOR ) ? 5'h17
*						: ( su_instfunc_rd == `VXOR ) ? 5'h11
*						  : ( su_instfunc_rd == `VXNOR ) ? 5'h10
*						    : ( vct_sbtypop_rd || vct_stgelcpop_rd ) ? 5'h01
*						      : 5'h00 ;
*/

	assign	vct_aluprectl_rd[0] =	vct_vorop_rd || vct_vnorop_rd || vct_vxorop_rd ||
					vct_sbtypop_rd || vct_stgelcpop_rd ;

	assign	vct_aluprectl_rd[1] =	vct_vorop_rd || vct_vnorop_rd ;

	assign	vct_aluprectl_rd[2] =	vct_vandop_rd || vct_vnandop_rd || 
					vct_vorop_rd || vct_vnorop_rd ;

	assign	vct_aluprectl_rd[3] =	vct_vnandop_rd || vct_vorop_rd ;

	assign	vct_aluprectl_rd[4] =	vct_vandop_rd || vct_vnandop_rd || 
					vct_vorop_rd || vct_vnorop_rd || 
					vct_vxorop_rd || vct_vxnorop_rd ;


	asdffen #(4, 0)	vctaluctlrgmu (vct_aluprectl_mu, vct_aluprectl_rd[4:1], su_instvld_rd, clk, reset_l );


	wire	vct_aluprecin_rd;		/* carry in to alu decoded subtract instructions */

	assign	vct_aluprecin_rd =	vct_subcop_rd || vct_stgelcpop_rd ||
					vct_stcrop_rd ;
					/* for one's complement VS+VT+1<=0 or VS-VT>=0 */



/*
*	The next portion of code handles the move from CP2 control registers by muxing between 
*	the vector compare code register, vector carry out register and the data from the 
*	store data port of the register file of vector 0.  The store data port also provides the
*	data for the move from CP2 registers.
*/
	wire	vct_cmpcdhi0_ac;	/* high bit from Vector Compare code register - vector 0 */
	wire	vct_cmpcdhi1_ac;	/* high bit from Vector Compare code register - vector 1 */

	wire	vct_cmpcdlo0_ac;	/* low bit from Vector Compare code register - vector 0 */
	wire	vct_cmpcdlo1_ac;	/* low bit from Vector Compare code register - vector 1 */

	wire	vct_cmpcdad0_ac;	/* Flag for Vector Compare Add register - vector 0 */
	wire	vct_cmpcdad1_ac;	/* Flag for Vector Compare Add register - vector 1 */

	wire	vct_opdneql0_ac;	/* operands not equal flag from Vector Carry out register - vector 0 */
	wire	vct_opdneql1_ac;	/* operands not equal flag from Vector Carry out register - vector 1 */

	wire	vct_cryout0_ac;		/* carry out flag from Vector Carry out register - vector 0 */
	wire	vct_cryout1_ac;		/* carry out flag from Vector Carry out register - vector 1 */



	wire	su_rdcmpcd_mu;		/* read vector compare code register */
	wire	su_rdcryout_mu;		/* read vector carry out register */
	wire	su_rdcmpcdad_mu;	/* read vector compare add register */
	wire	[3:0]	vct_contbus_mu;	/* output control bus to tristate drivers */
	wire	vct_contbusen_mu;		/* output enable to tristate drivers */

	asdff #(1, 0)	vctrdcmpcdffmu (su_rdcmpcd_mu, su_rdcmpcd_rd, clk, reset_l );
	asdff #(1, 0)	vctrdcryoutffmu (su_rdcryout_mu, su_rdcryout_rd, clk, reset_l );
	asdff #(1, 0)	vctrdcmpcdadffmu (su_rdcmpcdad_mu, su_rdcmpcdad_rd, clk, reset_l );


/*	The following code was replaced with instantiated gates so that I could control
*	the 3 state output driver and timing through the mux.
*/

/*	This code was replaced by instantiated muxes for timing reasons.
*
*	assign	vct_contbus_mu =	su_rdcryout_mu ?
*					    {
*						vct_opdneql1_ac,vct_opdneql0_ac,
*						vct_cryout1_ac,vct_cryout0_ac 
*					    }
*						: su_rdcmpcdad_mu ?
*						    {
*							2'h0,
*							vct_cmpcdad1_ac,vct_cmpcdad0_ac 
*						    }
*						:
*						    {
*							vct_cmpcdhi1_ac,vct_cmpcdhi0_ac,
*							vct_cmpcdlo1_ac,vct_cmpcdlo0_ac 
*						    } ;
*
*/

	wire	[3:0]	vct_contbusin_ac;	/* output of mux selecting between VCA and VCC */

	mx21d1	vctcontbusmx0mu	(	.z		(vct_contbus_mu[0]), 
					.i0		(vct_contbusin_ac[0]), 
					.i1		(vct_cryout0_ac), 
					.s		(su_rdcryout_mu) 
				) ;
	mx21d1	vctcontbusmx1mu	(	.z		(vct_contbus_mu[1]), 
					.i0		(vct_contbusin_ac[1]), 
					.i1		(vct_cryout1_ac), 
					.s		(su_rdcryout_mu) 
				) ;
	mx21d1	vctcontbusmx2mu	(	.z		(vct_contbus_mu[2]), 
					.i0		(vct_contbusin_ac[2]), 
					.i1		(vct_opdneql0_ac), 
					.s		(su_rdcryout_mu) 
				) ;
	mx21d1	vctcontbusmx3mu	(	.z		(vct_contbus_mu[3]), 
					.i0		(vct_contbusin_ac[3]), 
					.i1		(vct_opdneql1_ac), 
					.s		(su_rdcryout_mu) 
				) ;

	mx21d1	vctcontbusin0mu	(	.z		(vct_contbusin_ac[0]), 
					.i0		(vct_cmpcdlo0_ac), 
					.i1		(vct_cmpcdad0_ac), 
					.s		(su_rdcmpcdad_mu) 
				) ;
	mx21d1	vctcontbusin1mu	(	.z		(vct_contbusin_ac[1]), 
					.i0		(vct_cmpcdlo1_ac), 
					.i1		(vct_cmpcdad1_ac), 
					.s		(su_rdcmpcdad_mu) 
				) ;


	assign	vct_contbusin_ac[2] =	vct_cmpcdhi0_ac && !su_rdcmpcdad_mu ;

	assign	vct_contbusin_ac[3] =	vct_cmpcdhi1_ac && !su_rdcmpcdad_mu ;


	assign	vct_contbusen_mu =	su_rdcryout_mu || su_rdcmpcdad_mu || su_rdcmpcd_mu ;


	nt01d3	vctcontbus0nt	(
					.z		(su_cont_to_from[0]),
					.oe		(vct_contbusen_mu),
					.i		(vct_contbus_mu[0])
				) ;

	nt01d3	vctcontbus1nt	(
					.z		(su_cont_to_from[1]),
					.oe		(vct_contbusen_mu),
					.i		(vct_contbus_mu[1])
				) ;

	nt01d3	vctcontbus2nt	(
					.z		(su_cont_to_from[2]),
					.oe		(vct_contbusen_mu),
					.i		(vct_contbus_mu[2])
				) ;

	nt01d3	vctcontbus3nt	(
					.z		(su_cont_to_from[3]),
					.oe		(vct_contbusen_mu),
					.i		(vct_contbus_mu[3])
				) ;


	assign	vct_couprsl_mu[0] =	reset_l && !vct_instvld_mu ;
	assign	vct_couprsl_mu[1] =	reset_l && vct_instvld_mu && vct_multtypop_mu ;
	assign	vct_couprsl_mu[2] =	reset_l && vct_instvld_mu && !vct_multtypop_mu ;


	assign	vct_smuprsl_mu[0] =	reset_l && !vct_instvld_mu ;

	assign	vct_smuprsl_mu[1] =	reset_l && vct_instvld_mu && vct_multtypop_mu ;

	assign	vct_smuprsl_mu[2] =	reset_l && vct_instvld_mu &&
					( vct_stcpop_mu || vct_stmrgop_mu ) ;	/* select or merge op */


	assign	vct_colwrsl_mu[0] =	reset_l && !vct_instvld_mu ;

	assign	vct_colwrsl_mu[1] =	reset_l && vct_instvld_mu && vct_multtypop_mu ;

	assign	vct_colwrsl_mu[2] =	reset_l && vct_instvld_mu && 
					!vct_dvtypop_mu && !vct_multtypop_mu ;


/*
*	We need unique selects for low sum register to handle the case 
*	of VS=0 for VABS instruction.
*/

	wire	[2:0]	vct_prsmlwrsl_mu;	/* selects for multiply lower sum out all vectors */

	assign	vct_prsmlwrsl_mu[0] =	reset_l && !vct_instvld_mu ;

	assign	vct_prsmlwrsl_mu[1] =	reset_l && vct_instvld_mu && vct_multtypop_mu ;

	assign	vct_prsmlwrsl_mu[2] =	reset_l && vct_instvld_mu &&
					( vct_stcpop_mu || vct_stmrgop_mu || vct_dvtypop_mu
					) ;	/* select or merge or divide op */

/*
*	Control signals for the multiplier are decoded in the RD stage and then registered for timing 
*	reasons.
*/

/*
*	Easier to figure out if operand should be unsigned and then complement to produce control signal.
*/
	wire	vct_sgnmplr_rd;			/* signed multiplier */

	assign	vct_sgnmplr_rd =	!( ( su_instfunc_rd == `VMUDL ) || ( su_instfunc_rd == `VMADL ) ||
					  ( su_instfunc_rd == `VMUDN ) || ( su_instfunc_rd == `VMADN )
					) ;

	asdffen #(1, 0)	vctsgnmplrffmu (vct_sgnmplr_mu, vct_sgnmplr_rd, su_instvld_rd, clk, reset_l );

/*
*	Easier to figure out if operand should be unsigned and then complement to produce control signal.
*/
	wire	vct_sgnmplcnd_rd;		/* signed multiplicand */

	assign	vct_sgnmplcnd_rd =	!( ( su_instfunc_rd == `VMUDL ) || ( su_instfunc_rd == `VMADL ) ||
					  ( su_instfunc_rd == `VMUDM ) || ( su_instfunc_rd == `VMADM )
					) ;

	asdffen #(1, 0)	vctsgnmplcndffmu (vct_sgnmplcnd_mu, vct_sgnmplcnd_rd, su_instvld_rd, clk, reset_l );


	wire	vct_shftlftone_rd;		/* shift left by 1 for MULF, MACF, MULU, MACU */

	assign	vct_shftlftone_rd =	( su_instfunc_rd == `VMULF ) || ( su_instfunc_rd == `VMACF ) ||
					( su_instfunc_rd == `VMULU ) || ( su_instfunc_rd == `VMACU ) ;

	asdffen #(1, 0)	vctshftlftoneffmu (vct_shftlftone_mu, vct_shftlftone_rd, su_instvld_rd, clk, reset_l );


/*
*	The next group are output control signals for the
*	accumulate stage of the vector unit datapath.
*/

	wire	[2:0]	vct_prcslwasl_mu;	/* MU stage mux select signals for input a of lower CSA */
	wire	[2:0]	vct_prcslwasl_ac;	/* AC stage mux select signals for input a of lower CSA */

	assign	vct_prcslwasl_mu[0]	=	vct_macfop_mu || vct_macuop_mu ||
						vct_rndpop_mu || vct_rndnop_mu ||
						vct_madlop_mu || vct_madmop_mu || 
						vct_madnop_mu ;

	assign	vct_prcslwasl_mu[1]	=	vct_macqop_mu || vct_madhop_mu ;

	assign	vct_prcslwasl_mu[2]	=	vct_mulfop_mu || vct_muluop_mu ||
						vct_mulqop_mu ;


	asdffen #(3, 0)	vctprcslwaslrgac (vct_prcslwasl_ac, vct_prcslwasl_mu, vct_instvld_mu, clk, reset_l );


/*
*	Unless it is a multiply or round instruction then the above mux produces zero to
*	allow the data from the registers to be passed through the accumulate adder.
*/

	wire	[2:0]	vct_prcslwbsl_mu;	/* MU stage mux select signals for input b of lower CSA */
	wire	[2:0]	vct_prcslwbsl_ac;	/* AC stage mux select signals for input b of lower CSA */

	assign	vct_prcslwbsl_mu[0]	=	!vct_macqop_mu && !vct_rndpop_mu && !vct_rndnop_mu &&
						!vct_absop_mu && !vct_stcpop_mu && !vct_stmrgop_mu &&
						!vct_mudlop_mu && !vct_madlop_mu ;

 	assign	vct_prcslwbsl_mu[1]	=	vct_macqop_mu ;

 	assign	vct_prcslwbsl_mu[2]	=	vct_mudlop_mu || vct_madlop_mu ;


	asdffen #(3, 0)	vctcslwbslrgac (vct_prcslwbsl_ac, vct_prcslwbsl_mu, vct_instvld_mu, clk, reset_l );


	wire	vct_cslwcsl_mu;			/* select for input c of lower csa all vectors */

 	assign	vct_cslwcsl_mu	=	vct_mudlop_mu || vct_madlop_mu ;

	asdffen #(1, 0)	vctcslwcslffac (vct_cslwcsl_ac, vct_cslwcsl_mu, vct_instvld_mu, clk, reset_l );


	wire	[1:0]	vct_prcsupasl_ac;	/* AC stage mux select signals for input a of upper CSA */

	assign	vct_prcsupasl_ac[0]	=	vct_macfop_ac || vct_macuop_ac ||
						vct_rndpop_ac || vct_rndnop_ac ||
						vct_madlop_ac || vct_madmop_ac || 
						vct_madnop_ac ;

	assign	vct_prcsupasl_ac[1]	=	vct_macqop_ac || vct_madhop_ac ;



	wire	[1:0]	vct_prcsupbsl_ac;	/* AC stage mux select signals for input b of upper CSA */

	assign	vct_prcsupbsl_ac[0]	=	vct_multndlop_ac ;

 	assign	vct_prcsupbsl_ac[1]	=	vct_macqop_ac ;


	wire	vct_prcsupcen_ac;	/* pre decoding of input c enable for upper csa all vectors */

	assign	vct_prcsupcen_ac =	!(vct_mudlop_ac || vct_madlop_ac) ;


	wire	[1:0]	vct_praclwsl_ac;	/* selects input for lower mux of accumulator all vectors */

	assign	vct_praclwsl_ac[0] =	vct_sarop_ac || vct_macqop_ac || vct_madhop_ac ;

	assign	vct_praclwsl_ac[1] =	!vct_sarop_ac && !vct_stcpop_ac &&
					!vct_mulqop_ac && !vct_macqop_ac &&  /* zero or hold due to << 16 */
					!vct_mudhop_ac && !vct_madhop_ac ;   /* zero or hold due to << 16 */



	wire	[2:0]	vct_pracmisl_ac;	/* selects input for middle mux of accumulator all vectors */

/*
*	This change was made to prevent the accumulator updating bits 16 to 47
*	on instruction which do not load or accumulate ie. any now multiply 
*	instruction.  This was to allow the upper 32 bits of the accumulator
*	to be used for testin.
*
*	assign	vct_pracmisl_ac[0] =	vct_sarop_ac ;
*/
	assign	vct_pracmisl_ac[0] =	!vct_mulfop_ac && !vct_macfop_ac &&
					!vct_muluop_ac && !vct_macuop_ac &&
					!vct_rndpop_ac && !vct_rndnop_ac &&
					!vct_mulqop_ac && !vct_macqop_ac &&
					!vct_mudlop_ac && !vct_madlop_ac &&
					!vct_mudmop_ac && !vct_madmop_ac &&
					!vct_mudnop_ac && !vct_madnop_ac &&
					!vct_mudhop_ac && !vct_madhop_ac ;


	assign	vct_pracmisl_ac[1] =	( vct_mulfop_ac || vct_macfop_ac ||
					  vct_muluop_ac || vct_macuop_ac ||
					  vct_rndpop_ac || vct_rndnop_ac ||
					  vct_mudlop_ac || vct_madlop_ac ||
					  vct_mudmop_ac || vct_madmop_ac ||
					  vct_mudnop_ac || vct_madnop_ac
					) ;

	assign	vct_pracmisl_ac[2] =	( vct_mulqop_ac || vct_macqop_ac ||
					  vct_mudhop_ac || vct_madhop_ac 
					) ;
	wire	[2:0]	vct_pracupsl_ac;	/* selects input for upper mux of accumulator all vectors */

/*
*	This change was made to prevent the accumulator updating bits 16 to 47
*	on instruction which do not load or accumulate ie. any now multiply 
*	instruction.  This was to allow the upper 32 bits of the accumulator
*	to be used for testin.
*
*	assign	vct_pracupsl_ac[0] =	vct_sarop_ac ;
*/

	assign	vct_pracupsl_ac[0] =	!vct_mulfop_ac && !vct_macfop_ac &&
					!vct_muluop_ac && !vct_macuop_ac &&
					!vct_rndpop_ac && !vct_rndnop_ac &&
					!vct_mulqop_ac && !vct_macqop_ac &&
					!vct_mudlop_ac && !vct_madlop_ac &&
					!vct_mudmop_ac && !vct_madmop_ac &&
					!vct_mudnop_ac && !vct_madnop_ac &&
					!vct_mudhop_ac && !vct_madhop_ac ;

	assign	vct_pracupsl_ac[1] =	( vct_mulfop_ac || vct_muluop_ac ||
					  vct_mudlop_ac || vct_mudmop_ac ||
					  vct_mudnop_ac
					) ;


	assign	vct_pracupsl_ac[2] =	( vct_mulqop_ac || vct_macqop_ac ||
					  vct_mudhop_ac || vct_madhop_ac 
					) ;


/*
*	The next group are output control signals for the
*	write back stage of the vector unit datapath.
*/


	wire	vct_acchighsl_ac;	/* select high portion of accumulator */
	wire	vct_acchighsl_wb;	/* select high portion of accumulator */

	assign	vct_acchighsl_ac =	vct_sarop_ac && ( vct_instelem_ac == 4'h8) ;

	asdffen #(1, 0)	vctacchighslwb (vct_acchighsl_wb, vct_acchighsl_ac, vct_instvld_ac, clk, reset_l );


	wire	vct_accmidsl_ac;	/* select mid portion of accumulator */
	wire	vct_accmidsl_wb;	/* select mid portion of accumulator */

	assign	vct_accmidsl_ac =	( vct_sarop_ac && ( vct_instelem_ac == 4'h9) ) ||
					vct_mulfop_ac || vct_macfop_ac ||
					vct_muluop_ac || vct_macuop_ac ||
					vct_rndpop_ac || vct_rndnop_ac ||
					vct_mudmop_ac || vct_madmop_ac ||
					vct_mudhop_ac || vct_madhop_ac ;

	asdffen #(1, 0)	vctaccmidslwb (vct_accmidsl_wb, vct_accmidsl_ac, vct_instvld_ac, clk, reset_l );



	wire	vct_acclowsl_ac;	/* select low portion of accumulator */
	wire	vct_acclowsl_wb;	/* select low portion of accumulator */

	assign	vct_acclowsl_ac =	( vct_sarop_ac && ( vct_instelem_ac == 4'ha) ) ||
					vct_mudlop_ac || vct_madlop_ac ||
					vct_mudnop_ac || vct_madnop_ac ||
					vct_addtypop_ac || vct_stcpop_ac || 
					vct_logtypop_ac || vct_dvmovop_ac ;

	asdffen #(1, 0)	vctacclowslwb (vct_acclowsl_wb, vct_acclowsl_ac, vct_instvld_ac, clk, reset_l );

/*
*	Note that SAR instruction should be vct_sarop_wb && vct_instelem_wb[0] for
*	reading the low portion of the accumulator but this is covered within the 
*	add instructions.
*/

	wire	vct_accshftsl_ac;	/* select shifted high/mid portion of accumulator */
	wire	vct_accshftsl_wb;	/* select shifted high/mid portion of accumulator */

	assign	vct_accshftsl_ac =	( vct_mulqop_ac || vct_macqop_ac ) ;

	asdffen #(1, 0)	vctaccshftslwb (vct_accshftsl_wb, vct_accshftsl_ac, vct_instvld_ac, clk, reset_l );


	wire	vct_clpsgn16_ac;	/* instruction requiring signed clamping on 15 to 0 */
	wire	vct_clpsgn16_wb;	/* instruction requiring signed clamping on 15 to 0 */

	assign	vct_clpsgn16_ac	=	vct_mudlop_ac || vct_madlop_ac ||
					vct_mudnop_ac || vct_madnop_ac ;

	asdffen #(1, 0)	vctclpsgn16ffwb (vct_clpsgn16_wb, vct_clpsgn16_ac, vct_instvld_ac, clk, reset_l );


	wire	vct_clpsgn31_ac;	/* instruction requiring signed clamping on 31 to MSB */
	wire	vct_clpsgn31_wb;	/* instruction requiring signed clamping on 31 to MSB */

	assign	vct_clpsgn31_ac	=	vct_mulfop_ac || vct_macfop_ac ||
					vct_rndpop_ac || vct_rndnop_ac ||
					vct_mudmop_ac || vct_madmop_ac ||
					vct_mudhop_ac || vct_madhop_ac ;

	asdffen #(1, 0)	vctclpsgn31ffwb (vct_clpsgn31_wb, vct_clpsgn31_ac, vct_instvld_ac, clk, reset_l );


	wire	vct_clpsgn32_ac;	/* instruction requiring signed clamping on 32 to MSB */
	wire	vct_clpsgn32_wb;	/* instruction requiring signed clamping on 32 to MSB */

	assign	vct_clpsgn32_ac	=	vct_mulqop_ac || vct_macqop_ac ;

	asdffen #(1, 0)	vctclpsgn32ffwb (vct_clpsgn32_wb, vct_clpsgn32_ac, vct_instvld_ac, clk, reset_l );


	wire	vct_clpuns31_ac;	/* instruction requiring unsigned clamping on 31 to MSB */
	wire	vct_clpuns31_wb;	/* instruction requiring unsigned clamping on 31 to MSB */

	assign	vct_clpuns31_ac	=	vct_muluop_ac || vct_macuop_ac ;

	asdffen #(1, 0)	vctclpuns31pffwb (vct_clpuns31_wb, vct_clpuns31_ac, vct_instvld_ac, clk, reset_l );


	wire	vct_adscl16op_ac;	/* 16 bit ADD, SUB or ABS instruction in WB */
	wire	vct_adscl16op_wb;	/* 16 bit ADD, SUB or ABS instruction in WB */

	assign	vct_adscl16op_ac	=	vct_addop_ac || vct_subop_ac || vct_absop_ac ;

	asdffen #(1, 0)	vctadscl16fopffwb (vct_adscl16op_wb, vct_adscl16op_ac, vct_instvld_ac, clk, reset_l );

/*
*	Buffers for register file addresses to keep capacitance down for scalar unit.
*/

	wire	[4:0]	su_xp_rnumbuf_rd;	/* buffered register number for xpose stores */

	ni01d5	xp_address_buf0	(
				  .i (su_xp_rnum_rd[0]),	.z (su_xp_rnumbuf_rd[0])
				);

	ni01d5	xp_address_buf1	(
				  .i (su_xp_rnum_rd[1]),	.z (su_xp_rnumbuf_rd[1])
				);

	ni01d5	xp_address_buf2	(
				  .i (su_xp_rnum_rd[2]),	.z (su_xp_rnumbuf_rd[2])
				);

	ni01d5	xp_address_buf3	(
				  .i (su_xp_rnum_rd[3]),	.z (su_xp_rnumbuf_rd[3])
				);

	ni01d5	xp_address_buf4	(
				  .i (su_xp_rnum_rd[4]),	.z (su_xp_rnumbuf_rd[4])
				);


	wire	[4:0]	su_st_rnumbuf_rd;	/* buffered register number for stores */

	ni01d5	st_address_buf0	(
				  .i (su_st_rnum_rd[0]),	.z (su_st_rnumbuf_rd[0])
				);

	ni01d5	st_address_buf1	(
				  .i (su_st_rnum_rd[1]),	.z (su_st_rnumbuf_rd[1])
				);

	ni01d5	st_address_buf2	(
				  .i (su_st_rnum_rd[2]),	.z (su_st_rnumbuf_rd[2])
				);

	ni01d5	st_address_buf3	(
				  .i (su_st_rnum_rd[3]),	.z (su_st_rnumbuf_rd[3])
				);

	ni01d5	st_address_buf4	(
				  .i (su_st_rnum_rd[4]),	.z (su_st_rnumbuf_rd[4])
				);



	wire	[4:0]	su_ld_rnumbuf_ac;	/* buffered register number for load */

	ni01d5	ld_address_buf0	(
				  .i (su_ld_rnum_ac[0]),	.z (su_ld_rnumbuf_ac[0])
				);

	ni01d5	ld_address_buf1	(
				  .i (su_ld_rnum_ac[1]),	.z (su_ld_rnumbuf_ac[1])
				);

	ni01d5	ld_address_buf2	(
				  .i (su_ld_rnum_ac[2]),	.z (su_ld_rnumbuf_ac[2])
				);

	ni01d5	ld_address_buf3	(
				  .i (su_ld_rnum_ac[3]),	.z (su_ld_rnumbuf_ac[3])
				);

	ni01d5	ld_address_buf4	(
				  .i (su_ld_rnum_ac[4]),	.z (su_ld_rnumbuf_ac[4])
				);




vuctlsl	vuctlsl0 (	.clk		(clk),
			.reset_l	(reset_l),
 
			.su_instvld_rd		(su_instvld_rd),
			.vdp_vs_sign_rd		(vdp_vs_sign0_rd),
			.vct_aluprectl_rd	(vct_aluprectl_rd[0]),
			.vct_absop_rd		(vct_absop_rd),

			.vct_instvld_mu		(vct_instvld_mu), 
			.vct_addcop_mu		(vct_addcop_mu),
			.vct_subcop_mu		(vct_subcop_mu),
			.vct_addop_mu		(vct_addop_mu),
			.vct_subop_mu		(vct_subop_mu),
			.vct_vs_sgnmu_mu	(vct_vs_sgnmu_mu),
			.vct_vt_sgnmu_mu	(vct_vt_sgnmu_mu),
			.vct_stltop_mu		(vct_stltop_mu),
			.vct_steqop_mu		(vct_steqop_mu),
			.vct_stneop_mu		(vct_stneop_mu),
			.vct_stgeop_mu		(vct_stgeop_mu),
			.vct_stchop_mu		(vct_stchop_mu),
			.vct_stclop_mu		(vct_stclop_mu),
			.vct_stcrop_mu		(vct_stcrop_mu),
			.vct_stchrop_mu		(vct_stchrop_mu),
			.vct_substclop_mu	(vct_substclop_mu),
			.vct_absop_mu		(vct_absop_mu),

			.vct_rndpop_mu		(vct_rndpop_mu),
			.vct_rndnop_mu		(vct_rndnop_mu),
			.vct_rndop_mu		(vct_rndop_mu),
			.vct_mulqop_mu		(vct_mulqop_mu),
			.vct_mulfop_mu		(vct_mulfop_mu),
			.vct_muluop_mu		(vct_muluop_mu),
			.vct_vseqone_mu		(vct_vseqone_mu),

			.vct_aluprectl_mu	(vct_aluprectl_mu),
			.vct_aluprecin_rd	(vct_aluprecin_rd),
			.vct_cryoutld_mu	(vct_cryoutld_mu),
			.vct_cmpcdld_mu		(vct_cmpcdld_mu),
			.vct_cmpcdadld_mu	(vct_cmpcdadld_mu),
			.vdp_vs_zero_mu		(vdp_vs_zero0_mu),
			.vdp_vt_zero_mu		(vdp_vt_zero0_mu),
			.vdp_vt_sign_mu		(vdp_vt_sign0_mu),

			.vdp_aluovr_mu		(vdp_aluovr0_mu),
			.vdp_aluco_mu		(vdp_aluco0_mu), 
			.vdp_aluzero_mu		(vdp_aluzero0_mu),
			.vdp_aluone_mu		(vdp_aluone0_mu),
			.vct_prsmlwrsl_mu	(vct_prsmlwrsl_mu),

			.vct_instvld_ac		(vct_instvld_ac),
			.vct_prcslwasl_ac	(vct_prcslwasl_ac),
			.vct_prcslwbsl_ac	(vct_prcslwbsl_ac),
			.vct_prcsupasl_ac	(vct_prcsupasl_ac),
			.vct_prcsupbsl_ac	(vct_prcsupbsl_ac),
			.vct_prcsupcen_ac	(vct_prcsupcen_ac),

			.vct_stnclrdop_ac	(vct_stnclrdop_ac),
			.vct_stclrdop_ac	(vct_stclrdop_ac),
			.vct_stchop_ac		(vct_stchop_ac),
			.vct_stclop_ac		(vct_stclop_ac),
			.vct_macqop_ac		(vct_macqop_ac),
			.vct_mudlop_ac		(vct_mudlop_ac),
			.vct_madlop_ac		(vct_madlop_ac),
			.vct_mulfop_ac		(vct_mulfop_ac),
			.vct_muluop_ac		(vct_muluop_ac),
			.vct_rndpop_ac		(vct_rndpop_ac),
			.vct_rndnop_ac		(vct_rndnop_ac), 

			.vct_multtypop_ac	(vct_multtypop_ac),
			.vct_absop_ac		(vct_absop_ac),
			.vct_vseqone_ac		(vct_vseqone_ac),
			.vdp_addlwco_ac		(vdp_addlwco0_ac),
			.vdp_addlwov_ac		(vdp_addlwov0_ac),
			.vdp_csupco_ac		(vdp_csupco0_ac),
			.vdp_addupco_ac		(vdp_addupco0_ac),
			.vmu_co_clal_ac		(vmu_co_clal0_ac),
			.vmu_co_clah_ac		(vmu_co_clah0_ac),
			.vct_praclwsl_ac	(vct_praclwsl_ac),
			.vct_pracmisl_ac	(vct_pracmisl_ac),
			.vct_pracupsl_ac	(vct_pracupsl_ac),
			.vct_multactyp_ac	(vct_multactyp_ac),
			.vct_multincop_ac	(vct_multincop_ac),


			.su_wrcmpcd_wb		(su_wrcmpcd_wb),
			.su_wrcryout_wb		(su_wrcryout_wb),
			.su_wrcmpcdad_wb	(su_wrcmpcdad_wb),
			.su_datainlo_wb		(su_cont_to_from[0]),
			.su_datainhi_wb		(su_cont_to_from[2]),
			.vdp_accbit15_wb	(vdp_acc0bit15_wb),
			.vdp_accbit21_wb	(vdp_acc0bit21_wb), 
			.vdp_accbit31_wb	(vdp_acc0bit31_wb), 
			.vdp_accbit47_wb	(vdp_acc0bit47_wb), 
			.vdp_acchizero_wb	(vdp_achizero0_wb),
			.vdp_accmizero_wb	(vdp_acmizero0_wb),
			.vdp_acchione_wb	(vdp_achione0_wb),
			.vct_acchighsl_wb	(vct_acchighsl_wb),
			.vct_accmidsl_wb	(vct_accmidsl_wb),
			.vct_acclowsl_wb	(vct_acclowsl_wb),
			.vct_accshftsl_wb	(vct_accshftsl_wb),
			.vct_divrsltsl_wb	(vct_divrsltsl_wb),
			.vct_clpsgn31_wb	(vct_clpsgn31_wb),
			.vct_clpsgn16_wb	(vct_clpsgn16_wb),
			.vct_clpsgn32_wb	(vct_clpsgn32_wb),
			.vct_clpuns31_wb	(vct_clpuns31_wb),
			.vct_adscl16op_wb	(vct_adscl16op_wb),

			.vct_aluctl_mu		(vct_aluctl0_mu),
			.vct_alucin_mu		(vct_alucin0_mu), 
			.vct_compvt_mu		(vct_compvt0_mu), 
			.vct_smlwrsl_mu		(vct_smlwrsl0_mu),

			.vct_cryout_ac		(vct_cryout0_ac),
			.vct_opdneql_ac		(vct_opdneql0_ac),
			.vct_cmpcdlo_ac		(vct_cmpcdlo0_ac),
			.vct_cmpcdhi_ac		(vct_cmpcdhi0_ac),
			.vct_cmpcdad_ac		(vct_cmpcdad0_ac),

			.vct_rndvlu_ac		(vct_rndvlu0_ac),
			.vct_cslwasl_ac		(vct_cslwasl0_ac),
			.vct_cslwbsl_ac		(vct_cslwbsl0_ac),
			.vct_addlwci_ac		(vct_addlwci0_ac),
			.vct_csupasl_ac		(vct_csupasl0_ac),
			.vct_csupbsl_ac		(vct_csupbsl0_ac),
			.vct_csupcen_ac		(vct_csupcen0_ac),
			.vct_incrdwn_ac		(vct_incrdwn0_ac),
			.vct_incrci_ac		(vct_incrci0_ac),
			.vct_incrmxsl_ac	(vct_incrmxsl0_ac),
			.vct_aclwsl_ac		(vct_aclwsl0_ac),
			.vct_acmisl_ac		(vct_acmisl0_ac),
			.vct_acupsl_ac		(vct_acupsl0_ac),

			.vct_rsltsl_wb		(vct_rsltsl0_wb),
			.vct_clprslt_wb		(vct_clprslt0_wb),

/*
*	The following signals are for register file address decoding
*	only.
*/

			.su_st_rnum_rd		(su_st_rnumbuf_rd),
			.su_xp_rnum_rd		(su_xp_rnumbuf_rd),
			.su_ld_rnum_ac		(su_ld_rnumbuf_ac),
			.su_vd_addr_wb		(su_vd_addr_wb),
			.su_wbv_wr_en_wb	(su_wbv_wr_en_wb),
			.su_bwe_wb		(su_bwe_wb[3:2]),
			.su_xposeop_rdac	(su_xposeop_rdac),
			.slice			(vct_slice0),
			.wb_div_type		(vct_dvtypop_wb),
			.wb_div_elem		(vct_vs_addr_wb),

			.vct_rfadrt_hi_wb	(vct_rfadrt_hi0_wb),
			.vct_rfadrf_hi_wb	(vct_rfadrf_hi0_wb),
			.vct_rfadrt_lo_wb	(vct_rfadrt_lo0_wb),
			.vct_rfadrf_lo_wb	(vct_rfadrf_lo0_wb),
			.vct_rfadrt_st_rd	(vct_rfadrt_st0_rd),
			.vct_rfadrf_st_rd	(vct_rfadrf_st0_rd),
			.vct_rfadrt_vd_wb	(vct_rfadrt_vd0_wb),
			.vct_rfadrf_vd_wb	(vct_rfadrf_vd0_wb)
		);



vuctlsl	vuctlsl1 (	.clk		(clk),
			.reset_l	(reset_l),
 
			.su_instvld_rd		(su_instvld_rd),
			.vdp_vs_sign_rd		(vdp_vs_sign1_rd),
			.vct_aluprectl_rd	(vct_aluprectl_rd[0]),
			.vct_absop_rd		(vct_absop_rd),

			.vct_instvld_mu		(vct_instvld_mu), 
			.vct_addcop_mu		(vct_addcop_mu),
			.vct_subcop_mu		(vct_subcop_mu),
			.vct_addop_mu		(vct_addop_mu),
			.vct_subop_mu		(vct_subop_mu),
			.vct_vs_sgnmu_mu	(vct_vs_sgnmu_mu),
			.vct_vt_sgnmu_mu	(vct_vt_sgnmu_mu),
			.vct_stltop_mu		(vct_stltop_mu),
			.vct_steqop_mu		(vct_steqop_mu),
			.vct_stneop_mu		(vct_stneop_mu),
			.vct_stgeop_mu		(vct_stgeop_mu),
			.vct_stchop_mu		(vct_stchop_mu),
			.vct_stclop_mu		(vct_stclop_mu),
			.vct_stcrop_mu		(vct_stcrop_mu),
			.vct_stchrop_mu		(vct_stchrop_mu),
			.vct_substclop_mu	(vct_substclop_mu),
			.vct_absop_mu		(vct_absop_mu),

			.vct_rndpop_mu		(vct_rndpop_mu),
			.vct_rndnop_mu		(vct_rndnop_mu),
			.vct_rndop_mu		(vct_rndop_mu),
			.vct_mulqop_mu		(vct_mulqop_mu),
			.vct_mulfop_mu		(vct_mulfop_mu),
			.vct_muluop_mu		(vct_muluop_mu),
			.vct_vseqone_mu		(vct_vseqone_mu),

			.vct_aluprectl_mu	(vct_aluprectl_mu),
			.vct_aluprecin_rd	(vct_aluprecin_rd),
			.vct_cryoutld_mu	(vct_cryoutld_mu),
			.vct_cmpcdld_mu		(vct_cmpcdld_mu),
			.vct_cmpcdadld_mu	(vct_cmpcdadld_mu),
			.vdp_vs_zero_mu		(vdp_vs_zero1_mu),
			.vdp_vt_zero_mu		(vdp_vt_zero1_mu),
			.vdp_vt_sign_mu		(vdp_vt_sign1_mu),

			.vdp_aluovr_mu		(vdp_aluovr1_mu),
			.vdp_aluco_mu		(vdp_aluco1_mu), 
			.vdp_aluzero_mu		(vdp_aluzero1_mu),
			.vdp_aluone_mu		(vdp_aluone1_mu),
			.vct_prsmlwrsl_mu	(vct_prsmlwrsl_mu),


			.vct_instvld_ac		(vct_instvld_ac),
			.vct_prcslwasl_ac	(vct_prcslwasl_ac),
			.vct_prcslwbsl_ac	(vct_prcslwbsl_ac),
			.vct_prcsupasl_ac	(vct_prcsupasl_ac),
			.vct_prcsupbsl_ac	(vct_prcsupbsl_ac),
			.vct_prcsupcen_ac	(vct_prcsupcen_ac),

			.vct_stnclrdop_ac	(vct_stnclrdop_ac),
			.vct_stclrdop_ac	(vct_stclrdop_ac),
			.vct_stchop_ac		(vct_stchop_ac),
			.vct_stclop_ac		(vct_stclop_ac),
			.vct_macqop_ac		(vct_macqop_ac),
			.vct_mudlop_ac		(vct_mudlop_ac),
			.vct_madlop_ac		(vct_madlop_ac),
			.vct_mulfop_ac		(vct_mulfop_ac),
			.vct_muluop_ac		(vct_muluop_ac),
			.vct_rndpop_ac		(vct_rndpop_ac),
			.vct_rndnop_ac		(vct_rndnop_ac), 
			.vct_multtypop_ac	(vct_multtypop_ac),
			.vct_absop_ac		(vct_absop_ac),
			.vct_vseqone_ac		(vct_vseqone_ac),
			.vdp_addlwco_ac		(vdp_addlwco1_ac),
			.vdp_addlwov_ac		(vdp_addlwov1_ac),
			.vdp_csupco_ac		(vdp_csupco1_ac),
			.vdp_addupco_ac		(vdp_addupco1_ac),
			.vmu_co_clal_ac		(vmu_co_clal1_ac),
			.vmu_co_clah_ac		(vmu_co_clah1_ac),
			.vct_praclwsl_ac	(vct_praclwsl_ac),
			.vct_pracmisl_ac	(vct_pracmisl_ac),
			.vct_pracupsl_ac	(vct_pracupsl_ac),
			.vct_multactyp_ac	(vct_multactyp_ac),
			.vct_multincop_ac	(vct_multincop_ac),

			.su_wrcmpcd_wb		(su_wrcmpcd_wb),
			.su_wrcryout_wb		(su_wrcryout_wb),
			.su_wrcmpcdad_wb	(su_wrcmpcdad_wb),
			.su_datainlo_wb		(su_cont_to_from[1]),
			.su_datainhi_wb		(su_cont_to_from[3]),
			.vdp_accbit15_wb	(vdp_acc1bit15_wb),
			.vdp_accbit21_wb	(vdp_acc1bit21_wb), 
			.vdp_accbit31_wb	(vdp_acc1bit31_wb), 
			.vdp_accbit47_wb	(vdp_acc1bit47_wb), 
			.vdp_acchizero_wb	(vdp_achizero1_wb),
			.vdp_accmizero_wb	(vdp_acmizero1_wb),
			.vdp_acchione_wb	(vdp_achione1_wb),
			.vct_acchighsl_wb	(vct_acchighsl_wb),
			.vct_accmidsl_wb	(vct_accmidsl_wb),
			.vct_acclowsl_wb	(vct_acclowsl_wb),
			.vct_accshftsl_wb	(vct_accshftsl_wb),
			.vct_divrsltsl_wb	(vct_divrsltsl_wb),
			.vct_clpsgn31_wb	(vct_clpsgn31_wb),
			.vct_clpsgn16_wb	(vct_clpsgn16_wb),
			.vct_clpsgn32_wb	(vct_clpsgn32_wb),
			.vct_clpuns31_wb	(vct_clpuns31_wb),
			.vct_adscl16op_wb	(vct_adscl16op_wb),

			.vct_aluctl_mu		(vct_aluctl1_mu),
			.vct_alucin_mu		(vct_alucin1_mu), 
			.vct_compvt_mu		(vct_compvt1_mu), 
			.vct_smlwrsl_mu		(vct_smlwrsl1_mu),

			.vct_cryout_ac		(vct_cryout1_ac),
			.vct_opdneql_ac		(vct_opdneql1_ac),
			.vct_cmpcdlo_ac		(vct_cmpcdlo1_ac),
			.vct_cmpcdhi_ac		(vct_cmpcdhi1_ac),
			.vct_cmpcdad_ac		(vct_cmpcdad1_ac),

			.vct_rndvlu_ac		(vct_rndvlu1_ac),
			.vct_cslwasl_ac		(vct_cslwasl1_ac),
			.vct_cslwbsl_ac		(vct_cslwbsl1_ac),
			.vct_addlwci_ac		(vct_addlwci1_ac),
			.vct_csupasl_ac		(vct_csupasl1_ac),
			.vct_csupbsl_ac		(vct_csupbsl1_ac),
			.vct_csupcen_ac		(vct_csupcen1_ac),
			.vct_incrdwn_ac		(vct_incrdwn1_ac),
			.vct_incrci_ac		(vct_incrci1_ac),
			.vct_incrmxsl_ac	(vct_incrmxsl1_ac),
			.vct_aclwsl_ac		(vct_aclwsl1_ac),
			.vct_acmisl_ac		(vct_acmisl1_ac),
			.vct_acupsl_ac		(vct_acupsl1_ac),

			.vct_rsltsl_wb		(vct_rsltsl1_wb),
			.vct_clprslt_wb		(vct_clprslt1_wb),

/*
*	The following signals are for register file address decoding
*	only.
*/
			.su_st_rnum_rd		(su_st_rnumbuf_rd),
			.su_xp_rnum_rd		(su_xp_rnumbuf_rd),
			.su_ld_rnum_ac		(su_ld_rnumbuf_ac),
			.su_vd_addr_wb		(su_vd_addr_wb),
			.su_wbv_wr_en_wb	(su_wbv_wr_en_wb),
			.su_bwe_wb		(su_bwe_wb[1:0]),
			.su_xposeop_rdac	(su_xposeop_rdac),
			.slice			(vct_slice1),
			.wb_div_type		(vct_dvtypop_wb),
			.wb_div_elem		(vct_vs_addr_wb),

			.vct_rfadrt_hi_wb	(vct_rfadrt_hi1_wb),
			.vct_rfadrf_hi_wb	(vct_rfadrf_hi1_wb),
			.vct_rfadrt_lo_wb	(vct_rfadrt_lo1_wb),
			.vct_rfadrf_lo_wb	(vct_rfadrf_lo1_wb),
			.vct_rfadrt_st_rd	(vct_rfadrt_st1_rd),
			.vct_rfadrf_st_rd	(vct_rfadrf_st1_rd),
			.vct_rfadrt_vd_wb	(vct_rfadrt_vd1_wb),
			.vct_rfadrf_vd_wb	(vct_rfadrf_vd1_wb)
		);



endmodule


/*
*	32 bit non-inverting buffer module for register file VT address.
*/

module	buffer_ninv (	vt_addr_in, vt_addr_out ) ;

	input [31:0]	vt_addr_in ;
	output [31:0]	vt_addr_out ;


	ni01d5	bit_0	( .z(vt_addr_out[0]) , .i (vt_addr_in[0]) ) ;
	ni01d5	bit_1	( .z(vt_addr_out[1]) , .i (vt_addr_in[1]) ) ;
	ni01d5	bit_2	( .z(vt_addr_out[2]) , .i (vt_addr_in[2]) ) ;
	ni01d5	bit_3	( .z(vt_addr_out[3]) , .i (vt_addr_in[3]) ) ;
	ni01d5	bit_4	( .z(vt_addr_out[4]) , .i (vt_addr_in[4]) ) ;
	ni01d5	bit_5	( .z(vt_addr_out[5]) , .i (vt_addr_in[5]) ) ;
	ni01d5	bit_6	( .z(vt_addr_out[6]) , .i (vt_addr_in[6]) ) ;
	ni01d5	bit_7	( .z(vt_addr_out[7]) , .i (vt_addr_in[7]) ) ;
	ni01d5	bit_8	( .z(vt_addr_out[8]) , .i (vt_addr_in[8]) ) ;
	ni01d5	bit_9	( .z(vt_addr_out[9]) , .i (vt_addr_in[9]) ) ;

	ni01d5	bit_10	( .z(vt_addr_out[10]) , .i (vt_addr_in[10]) ) ;
	ni01d5	bit_11	( .z(vt_addr_out[11]) , .i (vt_addr_in[11]) ) ;
	ni01d5	bit_12	( .z(vt_addr_out[12]) , .i (vt_addr_in[12]) ) ;
	ni01d5	bit_13	( .z(vt_addr_out[13]) , .i (vt_addr_in[13]) ) ;
	ni01d5	bit_14	( .z(vt_addr_out[14]) , .i (vt_addr_in[14]) ) ;
	ni01d5	bit_15	( .z(vt_addr_out[15]) , .i (vt_addr_in[15]) ) ;
	ni01d5	bit_16	( .z(vt_addr_out[16]) , .i (vt_addr_in[16]) ) ;
	ni01d5	bit_17	( .z(vt_addr_out[17]) , .i (vt_addr_in[17]) ) ;
	ni01d5	bit_18	( .z(vt_addr_out[18]) , .i (vt_addr_in[18]) ) ;
	ni01d5	bit_19	( .z(vt_addr_out[19]) , .i (vt_addr_in[19]) ) ;

	ni01d5	bit_20	( .z(vt_addr_out[20]) , .i (vt_addr_in[20]) ) ;
	ni01d5	bit_21	( .z(vt_addr_out[21]) , .i (vt_addr_in[21]) ) ;
	ni01d5	bit_22	( .z(vt_addr_out[22]) , .i (vt_addr_in[22]) ) ;
	ni01d5	bit_23	( .z(vt_addr_out[23]) , .i (vt_addr_in[23]) ) ;
	ni01d5	bit_24	( .z(vt_addr_out[24]) , .i (vt_addr_in[24]) ) ;
	ni01d5	bit_25	( .z(vt_addr_out[25]) , .i (vt_addr_in[25]) ) ;
	ni01d5	bit_26	( .z(vt_addr_out[26]) , .i (vt_addr_in[26]) ) ;
	ni01d5	bit_27	( .z(vt_addr_out[27]) , .i (vt_addr_in[27]) ) ;
	ni01d5	bit_28	( .z(vt_addr_out[28]) , .i (vt_addr_in[28]) ) ;
	ni01d5	bit_29	( .z(vt_addr_out[29]) , .i (vt_addr_in[29]) ) ;

	ni01d5	bit_30	( .z(vt_addr_out[30]) , .i (vt_addr_in[30]) ) ;
	ni01d5	bit_31	( .z(vt_addr_out[31]) , .i (vt_addr_in[31]) ) ;

endmodule



/*
*	32 bit inverting buffer module for register file VT address.
*/

module	buffer_inv (	vt_addr_in, vt_addr_out_inv ) ;

	input [31:0]	vt_addr_in ;
	output [31:0]	vt_addr_out_inv ;


	in01d5	bit_0	( .zn(vt_addr_out_inv[0]) , .i (vt_addr_in[0]) ) ;
	in01d5	bit_1	( .zn(vt_addr_out_inv[1]) , .i (vt_addr_in[1]) ) ;
	in01d5	bit_2	( .zn(vt_addr_out_inv[2]) , .i (vt_addr_in[2]) ) ;
	in01d5	bit_3	( .zn(vt_addr_out_inv[3]) , .i (vt_addr_in[3]) ) ;
	in01d5	bit_4	( .zn(vt_addr_out_inv[4]) , .i (vt_addr_in[4]) ) ;
	in01d5	bit_5	( .zn(vt_addr_out_inv[5]) , .i (vt_addr_in[5]) ) ;
	in01d5	bit_6	( .zn(vt_addr_out_inv[6]) , .i (vt_addr_in[6]) ) ;
	in01d5	bit_7	( .zn(vt_addr_out_inv[7]) , .i (vt_addr_in[7]) ) ;
	in01d5	bit_8	( .zn(vt_addr_out_inv[8]) , .i (vt_addr_in[8]) ) ;
	in01d5	bit_9	( .zn(vt_addr_out_inv[9]) , .i (vt_addr_in[9]) ) ;

	in01d5	bit_10	( .zn(vt_addr_out_inv[10]) , .i (vt_addr_in[10]) ) ;
	in01d5	bit_11	( .zn(vt_addr_out_inv[11]) , .i (vt_addr_in[11]) ) ;
	in01d5	bit_12	( .zn(vt_addr_out_inv[12]) , .i (vt_addr_in[12]) ) ;
	in01d5	bit_13	( .zn(vt_addr_out_inv[13]) , .i (vt_addr_in[13]) ) ;
	in01d5	bit_14	( .zn(vt_addr_out_inv[14]) , .i (vt_addr_in[14]) ) ;
	in01d5	bit_15	( .zn(vt_addr_out_inv[15]) , .i (vt_addr_in[15]) ) ;
	in01d5	bit_16	( .zn(vt_addr_out_inv[16]) , .i (vt_addr_in[16]) ) ;
	in01d5	bit_17	( .zn(vt_addr_out_inv[17]) , .i (vt_addr_in[17]) ) ;
	in01d5	bit_18	( .zn(vt_addr_out_inv[18]) , .i (vt_addr_in[18]) ) ;
	in01d5	bit_19	( .zn(vt_addr_out_inv[19]) , .i (vt_addr_in[19]) ) ;

	in01d5	bit_20	( .zn(vt_addr_out_inv[20]) , .i (vt_addr_in[20]) ) ;
	in01d5	bit_21	( .zn(vt_addr_out_inv[21]) , .i (vt_addr_in[21]) ) ;
	in01d5	bit_22	( .zn(vt_addr_out_inv[22]) , .i (vt_addr_in[22]) ) ;
	in01d5	bit_23	( .zn(vt_addr_out_inv[23]) , .i (vt_addr_in[23]) ) ;
	in01d5	bit_24	( .zn(vt_addr_out_inv[24]) , .i (vt_addr_in[24]) ) ;
	in01d5	bit_25	( .zn(vt_addr_out_inv[25]) , .i (vt_addr_in[25]) ) ;
	in01d5	bit_26	( .zn(vt_addr_out_inv[26]) , .i (vt_addr_in[26]) ) ;
	in01d5	bit_27	( .zn(vt_addr_out_inv[27]) , .i (vt_addr_in[27]) ) ;
	in01d5	bit_28	( .zn(vt_addr_out_inv[28]) , .i (vt_addr_in[28]) ) ;
	in01d5	bit_29	( .zn(vt_addr_out_inv[29]) , .i (vt_addr_in[29]) ) ;

	in01d5	bit_30	( .zn(vt_addr_out_inv[30]) , .i (vt_addr_in[30]) ) ;
	in01d5	bit_31	( .zn(vt_addr_out_inv[31]) , .i (vt_addr_in[31]) ) ;

endmodule