/*
*************************************************************************
*									*
*               Copyright (C) 1994, Silicon Graphics, Inc.		*
*									*
*  These coded instructions, statements, and computer programs  contain	*
*  unpublished  proprietary  information of Silicon Graphics, Inc., and	*
*  are protected by Federal copyright  law.  They  may not be disclosed	*
*  to  third  parties  or copied or duplicated in any form, in whole or	*
*  in part, without the prior written consent of Silicon Graphics, Inc.	*
*									*
*************************************************************************
*/

// $Id: vusl.v,v 1.1.1.1 2002/05/17 06:07:49 blythe Exp $

/*
*************************************************************************
*									*
*	Project Reality							*
*									*
*	Module:		vusl						*
*	Description:	Vector unit slice which incorporates two vector	* 
*			unit datapaths, two multipliers and one 	*
*			control unit.  This partitioning was decided	*
*			upon for physical partitioning.			*
*									*
*	Designer:	Brian Ferguson					*
*	Date:		10/13/94					*
*									*
*************************************************************************
*/

// vu.v: 	RSP vector unit top level - instantiation of datapath and control

`timescale 1ns / 10ps

module	vusl (	clk, reset_l, 
		su_instvld_rd, su_storeinst_rd, su_storecfc2_rd, 
		su_vseqone_rd, su_instelem_rd, su_instfunc_rd, 
		su_rdcmpcd_rd, su_rdcryout_rd, su_rdcmpcdad_rd,
		su_wrcmpcd_wb, su_wrcryout_wb, su_wrcmpcdad_wb,

		su_st_rnum_rd,
		su_xp_rnum_rd,
		su_ld_rnum_ac,
		su_vs_addr_rd,
		su_vt_addr_rd,
		su_vd_addr_ac,
		su_wbv_wr_en_ac,
		su_bwe_ac,
		su_xposeop_rdac,
		vct_slice0,
		vct_slice1,

		vdi_divrslt0_wb,
		vdi_divrslt1_wb,

		vdp_hlfin0_rd,
		vdp_hlfin1_rd,

		vdp_whlin0_rd,
		vdp_whlin1_rd,

		vct_hlfsl0_rd,
		vct_hlfsl1_rd,

		vct_whlsl0_rd,
		vct_whlsl1_rd,

		vdp_datatristen0_mu,
		vdp_datatristen1_mu,


		vct_hlflosl_rd,
		vct_hlfhisl_rd,
		vct_whllosl_rd,
		vct_whlhisl_rd,

		vdp_hlfout0_rd,
		vdp_hlfout1_rd,

		vdp_whlout0_rd,
		vdp_whlout1_rd,

		su_storeinst_mu, 
		su_storecfc2_mu,

		su_data_to_from,
		su_cont_to_from

	   ) ;


	input	clk;				/* vu clock */
	input	reset_l;			/* vu active low reset */

	input	su_instvld_rd;			/* valid CP2 instruction for vu */
	input	su_storeinst_rd;		/* store from VU */
	input	su_storecfc2_rd;		/* store or move control from VU */
	input	su_vseqone_rd;			/* vs field of instruction equal to 1 */
	input   [3:0] su_instelem_rd;		/* element field of instruction */
	input   [5:0] su_instfunc_rd;		/* function field of instruction */

	input	su_rdcmpcd_rd;			/* read vector compare code register */
	input	su_rdcryout_rd;			/* read vector carry out register */
	input	su_rdcmpcdad_rd;		/* read vector compare add register */

	input	su_wrcmpcd_wb;			/* write vector compare code register */
	input	su_wrcryout_wb;			/* write vector carry out register */
	input	su_wrcmpcdad_wb;		/* write vector compare add register */

/*
*	The following input signals are for register file address decoding
*	only.
*/

	input	[4:0]	su_st_rnum_rd;		/* register number for stores */
	input	[4:0]	su_xp_rnum_rd;		/* register number for xpose stores */
	input	[4:0]	su_ld_rnum_ac;		/* register number for load */
	input	[4:0]	su_vs_addr_rd;		/* register number for vs read */
	input	[31:0]	su_vt_addr_rd;		/* decoded register number for vt read */
	input	[4:0]	su_vd_addr_ac;		/* register number for datapath writeback */
	input		su_wbv_wr_en_ac;	/* write enable for datapath results */
	input	[3:0]	su_bwe_ac;		/* load port byte write enable */
	input		su_xposeop_rdac;	/* transpose op in rd (store) or ac (load) */
	input	[2:0]	vct_slice0;		/* slice number of register file decode use */
	input	[2:0]	vct_slice1;		/* slice number of register file decode use */

	input	[15:0]	vdi_divrslt0_wb;	/* result from divide unit to even datapath */
	input	[15:0]	vdi_divrslt1_wb;	/* result from divide unit to odd datapath */

	input	[15:0]	vdp_hlfin0_rd;		/* data from other datapaths for dp even scalar half  */
	input	[15:0]	vdp_hlfin1_rd;		/* data from other datapaths for dp odd scalar half */

	input	[15:0]	vdp_whlin0_rd;		/* data from other datapaths for dp even scalar whole */
	input	[15:0]	vdp_whlin1_rd;		/* data from other datapaths for dp odd scalar whole */

	input	vct_hlfsl0_rd;			/* select VT scalar value for 2nd mux in dp 0 */
	input	vct_hlfsl1_rd;			/* select VT scalar value for 2nd mux in dp 1 */

	input	[2:0]	vct_whlsl0_rd;		/* select VT scalar value for 3rd mux in dp 0 */
	input	[2:0]	vct_whlsl1_rd;		/* select VT scalar value for 3rd mux in dp 1 */

	input	vdp_datatristen0_mu;		/* tristate enable for load/store data bus element 0 */
	input	vdp_datatristen1_mu;		/* tristate enable for load/store data bus element 1 */

	output	vct_hlflosl_rd;			/* select VT scalar value from 0,1,4,5 vectors */
	output	[2:0]	vct_whllosl_rd;		/* select VT scalar value from 0,1,2,3 vectors */
	output	vct_hlfhisl_rd;			/* select VT scalar value from 2,3,6,7 vectors */
	output	[2:0]	vct_whlhisl_rd;		/* select VT scalar value from 4,5,6,7 vectors */

	output	[15:0]	vdp_hlfout0_rd;		/* data from other datapaths for even dp scalar half */
	output	[15:0]	vdp_hlfout1_rd;		/* data from other datapaths for odd dp scalar half */

	output	[15:0]	vdp_whlout0_rd;		/* data from other datapaths for even dp scalar whole */
	output	[15:0]	vdp_whlout1_rd;		/* data from other datapaths for odd dp scalar whole */

	output	su_storeinst_mu;		/* store from VU */
	output	su_storecfc2_mu;		/* store or move control from VU */

	inout	[31:0]	su_data_to_from;	/* data field to/from vu */
	inout	[3:0]	su_cont_to_from;	/* data for control register moves */
	
/*
*	The following signals are the input signals to the 
*	vector unit control block.
*
*	The first group are input signals to the control block 
*	which provide general control such as clocks, reset
*	hold and instruction decoding.
*
*/

/*
*	The next group are input signals to the control block from
*	the register file read stage of the vector unit datapaths.
*/
	wire	vdp_vs_sign0_rd;	/* vs sign bit from vector 0 */
	wire	vdp_vs_sign1_rd;	/* vs sign bit from vector 1 */

/*
*	The next group of signals are outputs from the RD stage of the
*	datapath which drive data to other datapaths in the case of 
*	passing scalar data to other datapaths.
*/

	wire	[15:0]	vdp_opndt0_rd;	/* vt data from rf in RD stage in vector 0 */
	wire	[15:0]	vdp_opndt1_rd;	/* vt data from rf in RD stage in vector 1 */

/*
*	The next group are input signals to the control block from
*	the multiply stage of the vector unit datapaths.
*/

	wire	vdp_vt_sign0_mu;	/* vt sign bit from vector 0 */
	wire	vdp_vt_sign1_mu;	/* vt sign bit from vector 1 */

	wire	vdp_aluovr0_mu;		/* overflow bit from alu vector 0 */
	wire	vdp_aluco0_mu;		/* carry out from alu vector 0 */
	wire	vdp_vs_zero0_mu;	/* vs operand is equal to zero vector 0 */
	wire	vdp_vt_zero0_mu;	/* vt operand is equal to zero vector 0 */
	wire	vdp_aluzero0_mu;	/* alu result is equal to zero vector 0 */
	wire	vdp_aluone0_mu;		/* alu result is equal to all ones vector 0 */

	wire	vdp_aluovr1_mu;		/* overflow bit from alu vector 1 */
	wire	vdp_aluco1_mu;		/* carry out from alu vector 1 */
	wire	vdp_vs_zero1_mu;	/* vs operand is equal to zero vector 1 */
	wire	vdp_vt_zero1_mu;	/* vt operand is equal to zero vector 1 */
	wire	vdp_aluzero1_mu;	/* alu result operand s is equal to zero vector 1 */
	wire	vdp_aluone1_mu;		/* alu result is equal to all ones vector 1 */



/*
*	The next group are input signals to the control block from
*	the accumulate stage of the vector unit datapaths.
*/

	wire	vdp_cslwco0_ac;		/* carry out from low csa vector 0 */
	wire	vdp_addlwco0_ac;	/* carry out from low adder vector 0 */
	wire	vdp_addlwov0_ac;	/* overflow from low csa vector 0 */
	wire	vdp_csupco0_ac;		/* carry out from high csa vector 0 */
	wire	vdp_addupco0_ac;	/* carry out from high adder vector 0 */
	wire	vdp_addupov0_ac;	/* overflow from high csa vector 0 */
	wire	vdp_incrco0_ac;		/* carry out from incrementer vector 0 */

	wire	vdp_cslwco1_ac;		/* carry out from low csa vector 1 */
	wire	vdp_addlwco1_ac;	/* carry out from low adder vector 1 */
	wire	vdp_addlwov1_ac;	/* overflow from low csa vector 1 */
	wire	vdp_csupco1_ac;		/* carry out from high csa vector 1 */
	wire	vdp_addupco1_ac;	/* carry out from high adder vector 1 */
	wire	vdp_addupov1_ac;	/* overflow from high csa vector 1 */
	wire	vdp_incrco1_ac;		/* carry out from incrementer vector 1 */

	wire	vmu_co_clal0_ac;	/* carry out from 16 bit product of multiplier vector 0 */
	wire	vmu_co_clal1_ac;	/* carry out from 16 bit product of multiplier vector 1 */
	wire	vmu_co_clah0_ac;	/* false carry out from multiplier vector 0 */
	wire	vmu_co_clah1_ac;	/* false carry out from multiplier vector 1 */

/*
*	The next group are input signals to the control block from
*	the writeback stage of the vector unit datapaths.
*/


	wire	vdp_acc0bit15_wb;	/* bit 15 of accumulator used to determine sign vector 0 */
	wire	vdp_acc0bit21_wb;	/* bit 21 of accumulator used for macq vector 0 */
	wire	vdp_acc0bit31_wb;	/* bit 31 of accumulator used to determine sign vector 0 */
	wire	vdp_acc0bit47_wb;	/* bit 47 of accumulator used to determine sign vector 0 */

	wire	vdp_achizero0_wb;	/* 47:32 of accumulator equal zero vector 0 */
	wire	vdp_acmizero0_wb;	/* 31:16 of accumulator equal zero vector 0 */
	wire	vdp_achione0_wb;	/* 47:32 of accumulator equal one vector 0 */


	wire	vdp_acc1bit15_wb;	/* bit 15 of accumulator used to determine sign vector 1*/
	wire	vdp_acc1bit21_wb;	/* bit 21 of accumulator used for macq vector 1 */
	wire	vdp_acc1bit31_wb;	/* bit 31 of accumulator used to determine sign vector 1 */
	wire	vdp_acc1bit47_wb;	/* bit 47 of accumulator used to determine sign vector 1 */

	wire	vdp_achizero1_wb;	/* 47:32 of accumulator equal zero vector 1 */
	wire	vdp_acmizero1_wb;	/* 31:16 of accumulator equal zero vector 1 */
	wire	vdp_achione1_wb;	/* 47:32 of accumulator equal one vector 1 */


/*
*	The following signals are the output signals for the 
*	vector unit control block.
*
*	The first group are output control signals for the
*	register file read stage of the vector unit datapath.
*/

	wire	[2:0]	vct_regopssl_rd;	/* select signal ofr VS register in RF stage */

	wire	vct_qurtlosl_rd;		/* select VT scalar value from even vectors */

	wire	vct_qurthisl_rd;		/* select VT scalar value from odd vectors */


/*
*	The next group are output control signals for the
*	multiply stage of the vector unit datapath.
*/

	wire	[2:0]	vct_couprsl_mu;		/* selects for multiply upper carry out all vectors */
	wire	[2:0]	vct_smuprsl_mu;		/* selects for multiply upper sum out all vectors */

	wire	[2:0]	vct_colwrsl_mu;		/* selects for multiply lower carry out register all vectors */
	wire	[2:0]	vct_smlwrsl0_mu;	/* selects for multiply lower sum out vector 0 */
	wire	[2:0]	vct_smlwrsl1_mu;	/* selects for multiply lower sum out vector 1 */

	wire	[4:0]	vct_aluctl0_mu;		/* control for alu vector 0 */
	wire	vct_alucin0_mu;			/* carry in to alu vector 0 */

	wire	[4:0]	vct_aluctl1_mu;		/* control for alu vector 1 */
	wire	vct_alucin1_mu;			/* carry in to alu vector 1 */


/*
*	The next group of signals are inputs to the MU stage of the
*	datapath from the multiplier block which was done as a seperate module.
*/

	wire	[15:0]	vmu_sumlower0_mu;	/* lower sum vector for multiplier to datapath element 0 */
	wire	[15:0]	vmu_carrylower0_mu;	/* lower carry vector for multiplier to datapath element 0 */
	wire	[15:0]	vmu_sumupper0_mu;	/* upper sum vector for multiplier to datapath element 0 */
	wire	[15:0]	vmu_carryupper0_mu;	/* upper carry vector for multiplier to datapath element 0 */

	wire	[15:0]	vmu_sumlower1_mu;	/* lower sum vector for multiplier to datapath element 1 */
	wire	[15:0]	vmu_carrylower1_mu;	/* lower carry vector for multiplier to datapath element 1 */
	wire	[15:0]	vmu_sumupper1_mu;	/* upper sum vector for multiplier to datapath element 1 */
	wire	[15:0]	vmu_carryupper1_mu;	/* upper carry vector for multiplier to datapath element 1 */


/*
*	The next group of signals are outputs from the vu control block
*	control the multiplier block which was done as a seperate module.
*/

	wire		vct_sgnmplcnd_mu;	/* multiplicand is signed */
	wire		vct_sgnmplr_mu;		/* multiplier is signed */
	wire		vct_shftlftone_mu;	/* shift multiply product left by one */


/*
*	The next group of signals are outputs from the MU stage of the
*	datapath which drive data to the multiplier block which was 
*	done as a seperate module.
*/

	wire	[15:0]	vdp_mplcnd0_mu;	/* multiplicand from datapath in vector 0 */
	wire	[15:0]	vdp_mplr0_mu;	/* multiplier from datapath in vector 0 */

	wire	[15:0]	vdp_mplcnd1_mu;	/* multiplicand from datapath in vector 1 */
	wire	[15:0]	vdp_mplr1_mu;	/* multiplier from datapath in vector 1 */


/*
*	The next group are output control signals for the
*	accumulate stage of the vector unit datapath.
*/

	wire	[2:0]	vct_aclwsl0_ac;		/* selects input for lower mux of accumulator vector 0 */
	wire	[2:0]	vct_aclwsl1_ac;		/* selects input for lower mux of accumulator vector 1 */

	wire	vct_cslwcsl_ac;			/* select for input c of lower csa all vectors */
	wire	vct_csupcen_ac;			/* input c enable for upper csa all vectors */


	wire	[2:0]	vct_acmisl0_ac;		/* selects for middle mux of accumulator vector 0 */
	wire	[2:0]	vct_acmisl1_ac;		/* selects for middle mux of accumulator vector 1 */

	wire	[2:0]	vct_acupsl0_ac;		/* selects input for upper mux of accumulator vector 0 */
	wire	[2:0]	vct_acupsl1_ac;		/* selects input for upper mux of accumulator vector 1 */

	wire	[3:0]	vct_rndvlu0_ac;	/* round value for multiplies/byte adds vector 0 */
	wire	[2:0]	vct_cslwasl0_ac;	/* selects for input a of lower csa vector 0 */
	wire	[2:0]	vct_cslwbsl0_ac;	/* selects for input b of lower csa vector 0 */
	wire	vdp_csalwci0_ac;		/* carry in to lower csa vector 0 */
	wire	vct_addlwci0_ac;		/* carry in to lower adder vector 0 */
	wire	[1:0]	vct_csupasl0_ac;	/* selects for input a of upper csa vector 0 */
	wire	[1:0]	vct_csupbsl0_ac;	/* selects for input b of upper csa vector 0 */
	wire	vct_csupcen0_ac;		/* input c enable for upper csa even vectors */
	wire	vdp_csaupci0_ac;		/* carry in to upper csa vector 0 */
	wire	vdp_addupci0_ac;		/* carry in to upper adder vector 0 */
	wire	vct_incrdwn0_ac;		/* increment/decrement control signal vector 0 */
	wire	vct_incrci0_ac;			/* increment/decrement enable signal vector 0 */
	wire	[1:0]	vct_incrmxsl0_ac;	/* mux selects for incrementer output vector 0 */

	wire	[3:0]	vct_rndvlu1_ac;	/* round value for multiplies/byte adds vector 1 */
	wire	[2:0]	vct_cslwasl1_ac;	/* selects for input a of lower csa vector 1 */
	wire	[2:0]	vct_cslwbsl1_ac;	/* selects for input b of lower csa vector 1 */
	wire	vdp_csalwci1_ac;		/* carry in to lower csa vector 1 */
	wire	vct_addlwci1_ac;		/* carry in to lower adder vector 1 */
	wire	[1:0]	vct_csupasl1_ac;	/* selects for input a of upper csa vector 1 */
	wire	[1:0]	vct_csupbsl1_ac;	/* selects for input b of upper csa vector 1 */
	wire	vct_csupcen1_ac;		/* input c enable for upper csa odd vectors */
	wire	vdp_csaupci1_ac;		/* carry in to upper csa vector 1 */
	wire	vdp_addupci1_ac;		/* carry in to upper adder vector 1 */
	wire	vct_incrdwn1_ac;		/* increment/decrement control signal vector 1 */
	wire	vct_incrci1_ac;			/* increment/decrement enable signal vector 1 */
	wire	[1:0]	vct_incrmxsl1_ac;	/* mux select for incrementer output vector 1 */


/*
*	The next group are output control signals for the
*	write back stage of the vector unit datapath.
*/

	wire	[5:0]	vct_rsltsl0_wb;		/* selects for result mux vector 0 */
	wire	[5:0]	vct_rsltsl1_wb;		/* selects for result mux vector 1 */

	wire	[2:0]	vct_clprslt0_wb;	/* clamp value for all clamping vector 0 */
	wire	[2:0]	vct_clprslt1_wb;	/* clamp value for all clamping vector 1 */


/*
*	The following output signals are for addressing the register file only.
*/
   	wire	[31:0]  vct_rfadrt_hi0_wb;	/* decoded wb load high byte address element 0 */
   	wire	[31:0]  vct_rfadrf_hi0_wb;	/* complement decoded wb load high byte address element 0 */
   	wire	[31:0]  vct_rfadrt_lo0_wb;	/* decoded wb load low byte address element 0 */
   	wire	[31:0]  vct_rfadrf_lo0_wb;	/* complement decoded wb load low byte address element 0 */
   	wire	[31:0]  vct_rfadrt_st0_rd;	/* decoded rd store read address element 0 */
   	wire	[31:0]  vct_rfadrf_st0_rd;	/* complement decoded rd store read address element 0 */

   	wire	[31:0]  vct_rfadrt_vs0_rd;	/* decoded rd read vs address element 0 */
   	wire	[31:0]  vct_rfadrf_vs0_rd;	/* complement decoded rf read vs address element 0 */
   	wire	[31:0]  vct_rfadrt_vt0_rd;	/* decoded rd read vt address element 0 */
   	wire	[31:0]  vct_rfadrf_vt0_rd;	/* complement decoded rf read vt address element 0 */
   	wire	[31:0]  vct_rfadrt_vd0_wb;	/* decoded wb write vd address element 0 */
   	wire	[31:0]  vct_rfadrf_vd0_wb;	/* complement decoded wb write vd address element 0 */

   	wire	[31:0]  vct_rfadrt_hi1_wb;	/* decoded wb load high byte address element 1 */
   	wire	[31:0]  vct_rfadrf_hi1_wb;	/* complement decoded wb load high byte address element 1 */
   	wire	[31:0]  vct_rfadrt_lo1_wb;	/* decoded wb load low byte address element 1 */
   	wire	[31:0]  vct_rfadrf_lo1_wb;	/* complement decoded wb load low byte address element 1 */
   	wire	[31:0]  vct_rfadrt_st1_rd;	/* decoded rd store read address element 1 */
   	wire	[31:0]  vct_rfadrf_st1_rd;	/* complement decoded rd store read address element 1 */

   	wire	[31:0]  vct_rfadrt_vs1_rd;	/* decoded rd read vs address element 1 */
   	wire	[31:0]  vct_rfadrf_vs1_rd;	/* complement decoded rf read vs address element 1 */
   	wire	[31:0]  vct_rfadrt_vt1_rd;	/* decoded rd read vt address element 1 */
   	wire	[31:0]  vct_rfadrf_vt1_rd;	/* complement decoded rf read vt address element 1 */
   	wire	[31:0]  vct_rfadrt_vd1_wb;	/* decoded wb write vd address element 1 */
   	wire	[31:0]  vct_rfadrf_vd1_wb;	/* complement decoded wb write vd address element 1 */

/*
*	???? Need to ensure feedthroughs for all signals
*	coming out of the top of the datapath and going 
*	into the bottom.
*/

	assign	vdp_csalwci0_ac =	0 ;
	assign	vdp_csalwci1_ac =	0 ;

/*
*	Removed since busses from both datapaths are now outputs from vusl.
*
*	wire	[15:0]	vdp_hlfout0_rd;
*	wire	[15:0]	vdp_hlfout1_rd;
*
*	wire	[15:0]	vdp_whlout0_rd;
*	wire	[15:0]	vdp_whlout1_rd;
*
*	assign	vdp_hlfout_rd	=	vdp_hlfout1_rd ;
*	assign	vdp_whlout_rd	=	vdp_whlout1_rd ;
*/

	wire	vct_fdalucin0_mu;	/* Fed thru output of datapath for alu carry in */
	wire	vct_fdaddci0_mu;	/* Fed thru output of datapath for addlw carry in */
	wire	vct_fdincrci0_mu;	/* Fed thru output of datapath for incrementer carry in */

	wire	vct_fdalucin1_mu;	/* Fed thru output of datapath for alu carry in */
	wire	vct_fdaddci1_mu;	/* Fed thru output of datapath for addlw carry in */
	wire	vct_fdincrci1_mu;	/* Fed thru output of datapath for incrementer carry in */



vuctl	vuctl1 (	

		.clk				(clk),
		.reset_l			(reset_l),
		.su_instvld_rd			(su_instvld_rd),
		.su_storeinst_rd		(su_storeinst_rd),
		.su_storecfc2_rd		(su_storecfc2_rd), 
		.su_vseqone_rd			(su_vseqone_rd),
		.su_instelem_rd			(su_instelem_rd),
		.su_instfunc_rd			(su_instfunc_rd),
		.su_rdcmpcd_rd			(su_rdcmpcd_rd),
		.su_rdcryout_rd			(su_rdcryout_rd),
		.su_rdcmpcdad_rd		(su_rdcmpcdad_rd),
		.su_wrcmpcd_wb			(su_wrcmpcd_wb),
		.su_wrcryout_wb			(su_wrcryout_wb),
		.su_wrcmpcdad_wb		(su_wrcmpcdad_wb),

		.vdp_vs_sign0_rd		(vdp_vs_sign0_rd),
		.vdp_vs_sign1_rd		(vdp_vs_sign1_rd),

		.vdp_vt_sign0_mu		(vdp_vt_sign0_mu),
		.vdp_vt_sign1_mu		(vdp_vt_sign1_mu),

		.vdp_aluovr0_mu			(vdp_aluovr0_mu),
		.vdp_aluco0_mu			(vdp_aluco0_mu),
		.vdp_vs_zero0_mu		(vdp_vs_zero0_mu),
		.vdp_vt_zero0_mu		(vdp_vt_zero0_mu),
		.vdp_aluzero0_mu		(vdp_aluzero0_mu),
		.vdp_aluone0_mu			(vdp_aluone0_mu),

		.vdp_aluovr1_mu			(vdp_aluovr1_mu),
		.vdp_aluco1_mu			(vdp_aluco1_mu),
		.vdp_vs_zero1_mu		(vdp_vs_zero1_mu),
		.vdp_vt_zero1_mu		(vdp_vt_zero1_mu),
		.vdp_aluzero1_mu		(vdp_aluzero1_mu),
		.vdp_aluone1_mu			(vdp_aluone1_mu),

		.vdp_addlwco0_ac		(vdp_addlwco0_ac),
		.vdp_addlwov0_ac		(vdp_addlwov0_ac),
		.vdp_csupco0_ac			(vdp_csupco0_ac),
		.vdp_addupco0_ac		(vdp_addupco0_ac),

		.vdp_addlwco1_ac		(vdp_addlwco1_ac),
		.vdp_addlwov1_ac		(vdp_addlwov1_ac),
		.vdp_csupco1_ac			(vdp_csupco1_ac),
		.vdp_addupco1_ac		(vdp_addupco1_ac),

		.vmu_co_clal0_ac		(vmu_co_clal0_ac),
		.vmu_co_clal1_ac		(vmu_co_clal1_ac),
		.vmu_co_clah0_ac		(vmu_co_clah0_ac),
		.vmu_co_clah1_ac		(vmu_co_clah1_ac),

		.vdp_acc0bit15_wb		(vdp_acc0bit15_wb),
		.vdp_acc0bit21_wb		(vdp_acc0bit21_wb),
		.vdp_acc0bit31_wb		(vdp_acc0bit31_wb),
		.vdp_acc0bit47_wb		(vdp_acc0bit47_wb),
		.vdp_achizero0_wb		(vdp_achizero0_wb),
		.vdp_acmizero0_wb		(vdp_acmizero0_wb),
		.vdp_achione0_wb		(vdp_achione0_wb),

		.vdp_acc1bit15_wb		(vdp_acc1bit15_wb),
		.vdp_acc1bit21_wb		(vdp_acc1bit21_wb),
		.vdp_acc1bit31_wb		(vdp_acc1bit31_wb),
		.vdp_acc1bit47_wb		(vdp_acc1bit47_wb),
		.vdp_achizero1_wb		(vdp_achizero1_wb),
		.vdp_acmizero1_wb		(vdp_acmizero1_wb),
		.vdp_achione1_wb		(vdp_achione1_wb),

		.vct_regopssl_rd		(vct_regopssl_rd),
		.vct_qurtlosl_rd		(vct_qurtlosl_rd),
		.vct_halflosl_rd		(vct_hlflosl_rd),
		.vct_whllosl_rd			(vct_whllosl_rd),
		.vct_qurthisl_rd		(vct_qurthisl_rd),
		.vct_halfhisl_rd		(vct_hlfhisl_rd),
		.vct_whlhisl_rd			(vct_whlhisl_rd),


		.vct_couprsl_mu			(vct_couprsl_mu),
		.vct_smuprsl_mu			(vct_smuprsl_mu),
		.vct_colwrsl_mu			(vct_colwrsl_mu),
		.vct_smlwrsl0_mu		(vct_smlwrsl0_mu),
		.vct_smlwrsl1_mu		(vct_smlwrsl1_mu),

		.vct_sgnmplr_mu			(vct_sgnmplr_mu),
		.vct_sgnmplcnd_mu		(vct_sgnmplcnd_mu),
		.vct_shftlftone_mu		(vct_shftlftone_mu),

		.vct_aluctl0_mu			(vct_aluctl0_mu),
		.vct_alucin0_mu			(vct_alucin0_mu),
		.vct_compvt0_mu			(vct_compvt0_mu), 

		.vct_aluctl1_mu			(vct_aluctl1_mu),
		.vct_alucin1_mu			(vct_alucin1_mu),
		.vct_compvt1_mu			(vct_compvt1_mu), 

		.vct_aclwsl0_ac			(vct_aclwsl0_ac), 
		.vct_aclwsl1_ac			(vct_aclwsl1_ac), 

		.vct_cslwcsl_ac			(vct_cslwcsl_ac),
		.vct_csupcen0_ac		(vct_csupcen0_ac),
		.vct_csupcen1_ac		(vct_csupcen1_ac),

		.vct_acmisl0_ac			(vct_acmisl0_ac),
		.vct_acmisl1_ac			(vct_acmisl1_ac),

		.vct_acupsl0_ac			(vct_acupsl0_ac), 
		.vct_acupsl1_ac			(vct_acupsl1_ac), 

		.vct_rndvlu0_ac			(vct_rndvlu0_ac),
		.vct_cslwasl0_ac		(vct_cslwasl0_ac),
		.vct_cslwbsl0_ac		(vct_cslwbsl0_ac),
		.vct_addlwci0_ac		(vct_addlwci0_ac),
		.vct_csupasl0_ac		(vct_csupasl0_ac),
		.vct_csupbsl0_ac		(vct_csupbsl0_ac),
		.vct_incrdwn0_ac		(vct_incrdwn0_ac),
		.vct_incrci0_ac			(vct_incrci0_ac),
		.vct_incrmxsl0_ac		(vct_incrmxsl0_ac),

		.vct_rndvlu1_ac			(vct_rndvlu1_ac),
		.vct_cslwasl1_ac		(vct_cslwasl1_ac),
		.vct_cslwbsl1_ac		(vct_cslwbsl1_ac),
		.vct_addlwci1_ac		(vct_addlwci1_ac),
		.vct_csupasl1_ac		(vct_csupasl1_ac),
		.vct_csupbsl1_ac		(vct_csupbsl1_ac),
		.vct_incrdwn1_ac		(vct_incrdwn1_ac),
		.vct_incrci1_ac			(vct_incrci1_ac),
		.vct_incrmxsl1_ac		(vct_incrmxsl1_ac),

		.vct_rsltsl0_wb			(vct_rsltsl0_wb),
		.vct_rsltsl1_wb			(vct_rsltsl1_wb),

		.vct_clprslt0_wb		(vct_clprslt0_wb),
		.vct_clprslt1_wb		(vct_clprslt1_wb),

		.su_storeinst_mu		(su_storeinst_mu),
		.su_storecfc2_mu		(su_storecfc2_mu), 

		.su_cont_to_from		(su_cont_to_from), 

/*
*	The following signals are for register file address decoding
*	only.
*/

		.su_st_rnum_rd			(su_st_rnum_rd),
		.su_xp_rnum_rd			(su_xp_rnum_rd),
		.su_ld_rnum_ac			(su_ld_rnum_ac),
		.su_vs_addr_rd			(su_vs_addr_rd),
		.su_vt_addr_rd			(su_vt_addr_rd),
		.su_vd_addr_ac			(su_vd_addr_ac),
		.su_wbv_wr_en_ac		(su_wbv_wr_en_ac),
		.su_bwe_ac			(su_bwe_ac),
		.su_xposeop_rdac		(su_xposeop_rdac),
		.vct_slice0			(vct_slice0),
		.vct_slice1			(vct_slice1),

		.vct_rfadrt_hi0_wb		(vct_rfadrt_hi0_wb),
		.vct_rfadrf_hi0_wb		(vct_rfadrf_hi0_wb),
		.vct_rfadrt_lo0_wb		(vct_rfadrt_lo0_wb),
		.vct_rfadrf_lo0_wb		(vct_rfadrf_lo0_wb),
		.vct_rfadrt_st0_rd		(vct_rfadrt_st0_rd),
		.vct_rfadrf_st0_rd		(vct_rfadrf_st0_rd),
		.vct_rfadrt_vs0_rd		(vct_rfadrt_vs0_rd),
		.vct_rfadrf_vs0_rd		(vct_rfadrf_vs0_rd), 
		.vct_rfadrt_vt0_rd		(vct_rfadrt_vt0_rd),
		.vct_rfadrf_vt0_rd		(vct_rfadrf_vt0_rd),
		.vct_rfadrt_vd0_wb		(vct_rfadrt_vd0_wb),
		.vct_rfadrf_vd0_wb		(vct_rfadrf_vd0_wb),

		.vct_rfadrt_hi1_wb		(vct_rfadrt_hi1_wb),
		.vct_rfadrf_hi1_wb		(vct_rfadrf_hi1_wb),
		.vct_rfadrt_lo1_wb		(vct_rfadrt_lo1_wb),
		.vct_rfadrf_lo1_wb		(vct_rfadrf_lo1_wb),
		.vct_rfadrt_st1_rd		(vct_rfadrt_st1_rd),
		.vct_rfadrf_st1_rd		(vct_rfadrf_st1_rd),
		.vct_rfadrt_vs1_rd		(vct_rfadrt_vs1_rd),
		.vct_rfadrf_vs1_rd		(vct_rfadrf_vs1_rd), 
		.vct_rfadrt_vt1_rd		(vct_rfadrt_vt1_rd),
		.vct_rfadrf_vt1_rd		(vct_rfadrf_vt1_rd),
		.vct_rfadrt_vd1_wb		(vct_rfadrt_vd1_wb),
		.vct_rfadrf_vd1_wb		(vct_rfadrf_vd1_wb)


		);



vudp	vudp0 (
		.vdpstoredatargrf_cp		(clk),
		.vdpregoptrf_cp			(clk),
		.vdpregopsrf_cp			(clk),

	        .vdpsumlwrmu_cp			(clk),
		.vdpcoutlwrmu_cp		(clk),
		.vdpsumuprmu_cp			(clk),
		.vdpcoutuprmu_cp		(clk),

	        .vdpaccumlwrac_cp		(clk),
	        .vdpaccummidac_cp		(clk),
		.vdpaccumuprac_cp		(clk),


		.vdpregfile_ral			(vct_rfadrt_vt0_rd[15:0]),
		.vdpregfile_rah			(vct_rfadrt_vt0_rd[31:16]),
		.vdpregfile_ralb		(vct_rfadrf_vt0_rd[15:0]),
		.vdpregfile_rahb		(vct_rfadrf_vt0_rd[31:16]),

		.vdpregfile_rbl			(vct_rfadrt_vs0_rd[15:0]),
		.vdpregfile_rbh			(vct_rfadrt_vs0_rd[31:16]),
		.vdpregfile_rblb		(vct_rfadrf_vs0_rd[15:0]),
		.vdpregfile_rbhb		(vct_rfadrf_vs0_rd[31:16]),

		.vdpregfile_rcl			(vct_rfadrt_st0_rd[15:0]),
		.vdpregfile_rch			(vct_rfadrt_st0_rd[31:16]),
		.vdpregfile_rclb		(vct_rfadrf_st0_rd[15:0]),
		.vdpregfile_rchb		(vct_rfadrf_st0_rd[31:16]),

		.vdpregfile_w1lx		(vct_rfadrt_lo0_wb[15:0]),
		.vdpregfile_w1ly		(vct_rfadrt_hi0_wb[15:0]),
		.vdpregfile_w1hx		(vct_rfadrt_lo0_wb[31:16]),
		.vdpregfile_w1hy		(vct_rfadrt_hi0_wb[31:16]),

		.vdpregfile_w1lxb		(vct_rfadrf_lo0_wb[15:0]),
		.vdpregfile_w1lyb		(vct_rfadrf_hi0_wb[15:0]),
		.vdpregfile_w1hxb		(vct_rfadrf_lo0_wb[31:16]),
		.vdpregfile_w1hyb		(vct_rfadrf_hi0_wb[31:16]),

		.vdpregfile_w0l			(vct_rfadrt_vd0_wb[15:0]),
		.vdpregfile_w0h			(vct_rfadrt_vd0_wb[31:16]),
		.vdpregfile_w0lb		(vct_rfadrf_vd0_wb[15:0]),
		.vdpregfile_w0hb		(vct_rfadrf_vd0_wb[31:16]),


		.vdpregopsrf			(vct_regopssl_rd),

		.vdpsclrmxqurtrf		(vct_qurtlosl_rd),
		.vdpsclrmxhalfrf		(vct_hlfsl0_rd),
	        .vdpsclrmxwhlrf			(vct_whlsl0_rd),

		.vdpsclrqurtinrf		(vdp_opndt1_rd),
	        .vdpsclrhlfinrf			(vdp_hlfin0_rd),
		.vdpsclrwhlinrf			(vdp_whlin0_rd),


		.vdpcoutlwrmu			(vct_colwrsl_mu),
		.vdpsumlwrmu			(vct_smlwrsl0_mu),
		.vdpcoutuprmu			(vct_couprsl_mu),
		.vdpsumuprmu			(vct_smuprsl_mu),

		.vdpalumu			(vct_aluctl0_mu),

		.vumsumlowermu			(vmu_sumlower0_mu),
		.vumcarrylowermu		(vmu_carrylower0_mu),
		.vumsumuppermu			(vmu_sumupper0_mu),
		.vumcarryuppermu		(vmu_carryupper0_mu),

		.vdpcompvtmu			(vct_compvt0_mu), 


		.vdprundvluac			(vct_rndvlu0_ac),

		.vdpcsalwrainac			(vct_cslwasl0_ac),
		.vdpcsalwrbinac			(vct_cslwbsl0_ac),
		.vdpcsalwrcinac			(vct_cslwcsl_ac),
		.vdpcsauprcinnandac		(vct_csupcen0_ac),

		.vdpcsalwrac_cin		(vdp_csalwci0_ac),

		.vdpaccumlwrac			(vct_aclwsl0_ac),

		.vdpcsauprainac			(vct_csupasl0_ac),
	        .vdpcsauprbinac			(vct_csupbsl0_ac),

		.vdpfeedalucimu_top		(vct_alucin0_mu),
		.vdpfeedalucimu_bot		(vct_fdalucin0_mu),
		.vdpalumu_cin			(vct_fdalucin0_mu),

	        .vdpcsalwrac_cout		(vdp_cslwco0_ac),
		.vdpfeedcsaac_top		(vdp_cslwco0_ac),
		.vdpfeedcsaac_bot		(vdp_csaupci0_ac),
	        .vdpcsauprac_cin		(vdp_csaupci0_ac),

		.vdpfeedaddciac_top		(vct_addlwci0_ac),
		.vdpfeedaddciac_bot		(vct_fdaddci0_ac),
		.vdpadderlwrac_cin		(vct_fdaddci0_ac),

	        .vdpadderlwrac_cout		(vdp_addlwco0_ac),
		.vdpfeedaddcoac_top		(vdp_addlwco0_ac),
		.vdpfeedaddcoac_bot		(vdp_addupci0_ac),
		.vdpadderuprac_cin		(vdp_addupci0_ac),

		.vdpfeedincrciac_top		(vct_incrci0_ac),
		.vdpfeedincrciac_bot		(vct_fdincrci0_ac),
	        .vdpincremac_cin		(vct_fdincrci0_ac),

		.vdpaccummidac			(vct_acmisl0_ac),

	        .vdpincremac_dwn		(vct_incrdwn0_ac),
		.vdpincremxac			(vct_incrmxsl0_ac),
 
	        .vdpaccuprmxac			(vct_acupsl0_ac),


		.vdpslctmxwb			(vct_rsltsl0_wb),
		.vdpclprsltwb			(vct_clprslt0_wb),
		.vdpdivrsltwb			(vdi_divrslt0_wb),


		.vdpopssignrf			(vdp_vs_sign0_rd),

		.vdpoperandtrf			(vdp_opndt0_rd),
		.vdpsclrhlfoutrf		(vdp_hlfout0_rd),
		.vdpsclrwhloutrf		(vdp_whlout0_rd),

		.vdpdatatristen			(vdp_datatristen0_mu),
		.vdpstoredatamu			(su_data_to_from[31:16]),
		.vdpoptsignmu			(vdp_vt_sign0_mu),
	        .vdpalumu_ovr			(vdp_aluovr0_mu),
		.vdpalumu_cout			(vdp_aluco0_mu),
		.vdpzerodetvsmu_z		(vdp_vs_zero0_mu),
		.vdpzerodetvtmu_z		(vdp_vt_zero0_mu),
		.vdpzerodetalumu_z		(vdp_aluzero0_mu),
		.vdponedetalumu_z		(vdp_aluone0_mu),

		.vdpmplcndmu			(vdp_mplcnd0_mu),
		.vdpmplrmu			(vdp_mplr0_mu),


		.vdpadderlwrac_ovr		(vdp_addlwov0_ac),
		.vdpcsauprac_cout		(vdp_csupco0_ac),
	        .vdpadderuprac_cout		(vdp_addupco0_ac),
		.vdpadderuprac_ovr		(vdp_addupov0_ac),
		.vdpincremac_cout		(vdp_incrco0_ac),

		.vdpaccmidzerowb_z		(vdp_acmizero0_wb),
		.vdpacchighzerowb_z		(vdp_achizero0_wb),
		.vdpacchighonewb_z		(vdp_achione0_wb),

		.vdpaccsign15wb			(vdp_acc0bit15_wb),
		.vdpaccsign21wb			(vdp_acc0bit21_wb),
		.vdpaccsign31wb			(vdp_acc0bit31_wb),
		.vdpaccsign47wb			(vdp_acc0bit47_wb)

	      );


vmult	vmult0 (
		.clk				(clk),
		.vum_mplcnd_mu			(vdp_mplcnd0_mu),
		.vum_mplr_mu			(vdp_mplr0_mu),
		.vum_sgnmplcnd_mu		(vct_sgnmplcnd_mu),
		.vum_sgnmplr_mu			(vct_sgnmplr_mu),
		.vum_shiftleft1_mu		(vct_shftlftone_mu),

		.vum_carryupper_mu		(vmu_carryupper0_mu),
		.vum_carrylower_mu		(vmu_carrylower0_mu),
		.vum_sumupper_mu		(vmu_sumupper0_mu),
		.vum_sumlower_mu		(vmu_sumlower0_mu),

		.vum_col_cla_acc		(vmu_co_clal0_ac),
		.vum_coh_cla_acc		(vmu_co_clah0_ac)
	       );


vudp	vudp1 (
		.vdpstoredatargrf_cp		(clk),
		.vdpregoptrf_cp			(clk),
		.vdpregopsrf_cp			(clk),

	        .vdpsumlwrmu_cp			(clk),
		.vdpcoutlwrmu_cp		(clk),
		.vdpsumuprmu_cp			(clk),
		.vdpcoutuprmu_cp		(clk),

	        .vdpaccumlwrac_cp		(clk),
	        .vdpaccummidac_cp		(clk),
		.vdpaccumuprac_cp		(clk),


		.vdpregfile_ral			(vct_rfadrt_vt1_rd[15:0]),
		.vdpregfile_rah			(vct_rfadrt_vt1_rd[31:16]),
		.vdpregfile_ralb		(vct_rfadrf_vt1_rd[15:0]),
		.vdpregfile_rahb		(vct_rfadrf_vt1_rd[31:16]),

		.vdpregfile_rbl			(vct_rfadrt_vs1_rd[15:0]),
		.vdpregfile_rbh			(vct_rfadrt_vs1_rd[31:16]),
		.vdpregfile_rblb		(vct_rfadrf_vs1_rd[15:0]),
		.vdpregfile_rbhb		(vct_rfadrf_vs1_rd[31:16]),

		.vdpregfile_rcl			(vct_rfadrt_st1_rd[15:0]),
		.vdpregfile_rch			(vct_rfadrt_st1_rd[31:16]),
		.vdpregfile_rclb		(vct_rfadrf_st1_rd[15:0]),
		.vdpregfile_rchb		(vct_rfadrf_st1_rd[31:16]),

		.vdpregfile_w1lx		(vct_rfadrt_lo1_wb[15:0]),
		.vdpregfile_w1ly		(vct_rfadrt_hi1_wb[15:0]),
		.vdpregfile_w1hx		(vct_rfadrt_lo1_wb[31:16]),
		.vdpregfile_w1hy		(vct_rfadrt_hi1_wb[31:16]),

		.vdpregfile_w1lxb		(vct_rfadrf_lo1_wb[15:0]),
		.vdpregfile_w1lyb		(vct_rfadrf_hi1_wb[15:0]),
		.vdpregfile_w1hxb		(vct_rfadrf_lo1_wb[31:16]),
		.vdpregfile_w1hyb		(vct_rfadrf_hi1_wb[31:16]),

		.vdpregfile_w0l			(vct_rfadrt_vd1_wb[15:0]),
		.vdpregfile_w0h			(vct_rfadrt_vd1_wb[31:16]),
		.vdpregfile_w0lb		(vct_rfadrf_vd1_wb[15:0]),
		.vdpregfile_w0hb		(vct_rfadrf_vd1_wb[31:16]),


		.vdpregopsrf			(vct_regopssl_rd),

		.vdpsclrmxqurtrf		(vct_qurthisl_rd),
		.vdpsclrmxhalfrf		(vct_hlfsl1_rd),
	        .vdpsclrmxwhlrf			(vct_whlsl1_rd),

		.vdpsclrqurtinrf		(vdp_opndt0_rd),
	        .vdpsclrhlfinrf			(vdp_hlfin1_rd),
		.vdpsclrwhlinrf			(vdp_whlin1_rd),


		.vdpcoutlwrmu			(vct_colwrsl_mu),
		.vdpsumlwrmu			(vct_smlwrsl1_mu),
		.vdpcoutuprmu			(vct_couprsl_mu),
		.vdpsumuprmu			(vct_smuprsl_mu),

		.vdpalumu			(vct_aluctl1_mu),

		.vumsumlowermu			(vmu_sumlower1_mu),
		.vumcarrylowermu		(vmu_carrylower1_mu),
		.vumsumuppermu			(vmu_sumupper1_mu),
		.vumcarryuppermu		(vmu_carryupper1_mu),

		.vdpcompvtmu			(vct_compvt1_mu), 


		.vdprundvluac			(vct_rndvlu1_ac),

		.vdpcsalwrainac			(vct_cslwasl1_ac),
		.vdpcsalwrbinac			(vct_cslwbsl1_ac),
		.vdpcsalwrcinac			(vct_cslwcsl_ac),
		.vdpcsauprcinnandac		(vct_csupcen1_ac),

		.vdpcsalwrac_cin		(vdp_csalwci1_ac),

		.vdpaccumlwrac			(vct_aclwsl1_ac),

		.vdpcsauprainac			(vct_csupasl1_ac),
	        .vdpcsauprbinac			(vct_csupbsl1_ac),


		.vdpfeedalucimu_top		(vct_alucin1_mu),
		.vdpfeedalucimu_bot		(vct_fdalucin1_mu),
		.vdpalumu_cin			(vct_fdalucin1_mu),

	        .vdpcsalwrac_cout		(vdp_cslwco1_ac),
		.vdpfeedcsaac_top		(vdp_cslwco1_ac),
		.vdpfeedcsaac_bot		(vdp_csaupci1_ac),
	        .vdpcsauprac_cin		(vdp_csaupci1_ac),

		.vdpfeedaddciac_top		(vct_addlwci1_ac),
		.vdpfeedaddciac_bot		(vct_fdaddci1_ac),
		.vdpadderlwrac_cin		(vct_fdaddci1_ac),

	        .vdpadderlwrac_cout		(vdp_addlwco1_ac),
		.vdpfeedaddcoac_top		(vdp_addlwco1_ac),
		.vdpfeedaddcoac_bot		(vdp_addupci1_ac),
		.vdpadderuprac_cin		(vdp_addupci1_ac),

		.vdpfeedincrciac_top		(vct_incrci1_ac),
		.vdpfeedincrciac_bot		(vct_fdincrci1_ac),
	        .vdpincremac_cin		(vct_fdincrci1_ac),

		.vdpaccummidac			(vct_acmisl1_ac),

	        .vdpincremac_dwn		(vct_incrdwn1_ac),
		.vdpincremxac			(vct_incrmxsl1_ac),

	        .vdpaccuprmxac			(vct_acupsl1_ac),

		.vdpslctmxwb			(vct_rsltsl1_wb),
		.vdpclprsltwb			(vct_clprslt1_wb),
		.vdpdivrsltwb			(vdi_divrslt1_wb),


		.vdpopssignrf			(vdp_vs_sign1_rd),

		.vdpoperandtrf			(vdp_opndt1_rd),
		.vdpsclrhlfoutrf		(vdp_hlfout1_rd),
		.vdpsclrwhloutrf		(vdp_whlout1_rd),

		.vdpdatatristen			(vdp_datatristen1_mu),
		.vdpstoredatamu			(su_data_to_from[15:0]),
		.vdpoptsignmu			(vdp_vt_sign1_mu),
	        .vdpalumu_ovr			(vdp_aluovr1_mu),
		.vdpalumu_cout			(vdp_aluco1_mu),
		.vdpzerodetvsmu_z		(vdp_vs_zero1_mu),
		.vdpzerodetvtmu_z		(vdp_vt_zero1_mu),
		.vdpzerodetalumu_z		(vdp_aluzero1_mu),
		.vdponedetalumu_z		(vdp_aluone1_mu),

		.vdpmplcndmu			(vdp_mplcnd1_mu),
		.vdpmplrmu			(vdp_mplr1_mu),


		.vdpadderlwrac_ovr		(vdp_addlwov1_ac),
		.vdpcsauprac_cout		(vdp_csupco1_ac),
	        .vdpadderuprac_cout		(vdp_addupco1_ac),
		.vdpadderuprac_ovr		(vdp_addupov1_ac),
		.vdpincremac_cout		(vdp_incrco1_ac),

		.vdpaccmidzerowb_z		(vdp_acmizero1_wb),
		.vdpacchighzerowb_z		(vdp_achizero1_wb),
		.vdpacchighonewb_z		(vdp_achione1_wb),

		.vdpaccsign15wb			(vdp_acc1bit15_wb),
		.vdpaccsign21wb			(vdp_acc1bit21_wb),
		.vdpaccsign31wb			(vdp_acc1bit31_wb),
		.vdpaccsign47wb			(vdp_acc1bit47_wb)

	      );


vmult	vmult1 (
		.clk				(clk),
		.vum_mplcnd_mu			(vdp_mplcnd1_mu),
		.vum_mplr_mu			(vdp_mplr1_mu),
		.vum_sgnmplcnd_mu		(vct_sgnmplcnd_mu),
		.vum_sgnmplr_mu			(vct_sgnmplr_mu),
		.vum_shiftleft1_mu		(vct_shftlftone_mu),

		.vum_carryupper_mu		(vmu_carryupper1_mu),
		.vum_carrylower_mu		(vmu_carrylower1_mu),
		.vum_sumupper_mu		(vmu_sumupper1_mu),
		.vum_sumlower_mu		(vmu_sumlower1_mu),

		.vum_col_cla_acc		(vmu_co_clal1_ac),
		.vum_coh_cla_acc		(vmu_co_clah1_ac)
	       );



endmodule