div.ss
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/* setup aliases */
alias set_default_operating_conditions "set_operating_conditions NOM -library rcp.db; \
set_wire_load 128000 -mode top;"
alias set_default_timing_constraints "create_clock CLK -period 15.0 -waveform {0 7.5}; \
set_input_delay 2.0 -clock CLK all_inputs(); \
set_output_delay 2.0 -clock CLK all_outputs(); \
max_delay 12.0 -to all_outputs(); \
set_clock_skew -uncertainty 1 CLK; \
fix_hold CLK; \
dont_touch_network CLK; \
set_output_delay 2.0 -clock CLK all_outputs(); \
set_driving_cell -cell in01d1 all_inputs(); \
set_driving_cell -cell ni01d3 VTH; \
set_driving_cell -cell ni01d3 VTL; \
set_drive 0 {CLK}; \
set_load 2 all_outputs();"
/* read the verilog sources */
read -f verilog ../src/div.v
read -f verilog ../src/fake_div_rom.v
read -f edif divctl.edf
current_design = div
set_default_operating_conditions
set_default_timing_constraints
link
check_design > div.lint
report -net > div.rn
write -f edif -o div.edf -hier div
quit