divctl.ss
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/* setup aliases */
alias set_default_operating_conditions "set_operating_conditions NOM -library rcp.db; \
set_wire_load 128000 -mode top;"
alias set_default_timing_constraints "create_clock CLK -period 15.0 -waveform {0 7.5}; \
set_input_delay 2.0 -clock CLK all_inputs(); \
max_delay 12.0 -to all_outputs(); \
set_clock_skew -uncertainty 1 CLK; \
fix_hold CLK; \
dont_touch_network CLK; \
set_output_delay 2.0 -clock CLK all_outputs(); \
set_driving_cell -cell in01d1 all_inputs(); \
set_driving_cell -cell ni01d3 VTH; \
set_driving_cell -cell ni01d3 VTL; \
set_drive 0 {CLK}; \
set_load 0.2 all_outputs(); \
set_load 2 DivOut;"
/* read the verilog sources */
read -f verilog ../src/divctl.v
current_design = divctl
ungroup -flatten u_inc*
ungroup -flatten u_data_mux
dont_touch u_*
max_fanout 16
set_default_operating_conditions
set_default_timing_constraints
max_area 1500
set_max_transition 2.0 current_design;
set_input_delay 8.0 -clock CLK Reset_l;
set_input_delay 8.0 -clock CLK OpCode[*];
set_input_delay 8.0 -clock CLK OpCodeValid;
set_input_delay 8.0 -clock CLK El2;
set_input_delay 13.0 -clock CLK VTL[*];
set_input_delay 13.0 -clock CLK VTH[*];
set_input_delay 12.0 -clock CLK ROMData[*];
set_max_fanout 0.02 {Reset_l}
max_delay 7.0 -to DivOut[*];
link
check_design > divctl.lint
compile -map_effort high -incremental_mapping
compile -map_effort high -incremental_mapping
report -reference > report/divctl.ref
report_area > report/divctl.area
report_constraint -all_violators > report/divctl.violators
report_timing -path full -delay max -max_paths 10 > report/divctl.full.paths
report_clock > report/divctl.clock
report -reference
report_constraint -all_violators
report_timing -path full -from VT*[15] -delay max -max_paths 2;
report_timing -path full -from OpCode[*] -delay max -max_paths 2;
report_timing -path full -from OpCodeValid -delay max -max_paths 2;
report_timing -path full -to RADDR[*] -delay max -max_paths 2;
report_timing -path full -delay max -max_paths 10;
report -net > divctl.rn
write -f edif -o divctl.edf -hier divctl
/* write -f verilog -o divctl.vsyn -hier divctl */
quit